International Conference on Computing, Communication and Automation (ICCCA2016)

Implementation of an Efficient Multiplier Using the

Vedic Multiplication Algorithm
Paras Gulati, Harsh Yadav and Manoj KumarTaleja
UniversitySchool of Information and Communication
Technology, GuruGobindSinghIndraprasthaUniversity,
New Delhi, India
parasgulati8@gmail.com

AbstractThis paper proposes the implementation of an ancient

Indian Vedic multiplier using the 16 bit modified carry select
adder, 16 bit ripple carry adder and 16 bit kogge stone adder.
The modified carry select adder shows the improved speed
performance with less time delay. The design has been
implemented using Verilog hardware description language. The
design code is tested using theModelsim simulator. The code is
synthesized using Virtex-7 family. The Virtex-7 family is based
on 28nm design which has 50 percent lower power compared to
the previous generation Virtex-6. The paper makes a comparison
of the performance of 16 bit Vedic multiplier using three
different adders modified carry select adder, ripple carry adder
and kogge stone adder. Results shows that the 16 bit Vedic
multiplier using modified carry select adder is better in terms of
power consumption and speed as compared to the other two 16
bit Vedic multipliers.

Keywords Modified carry select adder, vedic multiplier, ripple

carry adder, Kogge stone adder, binary to excess-1 converter
(BEC).

Fig. 1. Vedic multiplication of two decimal numbers

I. INTRODUCTION
The Vedic multiplier has a wide application and is used as key
element in most of the Arithmetic Logic Unit (ALU). It is an
ancient multiplication technique which reduces the tedious
calculation to a simpler one. Power consumption and delay are
the prime performance indicators in any VLSI circuit design.
High speed processors are required for many applications so
there is a great need for high speed multiplier circuits. The
reduction in time delay and power consumption is the prime
objective for the high speed processors. The Vedic multiplier
has applications in fast fourier transform, filtering,
convolution, communications and digital signal processing
[1]. The Vedic multiplication technique is time efficient
technique with increased speed and requires less hardware.The
ancient Vedic mathematics comprises of the 16 sutras where
each sutra represents the different branch of mathematics.
II. MULTIPLICATION OF TWO DECIMAL NUMBERS BY VEDIC
MATHEMATICS
To begin, let us take two three digit numbers 386 and 512.
The product of the two decimal numbers using the Vedic
multiplication technique is illustrated in Fig1. The
multiplication begins by first multiplying the two digits
connected through the line. Then, the first digit of the product
is stored as the first digit of result and the remaining digit is
the carry for the next stage. In the next stage of multiplication
again the digits connected to each other through the line are
multiplied and the individual products obtained are added to
the carry from the previous stage. Then, again the first digit of
the sum obtained is stored as the second digit of the result and
the remaining digit is the carry for the next stage. [2]-[4]. This
process is repeated again and again and thus the final result i.e.
the product of the two numbers 386 x 512 is obtained through
the Vedic multiplication technique as shown in Fig. 1.
III. ADDERS
Adders perform the function of adding two numbers [5].
The adders have a variety of use in processors, ALU and many
other applications.
A. Modified Carry Select Adder
The modified carry select adder is used as an alternative of
the ripple carry adder because it incorporates a binary to
excess-1 converter (BEC) as shown in Fig. 2, to reduce the
time delay and the area occupied in contrast to the ripple carry
adder. The performance of the modified carry select adder is

ISBN:978-1-5090-1666-2/16/$31.00 2016 IEEE 1440

 International Conference on Computing, Communication and Automation (ICCCA2016)

C. Kogge Stone Adder

Fig. 2. Binary to Excess-1 Converter, usedin designing the modified carry

select adder.

better as compared to the ripple carry adder and the kogge

stone adder [6].

The logic equations for the binary to excess-1 converter are:

N0 =~ M0
N1 = M0 ^ M1
N2 = M2 ^ (M0 &M1)
N3 = M3 ^ (M0 &M1 &M2)

B. Ripple Carry Adder

The ripple carry adder involves multiple full adders which are
cascaded in parallel for adding an N-bit number. In this adder,
the carry generated from the previous stage gets rippled into
the next stage. The block diagram representing a 4 bitripple
carry adder is shown in Fig. 3, which involves four full adders
and the carry generated is sent to the next stage for
computation [7]. Fig. 4. Kogge stone adder

The kogge stone adder is a high performance adder. It is a

parallel prefix form carry look-ahead adder which can
generate the carry signals in O(log t) time. In this adder, each
vertical stage produces a propagate and a generate. The
concept of kogge stone adder was evolved by Peter M. Kogge
and Harold S. Stone. The block diagram representing the
kogge stone adder [8] is shown in Fig. 4.

IV. TYPES OF MULTIPLIERS

Fig. 3. A 4- bitripple carry adder
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A. 16 X 16 Vedic Multiplier Using Modified Carry Select
Adder
This section describes the 16 x 16 Vedic multiplier using
ripple carry adder. The block diagram is shown in Fig. 5. In
this multiplier four 8 bit Vedic multipliers and three 16 bit
modified carry select adders have been used. Consider the
process of multiplication by taking two numbers X and Y each
of 16 bits. The two numbers X[15:0] and Y [15:0] are
multiplied as per the diagram shown in Fig 5and the final
product is obtained. The carry generated by each stage is fed
to the next stage as per the block diagramshown in Fig. 5. In
 International Conference on Computing, Communication and Automation (ICCCA2016)
this way the time delay gets reduced.
Fig. 5. Block diagram representing 16 x 16 Vedic multiplier using modified
carry select adder
B. 16 X 16 Vedic Multiplier Using Ripple Carry Adder
This section describes the 16 x 16 Vedic multiplier using
ripple carry adder. The block diagram is manifested in Fig. 6.
The ripple carry adder uses multiple adders for its design.This
multiplier uses three 16 bit adders and four 8 bit Vedic
multipliers. The carry from the last stage is fed as input to the
next stage [7]. The adder has a simple design but it is
relatively slow than the modified carry select adder due to the
time delay that is involved in transferring the carry generated
by the previous stage to the next stage. Therefore, this is the
reason for more time delay in case of the ripple carry adder.
The inputs are fed as per the block diagram shown in Fig. 6,
and thus the product of the inputs X and Y is generated at the
output.
Fig. 6. Block diagram representing 16 x 16 Vedic multiplier using ripple
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carry adder
C. 16 X 16 Vedic Multiplier Using Kogge Stone Adder
Fig. 7. Block diagram representing 16 x 16 Vedic multiplier using kogge
stone adder
This section describes the 16 x 16 Vedic multiplier using
kogge stone adder. The block diagram is shown in Fig. 7. The
16 x 16 Vedic Multiplier using kogge stone adder consists of
three 16 bit Kogge stone adders and four 8 bit Vedic
multipliers. The kogge stone adder is faster as compared to the
other adders. The two 16 bit inputs X and Y are fed as per the
diagram shown in Fig. 7, and the result obtained is the product
of the two inputs X and Y.
V. RESULT AND DISCUSSIONS
The 16 x 16 Vedic multiplier using modified carry select
adder, ripple carry adder and the kogge stone adder were
designed using Verilog hardware description language. The
Virtex-7 family has been used with the XC 7VX330T device.
The simulation is performed in Modelsim. Table 1 represents
the comparison of number of LUTs, maximum combinational
path delay and maximum output required time after clock for
the Vedic multiplier using the threeadders. The results show
that the 16 bit Vedic Multiplier using modified carry select
adder uses 34.60 % and 51.62 %less path delayas compared to
the 16 bit Vedic multiplier usingkogge stone adder and ripple
carry adder respectively.Further, modified carry select adder
shows the 38.74 % and 56.45 % less maximum output
required time after clock as compared to the 16 bit Vedic
multiplier usingkogge stone adder and ripple carry adder
respectively. Table 2 represents the comparison of power for
the Vedic multipliers using all three adders. The 16 bit Vedic
multiplier using modified carry select adder uses8.20% less
power as compared to the 16 bit Vedic multiplier using kogge
stone adder and 14.1 % t less power as compared to the 16 bit
Vedic multiplier usingripple carry adder.
 International Conference on Computing, Communication and Automation (ICCCA2016)

TABLE 2.POWER AND MEMORY USAGE COMPARISON

Vedic Multiplier Total Power Peak Memory

(mW) Usage (MB)
Using Modified Carry 142.92 978
Select Adder

Using Ripple carry 166.38 1012

adder
Using Kogge Stone 155.69 998
Fig. 8. Simulation results of 16 x 16 Vedic multiplier using modified carry Adder
select adder

VI. CONCLUSION
The 16 x 16 Vedic multiplier using modified carry select
adder shows lesser power consumption and peak memory
usage as compared to the same multiplier usingripple carry
adder and kogge stone adder. The time delay involved in the
16 x 16 Vedic multiplier using modified carry select adder is
also less as compared to the time delays of the other two 16 x
16 Vedic multipliers. The 16 bit Vedic Multiplier using
modified carry select adder uses 34.60 % and 51.62 % less
path delayas compared to the 16 bit Vedic multiplier
usingkogge stone.The 16 bit Vedic multiplier using modified
Fig. 9. Simulation results of 16 x 16 Vedic multiplier using ripple carry adder
carry select adderconsumes 8.20% less power as compared to
design withkogge stone adder and 14.1 % less power as
compared to the designwith ripple carry adder. Therefore, it
has an enhanced speed and can be used in the DSP
applications and in processors for faster computations.

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