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Tessent TestKompress Silicon Test and Yield Analysis

ATPG with Embedded Compression D A T A S H E E T

Tessent TestKompress uses Key Benefits

embedded deterministic test Provides thorough testing of
technology to achieve the
digital logic with scan-based
highest level of test quality
while reducing test time and
test data volume. Reduce both test time and data
volume as much as 100X.
Provides fast pattern gen-
eration through high-perfor-
mance ATPG and distributed
Mentor Graphics award-
winning customer support
ensures success.

Key Features
Industry Leading Scan Test Tool A wide variety of fault mod-
The Mentor Graphics Tessent TestKompress industry-leading automatic test els, including stuck-at, transi-
pattern generation (ATPG) solution delivers the highest quality scan test with the tion, path delay, and multiple-
lowest manufacturing test cost. The foundation of Tessent TestKompress is the detect provide a thorough
industry-proven ATPG engine that is able to apply all the fault models necessary silicon test.
for thorough silicon test. Supports low pin count test
strategies (as few as one scan
Reduced Test Time channel).
The patented embedded deterministic test (EDT) technology incorporated into Scan debug environment for
Tessent TestKompress reduces both test time and data volume without any loss in quick troubleshooting.
test coverage. Consistent compression levels, regardless of design architecture are
Tightly integrated with yield
achieved by effective X masking without the need for X bounding, test points, or
diagnosis and analysis tools:
any other design modifications.
Tessent Diagnosis and Tessent
The main components of EDT logic (decompressor and compactor) are part of
the scan path only, so functional timing closure is not affected. EDT logic can be Supported in the Tessent
generated in all design flows and is independent of synthesis tools. The EDT logic SoCScan hierarchical silicon
can be added at a designs top level or used in a modular configuration by placing test environment.
the decompressor and compactor into each block of the design. Award-winning technology:
2001 Electronic Products
Highest Coverage for Advanced Designs Product of the Year, 2002
Tessent TestKompress uses industry-proven fault models to uncover the most Test & Measurement Worlds
subtle defects. The tool supports standard stuck-at fault models for targeting static Best-in-Test, 2006 IEEE
failures as well as the necessary advanced fault models such as transition models Donald O. Pederson Best
for uncovering dynamically activated defects. Bridges and opens can be specifi- Paper, and 2009 Test &
cally targeted by advanced fault models intended for small geometry designs. Measurement World Test of
It supports accurate at-speed clock edges and both launch-off-shift and capture Time finalist.
transition fault application.
Tessent TestKompress provides several options to target
bridge defects. A multiple detect/N-detect fault model targets
bridging faults that result from random particles. Embedded
multiple detect (EMD) test can be used without increasing
the pattern count. The physical bridge fault model targets
feature-dependent bridge defects whose candidates can be
directly extracted from the physical layout with Calibre
nmLVS. Timing-aware ATPG can be used to selectively test
the most critical paths.

Tessent TestKompress X masking capability provides X

tolerance while maintaining high test coverage. False and
multicycle paths are a major source of X states during at-
speed test. X masking intelligently handles these paths by
reading the SDC file and masking as necessary, resulting in
more effective test coverage, higher levels of compression, Interface for viewing and correcting testability problems.
and stable patterns on the tester.

Named capture procedures provide a powerful means of sup- detailed analysis of untestable faults and classifies them into
porting the generation of accurate at-speed clock pulses with recognizable categories that simplify the debugging of low
the on-chip PLL. test coverage issues.

More Efficient Use of Tester and I/O Pins Hierarchical Logic Test Strategy
Compressed patterns generated by Tessent TestKompress with Tessent SoCScan
operate the same on the tester as standard ATPG patterns, Tessent TestKompress can be used with Tessent SoCScan
but with a reduction in test data volume and test time. As to take advantage of the Mentor Graphics automated hier-
few as a single scan channel can be used to ease issues with archical test integration and test generation flow. Tessent
routing and external I/O. Dual channel configuration capabil- SoCScan makes use of shared isolation and capture-by-
ity provides flexibility to support different testers. This is domain technologies to deliver independent core-level ATPG
especially useful in manufacturing test flows that use low- and chip-level pattern reuse. Tessent SoCScan also provides
pin-count testers or multi-site testing. access to BurstMode technology for higher at-speed test
coverage and improved power managment.
Testability Analysis and Debug
A visual debug utility is integrated within Tessent TestKom- Tessent Silicon Test
press for viewing and correcting testability problems. Visual- and Yield Analysis Solutions
izer presents the design in various views such as schematic, Tessent TestKompress is part of the Mentor Graphics
design structure, waveform, library, data, hierarchy, and industry- and technology-leading tool suite for silicon test
additional views to facilitate viewing and troubleshooting. and yield analysis. The Tessent suite includes integrated
solutions for test insertion; ATPG; on-chip compression;
The intuitive interface built into Visualizer also allows view-
memory, logic, and mixed-signal built-in self-test (BIST);
ing of the session transcript which includes active links for
silicon bring-up, and diagnosis-driven yield analysis. All
design rule violations, logic displays, file editing, documen-
Tessent tools are available on UNIX and Linux. For more
tation, and gate callouts. ATPG statistics reporting provides
information, visit

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All other trademarks mentioned in this document are trademarks of their respective owners.

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