Continuous-Time Switch Family: A1101, A1102, A1103, A1104, and A1106

A1101, A1102, A1103, A1104, and A1106
Continuous-Time Switch Family
FEATURES AND BENEFITS DESCRIPTION

AEC-Q100 automotive qualified The Allegro A1101-A1104 and A1106 Hall-effect switches
Continuous-time operation are next generation replacements for the popular Allegro
Fast power-on time 312x and 314x lines of unipolar switches. The A110x family,
Low noise produced with BiCMOS technology, consists of devices that
Stable operation over full operating temperature range feature fast power-on time and low-noise operation. Device
Reverse battery protection programming is performed after packaging, to ensure increased
Solid-state reliability switchpoint accuracy by eliminating offsets that can be induced
Factory-programmed at end-of-line for optimum by package stress. Unique Hall element geometries and low-
performance offset amplifiers help to minimize noise and to reduce the
Robust EMC performance residual offset voltage normally caused by device overmolding,
High ESD rating temperature excursions, and thermal stress.
Regulator stability without a bypass capacitor
The A1101-A1104 and A1106 Hall-effect switches include
the following on a single silicon chip: voltage regulator, Hall-
PACKAGES: voltage generator, small-signal amplifier, Schmitt trigger, and
Not to scale NMOS output transistor. The integrated voltage regulator
permits operation from 3.8 to 24 V. The extensive on-board
protection circuitry makes possible a 30 V absolute maximum
voltage rating for superior protection in automotive and
industrial motor commutation applications, without adding
NOT FOR external components. All devices in the family are identical
NEW DESIGN
except for magnetic switchpoint levels.
The small geometries of the BiCMOS process allow these
3-pin SOT23W devices to be provided in ultrasmall packages. The package
(suffix LH) styles available provide magnetically optimized solutions for
3-pin SIP, 3-pin SIP, most applications. Package LH is an SOT23W, a miniature low-
matrix HD style chopper style profile surface-mount package, while package UA is a three-lead
(suffix UA) (suffix UA) ultramini SIP for through-hole mounting. Each package is lead
(Pb) free, with 100% matte-tin-plated leadframes.
VCC
Regulator To all subcircuits
VOUT
Amp
Gain Offset
Trim
Control
GND
Functional Block Diagram
A1101-DS, Rev. 17 October 27, 2016

A1101, A1102, A1103,
A1104, and A1106 Continuous-Time Switch Family
SPECIFICATIONS
SELECTION GUIDE
Part Number Packing [1] Mounting Ambient, TA BRP (Min) BOP (Max)
A1101ELHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
A1101ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount 40C to 85C
A1101EUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
10 175
A1101LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount
40C to
A1101LLHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
150C
A1101LUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
A1102ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount 40C to 85C
A1102EUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole
60 245
40C to
150C
40C to 85C
A1103ELHLX-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount
A1103LLHLT-T 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount 150 355
40C to
150C
A1104EUA-T [2] Bulk, 500 pieces/bag 3-pin SIP through hole 40C to 85C
40C to 25 450
150C
A1106EUA-T Bulk, 500 pieces/bag 3-pin SIP through hole 40C to 85C
40C to 160 430
150C
A1106LUA-T Bulk, 500 pieces/bag 3-pin SIP through hole
1 Contact Allegro for additional packing options.
2 The chopper-style UA package is not for new design; the matrix HD style UA package is recommended for new designs.
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Units
Supply Voltage VCC 30 V
Reverse Supply Voltage VRCC 30 V
Output Off Voltage VOUT 30 V
Reverse Output Voltage VROUT 0.5 V
Output Current IOUTSINK 25 mA
Magnetic Flux Density B Unlimited G
Range E 40 to 85 C
Operating Ambient Temperature TA
Range L 40 to 150 C
Maximum Junction Temperature TJ(max) 165 C
Storage Temperature Tstg 65 to 170 C
Allegro MicroSystems, LLC 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1101, A1102, A1103,
ELECTRICAL OPERATING CHARACTERISTICS over full operating voltage and ambient temperature ranges,
unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Supply Voltage [1] VCC Operating, TJ < 165C 3.8 24 V
Output Leakage Current IOUTOFF VOUT = 24 V, B < BRP 10 A
Output On Voltage VOUT(SAT) IOUT = 20 mA, B > BOP 215 400 mV
Slew rate (dVCC/dt) < 2.5 V/s, B > BOP + 5 G or B< BRP
Power-On Time [2] tPO 4 s
5G
Output Rise Time [3] tr VCC = 12 V, RLOAD = 820 , CS = 12 pF 400 ns
Output Fall Time [3] tf VCC = 12 V, RLOAD = 820 , CS = 12 pF 400 ns
ICCON B > BOP 4.1 7.5 mA
Supply Current
ICCOFF B < BRP 3.8 7.5 mA
Reverse Battery Current IRCC VRCC = 30 V 10 mA
Supply Zener Clamp Voltage VZ ICC = 10.5 mA; TA = 25C 32 V
Supply Zener Current [4] IZ VZ = 32 V; TA = 25C 10.5 mA
1 Maximum voltage must be adjusted for power dissipation and junction temperature, see Power Derating section.
2 For VCC slew rates greater than 250 V/s, and TA = 150C, the Power-On Time can reach its maximum value.
3 C =oscilloscope probe capacitance.
S
4 Maximum current limit is equal to the maximum I
CC(max) + 3 mA.
DEVICE QUALIFICATION PROGRAM

Contact Allegro for information.
EMC (ELECTROMAGNETIC COMPATABILITY) REQUIREMENTS

Contact Allegro for information.
GND
1 2 1 2 3
VCC
VOUT
GND
VCC
VOUT
Package LH Package UA, 3-pin SIP
Terminal List
Number
Name Description
Package LH Package UA
1 1 VCC Connects power supply to chip
2 3 VOUT Output from circuit
3 2 GND Ground

A1101, A1102, A1103,
MAGNETIC OPERATING CHARACTERISTICS [1]: over full operating voltage and ambient temperature ranges,
unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. Max. Units
TA = 25C 50 100 160 G
A1101
Operating Temperature Range 30 100 175 G
TA = 25C 130 180 230 G
A1102
TA = 25C 220 280 340 G
Operate Point BOP A1103
TA = 25C 70 350 G
A1104
Operating Temperature Range 35 450 G
TA = 25C 280 340 400 G
A1106
TA = 25C 10 45 130 G
A1101
TA = 25C 75 125 175 G
A1102
TA = 25C 165 225 285 G
Release Point BRP A1103
TA = 25C 50 330 G
A1104
TA = 25C 180 240 300 G
A1106
TA = 25C 20 55 80 G
A1101
TA = 25C 30 55 80 G
A1102
TA = 25C 30 55 80 G
Hysteresis BHYS A1103
TA = 25C 20 55 G
A1104
TA = 25C 70 105 140 G
A1106
1 Magnetic flux density, B, is indicated as a negative value for north-polarity magnetic fields, and as a positive value for south-polarity magnetic fields. This so-called alge-
braic convention supports arithmetic comparison of north and south polarity values, where the relative strength of the field is indicated by the absolute value of B, and the
sign indicates the polarity of the field (for example, a 100 G field and a 100 G field have equivalent strength, but opposite polarity).

A1101, A1102, A1103,
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions Value Units

Package LH, 1-layer PCB with copper limited to solder pads 228 C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side
Package Thermal Resistance RJA 110 C/W
connected by thermal vias
Package UA, 1-layer PCB with copper limited to solder pads 165 C/W
Power Derating Curve

TJ(max) = 165C; ICC = ICC(max)
25
24 VCC(max)
23
22
Maximum Allowable VCC (V)
21
20
19
18
17
16
15
14
13
12
Package LH, 2-layer PCB
11 (RJA = 110 C/W)
10
9 Package UA, 1-layer PCB
8 (RJA = 165 C/W)
7
6 Package LH, 1-layer PCB
5 (RJA = 228 C/W)
4 VCC(min)
3
2
20 40 60 80 100 120 140 160 180
Temperature
Power Dissipation (C)
versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
Power Dissipation, PD (mW)
1200 Pa
1100 (R cka
J ge
A = L
1000 11 H, 2
Pac 0 -la
900 C/ ye
800 (R kage W
) r PC
JA = UA B
165 1-la,
700 C/ yer
W) PC
600 B
500 Pac
k
400 (R age LH
,
300 JA =
228 1-laye
C/W r PC
200 ) B
100
0
20 40 60 80 100 120 140 160 180
Temperature (C)

A1101, A1102, A1103,
CHARACTERISTIC DATA
Supply Current (On) versus Ambient Temperature Supply Current (On) versus Supply Voltage
(A1101/02/03/04/06) (A1101/02/03/04/06)
8.0 8.0
7.0 7.0
6.0 6.0 TA (C)
VCC (V)
ICCON (mA)
ICCON (mA)
5.0 5.0 40
24
4.0 4.0 25
3.8
150
3.0 3.0
2.0 2.0
1.0 1.0
0 0
50 0 50 100 150 0 5 10 15 20 25
TA (C) VCC (V)
Supply Current (Off) versus Ambient Temperature Supply Current (Off) versus Supply Voltage
(A1101/02/03/04/06) (A1101/02/03/04/06)
8.0 8.0
7.0 7.0
6.0 6.0 TA (C)
VCC (V)
ICCOFF (mA)
ICCOFF (mA)
5.0 5.0 40
24
4.0 4.0 25
3.8
150
3.0 3.0
2.0 2.0
1.0 1.0
0 0
50 0 50 100 150 0 5 10 15 20 25
TA (C) VCC (V)
Output Voltage (On) versus Ambient Temperature Output Voltage (On) versus Supply Voltage
(A1101/02/03/04/06) (A1101/02/03/04/06)
400 400
350 350
300 300
VOUT(SAT) (mV)
TA (C)
VOUT(SAT) (mV)
250 VCC (V) 250

24 40
200 200
3.8 25
150 150 150
100 100
50 50
0 0
50 0 50 100 150 0 5 10 15 20 25
TA (C) VCC (V)

A1101, A1102, A1103,
FUNCTIONAL DESCRIPTION
OPERATION time devices typically require programming after packaging to

tighten magnetic parameter distributions. In contrast, chopper-
The output of these devices switches low (turns on) when a stabilized switches employ an offset cancellation technique on
magnetic field (south polarity) perpendicular to the Hall element the chip that eliminates these offsets without the need for after-
exceeds the operate point threshold, BOP. After turn-on, the output packaging programming. The tradeoff is a longer settling time and
is capable of sinking 25 mA and the output voltage is VOUT(SAT). reduced frequency response as a result of the chopper-stabiliza-
When the magnetic field is reduced below the release point, tion offset cancellation algorithm.
BRP, the device output goes high (turns off). The difference in
the magnetic operate and release points is the hysteresis, Bhys, of The choice between continuous-time and chopper-stabilized
the device. This built-in hysteresis allows clean switching of the designs is solely determined by the application. Battery manage-
output, even in the presence of external mechanical vibration and ment is an example where continuous-time is often required. In
electrical noise. these applications, VCC is chopped with a very small duty cycle
in order to conserve power (refer to figure 2). The duty cycle
Powering-on the device in the hysteresis region, less than BOP and is controlled by the power-on time, tPO, of the device. Because
higher than BRP, allows an indeterminate output state. The correct continuous-time devices have the shorter power-on time, they are
state is attained after the first excursion beyond BOP or BRP. the clear choice for such applications.
CONTINUOUS-TIME BENEFITS For more information on the chopper stabilization technique,
refer to Technical Paper STP 97-10, Monolithic Magnetic Hall
Continuous-time devices, such as the A110x family, offer the fast- Sensing Using Dynamic Quadrature Offset Cancellation and
est available power-on settling time and frequency response. Due Technical Paper STP 99-1, Chopper-Stabilized Amplifiers with a
to offsets generated during the IC packaging process, continuous- Track-and-Hold Signal Demodulator.
(A) (B)
VS
V+
VCC
VCC RL
Switch to High
Switch to Low
VOUT
Output
A110x VOUT
GND
VOUT(SAT)
0
B 0 B+
BOP
BRP
BHYS
Figure 1: Switching Behavior of Unipolar Switches

On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B direction indicates decreasing
south polarity field strength (including the case of increasing north polarity). This behavior can be exhibited when using a circuit such as that
shown in Panel B.

A1101, A1102, A1103,
ADDITIONAL APPLICATIONS INFORMATION

Extensive applications information for Hall-effect devices is
available in:
Hall-Effect IC Applications Guide, Application Note 27701
Hall-Effect Devices: Guidelines for Designing Subassemblies
Using Hall-Effect Devices, Application Note 27703.1
Soldering Methods for Allegros Products SMT and Through-
Hole, Application Note 26009
All are provided in Allegro Electronic Data Book, AMS-702,
and the Allegro Web site, www.allegromicro.com.
1 2 3 4 5
VCC
VOUT
t
Output Sampled
tPO(max)
Figure 2: Continuous-Time Application, B < BRP

This figure illustrates the use of a quick cycle for chopping VCC in order to conserve battery power. Position 1, power is applied to the
device. Position 2, the output assumes the correct state at a time prior to the maximum Power-On Time, tPO(max). The case shown is where
the correct output state is HIGH. Position 3, tPO(max) has elapsed. The device output is valid. Position 4, after the output is valid, a control unit
reads the output. Position 5, power is removed from the device.

A1101, A1102, A1103,
POWER DERATING
Power Derating A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding TJ(max),
The device must be operated below the maximum junction
at a selected RJA and TA.
temperature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied Example: Reliability for VCC at TA=150C, package UA, using
power or improving the heat dissipation properties of the appli- minimum-K PCB.
cation. This section presents a procedure for correlating factors
Observe the worst-case ratings for the device, specifically:
affecting operating TJ. (Thermal data is also available on the
RJA=165C/W, TJ(max)=165C, VCC(max)= 24 V, and
Allegro MicroSystems website.)
ICC(max) = 7.5 mA.
The Package Thermal Resistance, RJA, is a figure of merit sum-
Calculate the maximum allowable power level, PD(max). First,
marizing the ability of the application and the device to dissipate
invert equation 3:
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K, Tmax = TJ(max) TA = 165C150C = 15C
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RJC, is relatively This provides the allowable increase to TJ resulting from internal
small component of RJA. Ambient air temperature, TA, and air power dissipation. Then, invert equation 2:
motion are significant external factors, damped by overmolding.
PD(max) = TmaxRJA =15C165C/W=91mW
The effect of varying power levels (Power Dissipation, PD), can Finally, invert equation 1 with respect to voltage:
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD. VCC(est) = PD(max) ICC(max)= 91mW7.5mA=12.1 V
PD = VIN IIN (1) The result indicates that, at TA, the application and device can dis-
sipate adequate amounts of heat at voltages VCC(est).
T = PD RJA (2)
Compare VCC(est) to VCC(max). If VCC(est) VCC(max), then reli-
TJ = TA + T (3) able operation between VCC(est) and VCC(max) requires enhanced
RJA. If VCC(est) VCC(max), then operation between VCC(est) and
For example, given common conditions such as: TA= 25C, VCC(max) is reliable under these conditions.
VCC = 12V, ICC = 4 mA, and RJA = 140 C/W, then:
PD = VCC ICC = 12 V 4 mA = 48 mW
T = PD RJA = 48 mW 140C/W = 7C
TJ = TA + T = 25C + 7C = 32C

A1101, A1102, A1103,
CUSTOMER PACKAGE DRAWING
For Reference Only Not for Tooling Use

(Reference DWG-2840)
Dimensions in millimeters NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
+0.12
2.98 0.08
D
1.49
4 4
A
3
+0.020
0.180 0.053
0.96 D
+0.19
+0.10 1.91 0.06 2.40
2.90 0.20
0.70
D
1.00
0.25 MIN
1 2
0.55 REF
0.25 BSC 0.95
Seating Plane
Branded Face Gauge Plane B PCB Layout Reference View
8X 10
REF
1.00 0.13
A1101, A1102,
A1103, A1104, NNT
and A1106
+0.10
0.05 0.05
0.95 BSC
0.40 0.10
N = Last three digits of device part number
T = Temperature Code (Letter)
A Active Area Depth, 0.28 mm
B Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads;
adjust as necessary to meet application process requirements and PCB layout tolerances
A1101, A1102,
C Branding scale and appearance at supplier discretion A1103, A1104, NNN
and A1106
D Hall elements, not to scale
N = Last three digits of device part number
C Standard Branding Reference View
Figure 3: Package LH, 3-Pin (SOT-23W)

A1101, A1102, A1103,
+0.08
4.09 0.05
45
B D Standard Branding Reference View
C
E
2.04
1.52 0.05
NNN
1.44 E
Mold Ejector
+0.08 2X10
3.02 0.05 Pin Indent
E 1
Branded 45
= Supplier emblem
Face N = Last three digits of device part number
A
1.02 0.79 REF
MAX
0.51 NNT
REF
1 2 3
1
= Supplier emblem
N = Last two digits of device part number
14.99 0.25 +0.03 T = Temperature code
0.41 0.06
For Reference Only; not for tooling use (reference DWG-9013)

Dimensions in millimeters
A Dambar removal protrusion (6X)

B Gate and tie bar burr area
C Active Area Depth, 0.50 mm REF
D Branding scale and appearance at supplier discretion
E Hall element, not to scale
+0.05 1.27 NOM
0.43 0.07
Figure 4: Package UA, 3-Pin SIP, Matrix Style

A1101, A1102, A1103,
+0.08
4.09 0.05
45
B
C
E
2.04
1.52 0.05
1.44 E
Mold Ejector
+0.08 Pin Indent
3.02 0.05
E
Branded 45
Face
2.16
MAX D Standard Branding Reference View
0.79 REF
0.51
REF
A
NOT FOR NNT
NEW DESIGN
1 2 3
1
= Supplier emblem
+0.03 N = Last two digits of device part number
0.41 0.06
15.75 0.51 T = Temperature code
For Reference Only; not for tooling use (reference DWG-9049)

Dimensions in millimeters
A Dambar removal protrusion (6X)

B Gate burr area
C Active Area Depth, 0.50 mm REF
D Branding scale and appearance at supplier discretion
E Hall element, not to scale
+0.05 1.27 NOM

0.43 0.07
Figure 5: Package UA, 3-Pin SIP, Chopper Style

A1101, A1102, A1103,
Revision History
Number Date Description
14 May 29, 2012 Add A1106 UA package drawing
15 January 1, 2015 Added the LX option to Selection Guide
16 September 30, 2015 Corrected LH package Active Area Depth value and LH package branding; added AEC-Q100
qualification under Features and Benefits
17 October 27, 2016 Chopper-style UA package designated as not for new design
Copyright 2016, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegros product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com


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A1101, A1102, A1103, A1104, and A1106

Continuous-Time Switch Family

FEATURES AND BENEFITS DESCRIPTION

Regulator To all subcircuits

Functional Block Diagram

A1101-DS, Rev. 17 October 27, 2016

ABSOLUTE MAXIMUM RATINGS

Allegro MicroSystems, LLC 2

DEVICE QUALIFICATION PROGRAM

EMC (ELECTROMAGNETIC COMPATABILITY) REQUIREMENTS

Package LH Package UA, 3-pin SIP

Allegro MicroSystems, LLC 3

Allegro MicroSystems, LLC 4

Characteristic Symbol Test Conditions Value Units

Power Derating Curve

Allegro MicroSystems, LLC 5

250 VCC (V) 250

Allegro MicroSystems, LLC 6

OPERATION time devices typically require programming after packaging to

Figure 1: Switching Behavior of Unipolar Switches

Allegro MicroSystems, LLC 7

ADDITIONAL APPLICATIONS INFORMATION

Figure 2: Continuous-Time Application, B < BRP

Allegro MicroSystems, LLC 8

Allegro MicroSystems, LLC 9

CUSTOMER PACKAGE DRAWING

For Reference Only Not for Tooling Use

A Active Area Depth, 0.28 mm

N = Last three digits of device part number

C Standard Branding Reference View

Figure 3: Package LH, 3-Pin (SOT-23W)

Allegro MicroSystems, LLC 10

For Reference Only; not for tooling use (reference DWG-9013)

A Dambar removal protrusion (6X)

Figure 4: Package UA, 3-Pin SIP, Matrix Style

Allegro MicroSystems, LLC 11

For Reference Only; not for tooling use (reference DWG-9049)

A Dambar removal protrusion (6X)

+0.05 1.27 NOM

Figure 5: Package UA, 3-Pin SIP, Chopper Style

Allegro MicroSystems, LLC 12

Copyright 2016, Allegro MicroSystems, LLC

For the latest version of this document, visit our website:

Allegro MicroSystems, LLC 13

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