----------------------------------------------------------------------------------

-- Company:
-- Engineer:
--
-- Create Date: 08/05/2017 08:17:43 AM
-- Design Name:
-- Module Name: jk_flipflop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jk_flipflop is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end jk_flipflop;

architecture Behavioral of jk_flipflop is

signal temp : STD_LOGIC;
begin

process (j,k,clk,rst)
begin
if (rst='1') then temp<='0';
elsif ( clk='1' and clk'event) then
if (j='0' and k='0') then temp<=temp;
elsif (j='0' and k='1') then temp<='0';
elsif (j='1' and k='0') then temp<='1';
else temp<= not temp;
end if;
end if;
end process;

q<=temp;
qbar<= not temp;

end Behavioral;

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/05/2017 08:30:31 AM
-- Design Name:
-- Module Name: jk_flipflop_test - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity jk_flipflop_test is
-- Port ( );
end jk_flipflop_test;

architecture Behavioral of jk_flipflop_test is

component jk_flipflop is
Port ( j : in STD_LOGIC;
k : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC;
 clk : in STD_LOGIC;
rst : in STD_LOGIC);
end component;
signal j,k,q,qbar,clk,rst : STD_LOGIC;

begin
x1: jk_flipflop port map (j,k,q,qbar,clk,rst);

rst<='0','1' after 20 ns, '0' after 50 ns;

process
begin
clk<='0';
wait for 50 ns;
clk<='1';
wait for 50 ns;
end process;

process
begin
j<='0';
wait for 100 ns;
j<='1';
wait for 100 ns;
end process;

process
begin
k<='0';
wait for 150 ns;
k<='1';
wait for 150 ns;
end process;

end Behavioral;