LOW power VLSI Design

CMOS Layout tool orientation

Instructor:
Luo, Ci_Hang
Office ROOM:E1-118-1
Email: k9966809@gmail.com
Layout tool

1. Cadence Virtuso (fee)

2. Synopsys Laker (fee)
3. Mentor Tanner L-Edit (fee)
4. LASI (fee)
5. Silvaco (fee)
-----------------------------------
4. Electric (free)
5. Magic VLSI (free)
Magic VLSI
http://www.sourceware.org/cygwin/
Downland

https://fossies.org/linux/misc/magic-8.1.135.tgz/magic-
8.1.135/doc/html/ext2spice.html
:https://www.youtube.com/watch?v=MxXvp_tuY8s
https://www.youtube.com/watch?v=D32woicgdRk
Electronics
Installation (for Windows, see bottom of page for detailed Linux/Unix installation)
1.Ensure Java is installed on your computer by going to Java.com
2.Create a directory C:\Electric
3.Save electric-9.07.jar in this directory
4.Ensure the file extension is *.jar since Windows may try to change the download to *.zip
5.Double clicking on the jar file starts Electric
Examples are found in: opamp.zip and ece5410.zip.
Hundreds of examples are found on the CMOS books' webpages or in a single zip here.

Electric User's Manual

http://www.staticfreesoft.com/jmanual/index.html
 nMOS&pMOS
Choose device(The left mouse button)
and Pull line (Right click on the mouse)

VDD&GND

pin
Crtl+I Properties
Imput model CIC0.18.l
Correspond cic018.l model name

Crtl+I Properties
Crtl+E pin name
double right click on
the mouse on line
Crtl+I Properties
LTspice
Hspice
123.spi 123.sp
Simulate&wave
Crtl+I Properties
Crtl+J 90 DEGRESS
Cic018.l model name
Choose device(The left mouse button)
and Pull line (Right click on the mouse)
Crtl+E PIN NAME
Crtl+m P COPY

cont
nact
pact
Choose device(double left mouse button)
Must pull line
 Metla 1 doesnt give pin name,
So metal 1 text.

M1 text

Crtl+E PIN NAME

Choose device(double left mouse button)
Crtl+E PIN NAME

Choose device(double left mouse button)

nWell&pWell
Check LVS
Copt your testbench
Choose device(double left mouse button)
LTSPICE
HSPICE
File name
XXXX.spi XXX.sp
Simulate&wave
pre-sim

Post-sim(NO parasitic)

Post-sim( parasitic)
Run tran
Post-sim( parasitic)

Post-sim(NO parasitic)

pre-sim
Run 5 corner

add
ff
fs
sf
ss
tt
Run temp
100

50

25
Virtuoso(1P6M_CIC018)
 2. 4.

1.

3.

icfbOptionUser Preference
Undo Limit OK
 F2
f
Zoom in Ctrl+z Esc
Zoom out Shift+z
s
c
m
Delete
u
q
i
p
Shift+p
L
r
k
OptionDisplay(e)
X Snap Spacing 0.001
Y Snap Spacing 0.001
OK
Cont(via)1/5
Cont(via)2/5
Cont(via)3/5
Cont(via)4/5
Cont(via)5/5
 0.2um
PIMP

W =1um
0.2um
0.2um

0.2um

NIMPPIMP
N
PMOS
NPMOS L
Gate

0.2um

0.2um W =0.5um
0.2um

0.2um
NIMP 89
89
 NMOS(1/10)
3.0.23X0.23

1.CONT

=0.23um

2.R

=0.23um

contact

 NMOS(2/10)
5.RMetal1CONT
Metal 1
contact
>0.08um 0.08m

4.ME1 >0.08um

>0.08um

>0.08um
 NMOS(3/10)
5.RDiffusionCONT
Diffusion
contact
0.12m
>0.12um

6.DIFF
>0.12um
>0.12um

>0.12um
 NMOS(4/10)

(Cell)

EditHierarchyMake CellCellCell NameOK

NMOS(5/10)
Cell

Celllayout
Shift+F
NMOS(6/10)

0.18um

Poly to Diff >0.12 m

>0.12um
NMOS(7/10)
C CONT
POLY

NMOS(8/10)
Diff
0.25 m
NMOS W

0.25um
NMOS(9/10)
MOSWL
layout
DIFFPOLY
(Channel)

L

W
 NMOS(10/10)
NIMP
Diffusion

0.2m
>0.2um

NIMPDIFFN+ DiffusionNMOS
NMOS
NMOSI

 (Instance)
5.Hide
2.Browse
1.I

4.layout
3. close
cell
(Instance)

0.47um
CONT to CONT >0.25 m
CONT
0.24 m?
CONTQ

Delta X+0.01
DIFF
>0.1um
>0.1um
 PMOSBODYNWELL
N Tap
S

G B

PMOSNMOS
S/D D/S SourceDrain D
S PMOS
D
D

G
B
S/D D/S

S
NMOS
NMOSBODYP Sub
P Tap

P
F3

F3


vdd!
vdd!

out
in out
in

gnd!

gnd!
 Lable
2

1.MX_TEXT(X:
METALMetal1
M1_TEXTMetal2 M2_TEXT)
2.LLabel
3.(
Metal)
Lable


POLYpin
PO_TEXTpoly
to metal1 contact M1_TEXT
lable

>0.12um

CONT
PO1 ME1
Inverter layout !
Check DRC(Process rule)
comparison
 Check LVS

Check

?
schematic layout
comparison
output GDS