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Experiment: 6 VHDL Program Date: 26.08.

15

Aim: To write a VHDL program for Subprogram overloading.

VHDL Program for Subprogram overloading:


add_fun_overload
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
usework.fun_overload.all;--contains overloaded functions

entityadd_fun_overload is
Port ( a : in bit_VECTOR (7 downto 0);
b : in bit_VECTOR (7 downto 0);
z : out bit_VECTOR (7 downto 0);
a1: in integer;
z1:out integer);
endadd_fun_overload;
architecture Behavioral of add_fun_overload is
begin
z<= addition(a,b);
z1<=addition(a,a1);
end Behavioral;

Fun_Overload
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_unsigned.ALL;
usework.bit_pack.all; --contains vec2int convertion
packageFun_Overload is
function addition(add1, add2:bit_vector) return bit_vector;
function addition(add1:bit_vector;add2:integer) return integer;
endFun_Overload;

package body Fun_Overload is


function addition(add1, add2:bit_vector) return bit_vector is
variablesum:bit_vector(add1'length-1 downto 0);
variable c:bit:='0';
alias n1:bit_vector(add1'length-1 downto 0) is add1;
alias n2:bit_vector(add2'length-1 downto 0) is add2;
begin
fori in sum'reverse_range loop
sum(i):=n1(i) xor n2(i) xor c;
c:=(n1(i)and n2(i)) or (n1(i)and c)or (n2(i)and c);
end loop;
return(sum);
end addition;
function addition(add1:bit_vector;add2:integer) return integer is
variable sum1,a: integer;
begin
a:= vec2int(add1);
sum1:= a+add2;
return(sum1);
end addition;
endFun_Overload;
bit_pack
library IEEE;
use IEEE.STD_LOGIC_1164.all;
packagebit_pack is
function vec2int(vec1: bit_vector)return integer;
endbit_pack;

package body bit_pack is


function vec2int(vec1: bit_vector) return integer is
variableretval: integer:=0;
aliasvec: bit_vector(vec1'length-1 downto 0) is vec1;
begin
fori in vec'highdownto 1 loop
if (vec(i)='1') then
retval:=(retval+1)*2;
else
retval:=retval*2;
end if;
end loop;
ifvec(0)='1' then
retval:=retval+1;
end if;
returnretval;
end vec2int;
endbit_pack;

Output of Subprogram overloading:

Conclusion: The VHDL program for Subprogram overloading was studied and successfully implemented.

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