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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

Power PC is abbreviated as Performance Computing. Since the early 1970s, computing


power has doubled about every 18 months due to the creation of faster microprocessors,
the incorporation of multiple microprocessor designs, and the development of new storage
technologies. Ongoing research is focused on creating computers that use light and
biological molecules instead of-or in combination with-conventional electronic computer
circuitry. These technological advances, coupled with new methods for interconnecting
computers, such as the proposed Internet2, an advanced Internet under development by
universities, industry, and the government, promise to make PCs even more powerful and
useful.

The history of the PowerPC begins with IBM's 801 prototype chip of John Cocke’s RISC ideas.
In 1975 the 801 minicomputer project at IBM pioneered many of the architecture concepts
used in RISC systems. The system allows for a superscalar implementation versions of the
design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER
specification, the PowerPC added:

 Support for operation in both big-endian and little-endian modes; the PowerPC can switch
from one mode to the other at run-time. This feature is not supported in the PowePC 970.
This was the reason Virtual PC took so long to be made functional on 970-based Macintosh
computers.
 Single-precision forms of some floating point instructions, in addition to double-precision
forms
 Additional floating point instructions at the behest of Apple
 A complete 64-bit specification that is backward compatible with the 32-bit mode
 A fused multiply-add.
 A paged memory management architecture which is used extensively in server and PC
systems.
 Addition of a new memory management architecture called Book-E, replacing the
conventional paged memory management architecture for embedded applications. Book-E
is application software compatible with existing PowerPC implementations, but requires
minor changes to the operating system.

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

POWER is also the name of a series of microprocessors that implement the POWER ISA. The
POWER series microprocessors are used as the CPU in many of IBM's servers,
minicomputers, workstations, and supercomputers. The POWER3 and subsequent
microprocessors in the POWER series all implement the full 64-bit PowerPC architecture.
The POWER3 and above do not implement any of the old POWER instructions that were
removed from the ISA when the PowerPC ISA came out or any of the POWER2 extensions
such as lfq or stfq.

The 801 project


In 1974, IBM started a project with a design objective of creating a large telephone-
switching network with a potential capacity to deal with at least 300 calls per second. It was
projected that 20,000 machine instructions would be required to handle each call while
maintaining a real-time response, so a processor with a performance of 12 MIPS was
deemed necessary. This requirement was extremely ambitious for the time, but it was
realized that much of the complexity of contemporary CPUs could be dispensed with, since
this machine would need only to perform I/O, branches, add register-register, move data
between registers and memory, and would have no need for special instructions to perform
heavy arithmetic.

This simple design philosophy, whereby each step of a complex operation is specified
explicitly by a single machine instruction, and all instructions are required to complete in the
same constant time, would later come to be known as RISC.

By 1975 the telephone switch project was canceled without a prototype. From the
estimates from simulations produced in the project's first year, however, it looked as if the
processor being designed for this project could be a very promising general-purpose
processor, so work continued at Thomas J. Watson Research Center building #801, on the
"801" project.

1982 Research Project “Cheetah”


For two years at the Watson Research Center the superscalar limits of the “801” design
were explored, such as the feasibility of implementing the “801” design using multiple
functional units to improve performance, similar to what had been done in the

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

IBM System/360 Model 91 and the CDC 6600 (although the Model 91 had been based on a
CISC design), to determine if a RISC machine could maintain multiple instructions per cycle,
or what design changes need to be made to the “801” design to allow for a multiple-
execution-unit “801” design.

To increase performance “Cheetah” had separate branch, fixed-point, and floating-point


execution units. Many changes were made to the “801” design to allow for a multiple-
execution-unit design. "Cheetah" was originally planned to be manufactured using bipolar
ECl technology, but by 1984 CMOS afforded an increase in the level of circuit integration
while improving transistor-logic performance.

The America Project


In 1985, research on a second-generation RISC architecture started at the IBM Thomas J.
Watson Research Center, producing the "AMERICA architecture"; in 1986, IBM Austin
started developing the RS/6000 series, based on that architecture.

The Bellatrix Project


Sometime in the years of 1986-89, the Bellatrix Project was started, with the premise of
using the America architecture as the base for a common architecture that could host
OS/390 for mainframe applications, OS/400 for multi-processor server transactional
processing, and AIX for scientific applications.

Sometime between the years of 1990-95, the project was considered overly ambitious and
was canceled.

POWER
In February 1990, the first computers from IBM to incorporate the POWER Architecture
("Performance Optimized With Enhanced RISC") were called the "RISC System/6000"
or RS/6000. These RS/6000 computers were divided into two
classes, workstations and servers, and hence introduced as the POWER-station and POWER-
server. The RS/6000 CPU had 2 configurations, called the "RIOS-1" and "RIOS.9" (or more
commonly the “POWER1” CPU). A RIOS-1 configuration had a total of 10 discrete chips - an
instruction cache chip, fixed-point chip, floating-point chip, 4 data cache chips, storage
control chip, input/output chips, and a clock chip. The lower cost RIOS.9 configuration had 8
discrete chips - an instruction cache chip, fixed-point chip, floating-point chip, 2 data cache
chips, storage control chip, input/output chip, and a clock chip.

A single-chip implementation of RIOS, RSC (for “RISC Single Chip”), was developed for lower-
end RS/6000's; the first machines using RSC were released in 1992.

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

The Amazon Project


In 1990 the Amazon project was started to create a common architecture that would host
both AIX and OS/400. The AS/400 engineering team at IBM was designing a RISC instruction
set to replace the CISC instruction set of the existing AS/400 computers. Their original
design was a variant of the existing "IMPI" instruction set, extended to 64 bits and given
some RISC instructions to speed up the more computationally intensive commercial
applications that were being put on AS/400s. IBM management wanted them to use
PowerPC, but they resisted, arguing that the existing 32/64-bit PowerPC instruction set
would not enable a viable transition for OS/400 software and that the existing instruction
set required extensions for the commercial applications on the AS/400. Eventually, an
extension to the PowerPC instruction set, called "Amazon", was developed.

At the same time, the RS/6000 developers were broadly expanding their product line to
include systems which spanned from low-end workstations, to mainframe competitor-large
enterprise SMP systems, to clustered RS/6000-SP2 supercomputing systems. PowerPC
processors developed in the AIM suited the low-end RISC workstation and small server
space well. But mainframe and large clustered supercomputing systems required more
performance and RAS features than processors designed for Apple Power Macs. Multiple
processor designs were required to simultaneously meet the requirements of the cost-
focused Apple Power Mac, high-performance and RAS RS/6000 systems, and the AS/400
transition to PowerPC.

Amazon was extended to support those features as well, so that processors could be
designed for use in both high-end RS/6000 and AS/400 machines.

The project to develop the first such processor was "Bellatrix" (the name of a star in the
Orion Constellation, also called the "Amazon Star"). The Bellatrix project was extremely
ambitious in its pervasive use of self-timed & pulse based circuits and the EDA tools
required to support this design strategy, and were eventually terminated. To address
technical workstation, supercomputer, and engineering/scientific markets, IBM Austin (the
home of the RS/6000s) then started developing a time-to-market single-chip version of the
Power2 (P2SC) in parallel with the development of a sophisticated 64-bit PowerPC processor
with the POWER2 extensions and twin sophisticated MAF floating point units (the
POWER3/630). To address RS/6000 commercial applications and AS/400 systems, IBM
Rochester (the home of the AS/400s) started developing the first of the high-end 64-bit
PowerPC processors with AS/400 extensions, and IBM Endicott started developing a low-
end single-chip PowerPC processor with AS/400 extensions.

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

POWER2
IBM started the POWER2 processor effort as a successor to the POWER1 two years before
the creation of the 1991 Apple/IBM/Motorola alliance in Austin, Texas. Despite being
impacted by diversion of resources to jump start the Apple/IBM/Motorola effort, the
POWER2 took five years from start to system shipment. By adding a second fixed-point unit,
a second floating point unit, and other performance enhancements to the design, the
POWER2 had leadership performance when it was announced in November 1993.

New instructions were also added to the instruction set:

 Quad-word storage instructions. The quad-word load instruction moves two adjacent
double-precision values into two adjacent floating-point registers.
 Hardware square root instruction.
 Floating-point to integer conversion instructions.
To support the RS/6000 and RS/6000 SP2 product lines in 1996, IBM had its own design
team implement a single-chip implementation of POWER2, the P2SC ("POWER2 Super
Chip"), outside the Apple/IBM/Motorola alliance in IBM's most advanced and dense CMOS-
6S process. P2SC combined all of the separate POWER2 instruction cache, fixed point,
floating point, storage control, and data cache chips onto a single huge die. At the time of its
introduction, P2SC was the largest and highest transistor count processor in the industry.
Despite the challenge of its size, complexity, and advanced CMOS process, the first tape-out
version of the processor was able to be shipped, and it had leadership floating point
performance at the time it was announced. P2SC was the processor used in the 1997 IBM
Deep Blue chess playing supercomputer which beat chess grandmaster Gary Kasparov. With
its twin sophisticated MAF floating point units and huge wide and low latency memory
interfaces, P2SC was primarily targeted at engineering and scientific applications. P2SC was
eventually succeeded by the POWER3, which included 64-bit, SMP capability, and a full
transition to PowerPC in addition to P2SC's sophisticated twin MAF floating point units.

PowerPC
At some point in 1991 the Apple Computer Corporation decided to not migrate their 68000-
based software and hardware to Motorola's recommended upgrade path the 88xxx series.
Soon after, Apple, as one of Motorola’s largest customers of desktop-class microprocessors,
asked Motorola to join the discussions because of their long relationship, their more
extensive experience with manufacturing high-volume microprocessors than IBM, and to
serve as a second source for the microprocessors. This three-way collaboration, based
in Austin Texas, became known as the AIM alliance, for Apple, IBM, Motorola.

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

After two years of development, the resulting PowerPC architecture was introduced in
1993. A modified version of the RSC architecture, PowerPC added single-precision floating
point instructions and general register-to-register multiply and divide instructions, and
removed some POWER features such as the specialized multiply and divide instructions
using the MQ register. It also added a 64-bit version of the architecture and support
for SMP.

POWER3
IBM introduced the POWER3 processor in 1998. It implemented the 64-bit PowerPC
instruction set, including all of the optional instructions of the ISA (at the time). All
subsequent POWER processors implemented the full 64-bit PowerPC and POWER
instruction sets, so that there were no longer any IBM processors that implemented only
POWER or only POWER2.

POWER4
IBM introduced the POWER4 processor, the first in the GIGA-Series, in 2001. Like the
POWER3, it was a full 64-bit processor, implementing the full 64-bit PowerPC instruction
set; it also had the AS/400 extensions, and was used in both RS/6000 and AS/400 systems,
replacing both POWER3 and the RS64 processors. There was a new ISA release at this point
called the PowerPC 2.00 ISA, which added a couple of extensions to the ISA, such as a
version of mfcr which also took a field argument.

POWER5
IBM introduced the POWER5 processor in 2004. It is a dual-core processor with support for
simultaneous multithreading with two threads, so it implements 4 logical processors. Using
the Virtual Vector Architecture, several POWER5 processors can act together as a
single vector Processor. The POWER5 added more instructions to the ISA. The POWER5+
added even more instructions, bringing the ISA to version 2.02.

POWER6
POWER6 was announced on May 21, 2007. It adds VMX to the POWER series. It also
introduces the second generation of IBM ViVA, ViVA-2. It is a dual-core design, reaching
5.0 GHz at 65 nm. It has very advanced interchip communication technology. Its power
consumption is nearly the same as the preceding POWER5, whilst offering doubled
performance.

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

POWER7
POWER7 is the first of the Peta-Series released in February 2010 and was selected
by DARPA as a processor to be used in their Peta-flops supercomputers, like Blue Water. In
the early 2000s, IBM submitted their proposal and received $53 million from DARPA to
continue to participate in the challenge; in 2006, IBM received $244 million to build a peta-
FLOPS computer for DARPA.

POWER8
Future successor to POWER7 PowerPC is currently under development; with unknown
specifications and unknown launch date.

This is the POWER5 version Explained Above.

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

Evolution in Intel’s Microprocessors is given year wise as under in sequence:

1971 4004
This is the first processor manufactured by Intel as a processing company, where transistors
and all the other components are used to attach on a single chip of silicon through
fabrication.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
108 KHz 4 bits 2300 10 640 bytes ---

1972 8008
It was designed for specific applications.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
108 KHz 8 bits 3500 --- 16 Kbytes ---

1947 8080
Instruction cycle for the first time was introduced by this model of processor, moreover it’s
the Intel’s first general purpose microprocessor.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
2 MHz 8 bits 6000 6 64 Kbytes ---

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

1978 8086
Clock Speed Bus Width Number of Feature Size Addressable Virtual
Transistors (µm) Memory Memory
5,8,10 MHz 16 bits 29000 3 1 MB ---

1979 8088
Clock Speed Bus Width Number of Feature Size Addressable Virtual
Transistors (µm) Memory Memory
5,8 MHz 8 bits 29000 6 1 MB ---

1982 80286
Virtual memory for the first time introduced here in this model of Intel processor series.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
6,12.5 MHz 16 bits 134000 1.5 16 MB 1 GB

1985 386TM DX
Multitasking is the key feature in this model of inlet’s microprocessor.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
16,33 MHz 32 bits 275000 1 4 GB 64 TB

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

1988 386TM SX
Clock Speed Bus Width Number of Feature Size Addressable Virtual
Transistors (µm) Memory Memory
16,33 MHz 16 bits 275000 1 16 MB 64 TB

1989 486TM DX CPU


Instruction Pipeline is the major advantage in this model such that the processor does not
have to wait for a process to complete execution and the next to be fetched for processing.
For the same one process is under processing & the second is being fetched for processing.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
25,50 MHz 32 bits 1.2 million 0.8-1 4 GB 64 TB

1991 486TM SX
Clock Speed Bus Width Number of Feature Size Addressable Virtual
Transistors (µm) Memory Memory
16,33 MHz 32 bits 1.185 million 1 4 GB 64 TB

1993 Pentium
This was the start of a new processing family. The processor was multitasking, instruction
execution was in parallel results in simultaneous instructions.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
60,166 MHz 32 bits 3.1 Million 0.8 4 GB 64 TB

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

1995 Pentium Pro


Clock Speed Bus Width Number of Feature Size Addressable Virtual
Transistors (µm) Memory Memory
150,200 MHz 64 bits 5.5 Million 0.6 64 GB 64 TB

1997 Pentium II
The processor more over a Pentium but was installed with Audio & Video i.e. with sound
and graphical processing for the first time being done.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
200,300 MHz 64 bits 7.5 Million 0.35 64 GB 64 TB

June 1998 Pentium II Xeon


The Model was announced just because a server machine over many Pentium II was
required its more efficient and powerful then the PII itself. Mover over Intel’s Xeon Series
was a server based series.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
400,600 MHz 64 bits 8.5 Million 0.35 BG 64 TB

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

Mar 1998 Celeron


This was the first ever mobile processer made by Intel and the same processor was used in
the first every small sized computer name Laptop in the world by means of average battery
life with low power consumption and same performance like that on the desktop.

Clock Speeds Bus Speed Number of Feature Size Addressable Virtual


Transistors (nm) Memory Memory
266,300,333,366, 66MHz 188 million 250 nm 64BG 64TB
400,433,466
MHz

1999 Pentium III


3D Graphics was installed in the processor all among with the video graphics.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
450,660 MHz 64 bits 9.5 Million 0.25 64 GB 64 TB

June 1999 Pentium III Xeon


Same like that of the Pentium II a Xeon model is introduced with Pentium III, more feasible
for multitasking and can easily bear more server load that Xeon Pentium II.

Clock Speed Bus Speed Number of Level 1 Level 2 Physical


Transistors Cache Cache Memory
500 MHz 100 MHz 9.5 Million 16 KB 512 KB 64GB

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

2000 Pentium 4
Pentium 4 is the most successful business for Intel till today in Pentium family after Dual
Core processor launched in June 2006. With a good processing speed and stable with all
respects of performance, power and heat.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
1.3-1.8 GHz 64 bits 42 million 0.18 64 GB 64 GB

2001 Itanium
Itanium is a family of Intel 64bit Processors, that implement the Intel Itanium
Architecture (formerly called IA-64)

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
733-800 MHz
][
64 bits 25 Million 0.18 64GB 64GB

2002 Itanium 2
The same IA-64 architecture come with this model but with a greater processing speed for
the same reason the number of transistors on each chip of Itanium 2 is thrice the amount
used in Itanium.

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (µm) Memory Memory
900 MHz 64 bits 220 Million 0.18 64 GB 64GB
1 GHz

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

Nov 2002 Pentium 4 HT


AThis model is the first introduced with the hyper-threading technology, a thread is a data
stream or data flow for execution of a program to the processing unit of the system Hyper-
threading is done to make the processor busy as much as it could

Clock Speed Bus Width Number of Feature Size Addressable Virtual


Transistors (nm) Memory Memory
1.8 to 3.4 64 bits 125 Million 180 64 GB 64 GB
GHz

Mar 2003 Centrino


The Centrino brand represents Intel Wi-Fi and WiMAX adapters.

the brand covered a particular combination of mainboard chipset, mobile CPU and wireless
network interface in the design of a laptop.

Mar 2003 Pentium M


The Pentium M brand refers to a family of mobile single core x86 processors. The Pentium
M represented a new and radical departure for Intel, as it was not a low-power version of
the desktop-oriented Pentium 4, but instead a heavily modified version of the Pentium
III designs (itself based on the Pentium Pro core design). It is optimized for power efficiency,
a vital characteristic for extending notebook computer battery life. Running with very low
average power consumption and much lower heat output than desktop processors, the
Pentium M runs at a lower clock speed than the laptop version of the Pentium
4 (The Pentium 4-Mobile, or P4-M), but with similar performance - a 1.6 GHz Pentium M
can typically attain or even surpass the performance of a 2.4 GHz Pentium 4-M.[2] The
Pentium M 740 has been tested to perform up to approximately 7,400 MIPS and 3.9 GFLOPS
(using SSE2).

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

Jan 2004 Celeron M


Celeron M is a Celeron mobile version of Intel Pentium M processor launched last year.

Clock Speed Number of Feature Size Addressable Virtual


Transistors (nm) Memory Memory
900 MHz to 1.3 GHz 120 Million 180 nm 64GB 64GB

Jan 2005 Pentium D


Pentium D was also a hyper threading model of Intel P4 HT series in Intel’s Pentium family
processors with special multitasking capabilities. However the series was not so famous
among the Intel users and considered as the flop series of Intel processors …

Clock Speed Number of Feature Size Addressable Virtual


Transistors (nm) Memory Memory
2 GHz to 3 GHz 250 Million 65 & 90 nm 64GB 64GB

June 2005 Celeron D


Celeron D is basically a Celeron Mobile version of Pentium D and where Pentium D was a
flop series of Intel for the same reason the name Celeron D was also comes under criticism
and was flopped too.

Clock Speed Number of Feature Size Addressable Virtual


Transistors (nm) Memory Memory
1.8 GHz to 2.2 GHz 250 million 90 nm 64GB 64GB

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

June 2006 Pentium Dual Core


The core common area is that area of a computer program where in data can remain
between the end of execution of one program and the start of execution of a subsequent
program in a pipeline. This implementation core technology first time was involved in the
invention of Dual core processor from Intel’s Pentium Family.

In computing, a multi-core processor is a processing system composed of two or more


independent cores. One can describe it as integrated circuits to which two or more
individual processors (called cores in this sense) have been attached

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

May 2007 Centrino 2 (Santa Rosa)


The most efficient technology yet to be come in mobile sense with maximum battery savior
and the best connectivity sense, it does multitasking on laptop form factor and do allow to
use processor such as dual-core and core 2 duo systems with less power consumption.

Sept 2007 Core 2 Solo


This is the first ever practical integration of two physical processors into a single processor
by using fabrication; however the model does not appear on the market more often for a
long time the invention was kept hidden and used by intelligence and other law and order
agencies, but do came in the market before the launch of a new processor for a while but it
seems if there are some architecture problems with the model and thus removed in the
next model launched by Intel.

Oct 2007 Xeon Dual Core


This basically belongs from the server Xeon family of processors of Intel with a Pentium
dual-core multitasking technology implemented for the sever to do more and more
multitasking but however it’s more powerful then the desktop version of dual-core.

Clock Speed Number of Feature Size Addressable Virtual


Transistors (nm) Memory Memory
2.2 GHz to 3.6 Ghz 500 Million 65 nm 64 GB 64GB

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

Dec 2007 Core 2 Duo


This is the first practical model of intelligent a dual CPU processor that is fabricated and
integrated with two physical processors and excellent multitasking capabilities …

Core 2 is a brand encompassing a range of Intel’s consumer 64 bit x86-64 single- & dual-
core CPUs based Core micro architecture. The single- and dual-core models are single-die.

CPU Speed FSB Technology Thermal Design


1.6GHz to 3.0 GHz 800,1066,1333 MHz LGA775 74.1 °C
L2 Cache Design Power Transistor Size Computing
1,2,3,4 & 6 MB 65W 65 & 45 nm 64 Bit Processor

July 2008 Celeron Dual Core


Celeron Dual Core is a dual core system with a technology implemented on a mobile
processing chip set, where the processor is low voltage, great processing and less power
dissipating and good for laptop computing.

CPU Speed FSB Technology Thermal Design


1.3 to 1.8 GHz 800 MHz LGA775 70°C
L2 Cache Power Transistor Size Computing
2 MB 45W 65nm 65 Bit processor

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

June 2008 Core 2 Quad


This is the first ever a physical four processor into one integration situation extremely
reliable and extra ordinary in terms of processing & uses clustering technology for all cores.

CPU Speed FSB Technology Thermal Design


2.2 to 3.2 GHz 1066 & 1333Mhz LGA775 85°C
L2 Cache Power Transistor Size Computing
4,6 & 8 MB 95W 65 & 45nm 64 bit

Aug 2008 Core 2 Extreme


Its basically a Quad Core processor where the need of over clocking is finished here the
processor is already over clocked to the best of its range by the manufacturer its extreme in
the sense of tuned clock and FSB. Where gamers after its launched purchased the model
and significantly used it … and acceptably the best over clocked edition of any processor
after core i7 extreme is this one in the whole of Intel’s processors.

CPU Speed FSB Technology Thermal Design


3.2 GHz 1333 MHz LGAS775 85°C
L2 Cache Power Transistor Size Computing
6MB 95W 45nm 64 bit

Sep 2008 Xeon Quad Core


It’s the server edition of the Quad Core series of Intel and Very powerful in terms of
Performance.

CPU Speed FSB Technology Thermal Design


3.0 GHz 1333 MHz LGA775 85°C
L2 Cache Power Transistor Size Computing
8MB 80W 45nm 64 bit

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

Oct 2008 Xeon Six-Core Processor


The first ever six core processor with a physical six cores and no desktop version yet
announced yet only the server version available ... it’s an awesome processor by terms of
multitasking through a network and where ever extreme performance is needed.

CPU Speed FSB Technology Thermal Design


3.0 Ghz 1666 MHz LGA1266 80°C
L2 Cache Power Transistor Size Computing
12 MB 80W 45nm 64 bit

Nov 2008 Core i7


This processor is one of the best yet today and there is no comparison when it’s down to
performance, multitasking, networking, graphics, High definition and Gamming. It’s the one
and only pick to make for Engineers, Programmers, Designers and Gamers. No processor
currently available in the market that can beat the aspects of this processor. Its Hyper
threading it’s a quad core with 4 physical and 4 virtual processors a sum of 8 cores all
together and supports Gaga Threading Technology.

CPU Speed FSB Technology Thermal Design


2.66 GHz 1333 MHz LGA1236 70°C
L2 Cache Power Transistor Size DMI
8 to 12MB 130W 45nm 2.5 to 6.2 GT/s

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

Jan 2009 Core i7 (Mobile)


This is the mobile version of core i7 made for laptops and notebook computing.

CPU Speed FSB Technology Thermal Design


1.66 GHz 1333 MHz LGA1236 70°C
L2 Cache Power Transistor Size DMI
8 MB 60W 45nm 2.5 GT/s

Feb 2009 Atom


This smallest processor yet made by Intel specially designed for net-books for the same
maximum battery life came into being and average processing with just on the go portable
computing is possible with maximum battery backup to do simple networking and
documentation.

CPU Speed 1.66 GHz


FSB 800 MHz
Technology LGA445
Thermal Design 60°C
Cache 2MB
Power 35W
Transistor size 45nm
Computing 64 Bit
Cores 1

Nov 2009 Core i5 (Mobile)


Mover over i5 is the same quad core without the GT/s technology implemented for average
users not so extreme needed to compute. So simply is the without GT/s version of core i7.

CPU Speed FSB Technology Thermal Design


2.0 to 3.00 GHz 1333 MHz LGA1236 °C
L2 Cache Power Transistor Size Computing
6 & 8 MB 75W 45nm 64 bit

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Computer Architecture [POWER PC AND EVOLUTION OF INTEL’S MICROPROCESSORS]

Jan 2010 Core i3


This is the best and the most efficient processor yet with the term computing on a portable
system that is a laptop and powerful like i5 & i7 versions on the desktop over all the greatest
advancement featuring this processor is the individual transistor size during fabrication its
reduced from the latest 45nm to a more compact and smaller 32nm which reduces more
size and is more efficient in terms of power consumption and does support a GT/s
Technology… and does have 4 virtual and 4 real cores for processing.

CPU Speed FSB Technology Thermal Design


2.66 to 3.06 GHz 1333 & 1666 Mhz LGA1236 75°C
L2 Cache Power Transistor Size DMI
4, 6 & 8 MB 73W 32nm 2.5 GT/s

Feb 2010 Core i7 Extreme


It’s the extreme over clocked edition of core i7 within its maximum range of frequency.

CPU Speed FSB Technology Thermal Design


3.33 GHz 1666 MHz LGA1236 80°C
L2 Cache Power Transistor Size Computing
12 MB 130W 45nm 64 bit

Mar 2010 Core i3 (Mobile)


Core i3 mobile is the laptop version of the core i3 desktop processor which is the most
efficient in notebooks yet.

CPU Speed FSB Technology Thermal Design


1.3 to 1.8 GHz 1333 MHz LGA1236 65°C
L2 Cache Power Transistor Size Computing
4MB 75W 32nm 64 bit

Intel’s Centrino Technology (Huron River) is yet to come this year ….

Intel’s Core family will later this year will announce a Six-Core Real and Virtual processing
machine with 6 practical and 6 virtual processing Cores and Defiantly as an equivalent of 12
Core Processing With GT/s will rock the world this year...

Balochistan University of Information Technology Engineering and Management Sciences. 22