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Assignment#2, Digital Electronics 2017

1. Figure 1 shows the use of an 8-to-1 multiplexer to implement a certain four-variable Boolean
function. From the given logic circuit arrangement, derive the Boolean expression implemented by
the given circuit.

Figure 1

2. Design a 16-to-1 multiplexer using two 8-to-1 multiplexers having an active LOW ENABLE input.
3. We have an eight-line to three-line priority encoder circuit with D0,D1,D2,D3,D4,D5,D6 and D7 as
the data input lines. the output bits are A (MSB), B and C (LSB). Higher-order data bits have been
assigned a higher priority, with D7 having the highest priority. If the data inputs and outputs are
active when LOW, determine the logic status of output bits for the following logic status of data
inputs:
(a) All inputs are in logic 0 state.

(b) D1 to D 4 are in logic 1 state and D5 to D7 are in logic 0 state.

(c) D7 is in logic 0 state. The logic status of the other inputs is not known.

4. Implement a full adder circuit using a 3-to-8 line decoder.

5. A combinational circuit is defined by F = 0, 2, 5, 6, 7. Hardware implement the Boolean function
F with a suitable decoder and an external OR/NOR gate having the minimum number of inputs.
6. Construct a 4-to-16 line decoder with two 3-to-8 line decoders having active LOW ENABLE inputs.
7. Implement the three-variable Boolean function F(A, B, C) = C +AC +AB using
(i) an8-to-1 multiplexer and (ii) a 4-to-1 multiplexer.
8. Implement a full subtractor combinational circuit using a 3-to-8 decoder and external NOR gates.
9. Determine the function performed by the combinational circuit of Fig. 2.
10. What are the four types of flip-flop?
11. Why must the T and JK flip-flops be clocked (synchronous).
12. In what ways can the operation of a flip-flop be described; what does the excitation table tell you?
13. Draw the truth table and excitation table for a JK flip-flop and relate their respective entries to
each other (i.e. which entries in the two tables correspond to each other?).

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Assignment#2, Digital Electronics 2017

14. What do the terms transparent; level triggered and edge triggered mean?
15. What happens to the output Q when a flip-flop is preset or reset; and what do asynchronous and
synchronous mean when referred to these operations?
16. What is a shift register, and why can such a circuit be used to multiply a binary number by 2".
17. What is a flip-flop? Show the logic implementation of an R-S flip-flop having active HIGH R and S
inputs. Draw its truth table and mark the invalid entry.
18. With the help of the logic diagram, describe the operation of a clocked R-S flip-flop with active
LOW R and S inputs. Draw the truth table of this flip-flop if it were negatively edge triggered.

Fig.2

19. How could:

(a) a JK flip-flop be used as a D-type?
(b) a JK flip-flop be used as a T-type?
(c) a D-type flip-flop be used as a T-type?
20. Draw the truth table for the following types of flip-flop:
a) a positive edge-triggered J-K flip-flop with active HIGH J and K inputs and active LOW
PRESET and CLEAR inputs;
b) a negative edge-triggered J-K flip-flop with active LOW J and K inputs and active LOW
PRESET and CLEAR inputs.

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Assignment#2, Digital Electronics 2017

21. What does the circuit in Fig. 3 do?

Fig. 3
22. The 100 kHz square waveform of Fig. 3 (a) is applied to the clock input of the flip-flops shown in
Figs. 3(b) and (c). If the Q output is initially 0, draw the Q output waveform in the two cases. Also,
determine the frequency of the Q output in the two cases.

Fig. 4
23. Differentiate between:
(a) synchronous and asynchronous inputs;
(b) level-triggered and edge-triggered flip-flops;
(c) active LOW and active HIGH inputs.
24. Briefly describe the following flip-flop timing parameters:
(a) set-up time and hold time;
(b) propagation delay;
(c) maximum clock frequency.
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Assignment#2, Digital Electronics 2017

25. What is meant by the race problem in flip-flops? How does a masterslave configuration help in
solving this problem?
26. Differentiate between a D flip-flop and a D latch.
27. Draw the function table for (a) a negative edge-triggered D flip-flop and (b) a D latch with an
active LOW ENABLE input.
28. With the help of a schematic arrangement, explain how a J-K flip-flop can be used as a (a) a D flip-
flop and (b) a T flip-flop.
29. What is the 'mod' of a counter?
30. What are the differences between asynchronous and synchronous counters?
31. What do the terms preset and reset mean when referred to counters?
32. What design changes are necessary to turn an asynchronous up-counter into the corresponding
down-counter?
33. What is the procedure for producing an asynchronous binary mod-N counter, and what problems
may be encountered when using such a circuit in practice?
34. How is a synchronous binary mod-2" counter produced?
35. What is the procedure for producing a synchronous binary mod-N counter?
36. In general how may flip-flops are required to produce a mod-N counter, how many unused states
will there be, and what is the outcome of entering these 'unused states'?
37. What type of counter is shown in Fig. 5, and what is its exact function? Show how a three-input
NOR gate could be used to decode count state 3, and draw the resultant output waveform.

Fig.5
38. Design a mod-7 synchronous binary counter using JK flip-flops. Determine what happens if the
count goes into any of the unused states and show the results on a state diagram. How must the
circuit be modified if the unused state is to lead to state 4 (i.e. outputs of 100 from the flip-flops
(MSB first)).

39. A 100-stage serial-in/serial-out shift register is clocked at 100 kHz. How long will the data be
delayed in passing through this register?
40. A four-bit ring counter and a four-bit Johnson counter are in turn clocked by a 10 MHz clock signal.
Determine the frequency and duty cycle of the output of the output flip-flop in the two cases.