Question Paper for Digital Electronic

Q1. In the given Fig. 4 to 1 MUX to be used to implement the sum S of a 1-bit full adder with
input bits P and Q and the carry input Cin. Which of the following combinations of inputs to I0,
I1, I2, I3 of the MUX will be realize the sum S?

I0
I1 4
S
I2
I3
S0 S1
P Q
a) I0 = I1= Cin ; I2 = I3= Cin b) I0 = I1= Cin ; I2 = I3= Cin
c) I0 = I3= Cin ; I2 = I1= Cin d) I0 = I3= Cin ; I2 = I1= Cin

Q2. The Boolean expression XYZ +XYZ+XYZ+XYZ+ XYZ can be simplified to

a) XZ+ XZ+ YZ b) XY+ YZ+ YZ c) XY+ YZ+ YZ d) XY+ YZ+ YZ

Q3. An X-Y flip flop, whose characteristics Table is given below is to be implemented using a J-K
flip flop

X Y Qn+1

0 0 1
0 1 Qn
1 0 Qn
1 1 0
a) J=X, K=Y b) J=X, K=Y c) J=Y, K=X d) J=Y, K=X

Q4. The digital circuit using two inverters shown in fig. will acts as

a) A Bistable multi Vibrator b) An Astable multi Vibrator

c) A Monostable multi Vibrator d) An Oscillator

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 Question Paper for Digital Electronic
Q5. The simplified form of the Boolean expression Y=( ABC+ D)(AD +BC) can be written as

a) AD+ BCD b) AD+ BCD c) (A+ D)(BC+D) d) AD + BCD

Q6. In the fig, as long as X1=1 and X2=1, the output Q remains

X1
Q

X2

a) at 1 b) at 0 c) at its initial value d) unstable

Q7. The complete set of only those Logic Gates designated as Universal Gates is

a) NOT, OR and AND Gates b) XNOR, NOR and NAND Gates

c) NOR and NAND Gates d) XOR, NOR and NAND Gates

Q8. The output of Y of the logic circuit given below is

a) 1 b) 0 c)x d) x

Q 9. The present output of an edge triggered JK flip flop is logic 0. If J= 1, then Qn+1 =?

a) Cannot be determined b) will be logic 0 c) will be logic 0 d) will race around

Q10. The number of product terms in the minimized SOP expression obtained through the following
K- map is

1 0 0 1
0 x 0 0
0 0 x 1
1 0 0 1

a) 2 b) 3 c) 4 d) 5

Q11. A 4 bit modulo 16 ripple counter uses J-K flip flop. If the propagation delay of each flip flop is
50nsec, the maximum clock frequency that can be used is equal to

a) 20 MHZ b) 10 MHZ c) 8 MHZ d) 5 MHZ

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 Question Paper for Digital Electronic
Q12. 12 MHz clock frequency is applied to a cascaded of Modulus- 3 counter , Modulus- 4 counter &
Modulus- 5 counter. What are the lowest output frequency and overall modulus respectively?

a) 200 KHz, 60 b) 1MHz, 60 c) 3 MHz, 12 d) 4 MHz, 12

Q13. In order to added 1111 + 1101 we have

a) One Full adder & one Half adder b) Three Full adder & one Half adder
c) Two Full adder & Two Half adder d) Three half adder & one full adder

Q14. The Octal equivalent of the HEX number AB.CD is

a) 253.14 b) 253.632 c) 526.314 d) 526.632

Q15. Consider two 4- bit numbers A= A3A2A1Ao and B= B3B2B1Bo and the expression Xi=AiBi + AiBI for i=
0,1,2,3. The expression A3B3 + X3 A2B2+ X3 X2A1B1+ X3 X2 X1A0B0 evaluates to1 if

a) A=B b) A B c) A> B d) A< B