Vcc
16 - bit Address/Data Bus
CLK
RESET
A16 - A19 / S3 - S6
READY
4 - bit Address/Status Bus
TEST
BHE / S7
NMI
MN / MX
(MAX INTR 8086 (MAX
MODE) RD MODE)
(QS1)/INTA WR/(LOCK)
SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%
In 8088 CPU:
Length of internal FIFO queue is 4-bytes.
AD8 to AD15 changes to A8 to A15 as only 8-bit data bus is there.
Signal BHE/S7 changes to SSO, which is logically equivalent to signal S0.
The signal is always HIGH when 8088 is operating in maximum mode.
M/IO becomes IO/M.
Other pin functions and definitions remain same.
PIN FUNCTION
Vcc +5V +/- 10%
Gnd Ground pin connected to system ground. Two ground pins
Clock input signal with 33% duty cycle. It Determines the speed of
CLK
processor.
It causes the processor to reset itself if the RESET is high atleast for 4
clock periods.
RESET
At reset processor sets CS = FFFFh and clear the PSW, IP, DS, ES, SS
and instruction queue (IPQ).
Address/Data multiplexed bus. The address comes first and can be
AD0-AD15
latched externally. Then bus can be made free to carry the data.
Address/Status bus multiplexed bus. The upper 4-bit address comes
first and then come the status signals.
Status S6 always LOW i.e. S6=0 always.
A16-A19 /
Status S5 gives current status of IF flag i.e. S5=IF always.
S6 S3
Status S4 & S3 gives the information about current segment (register)
being used as shown below. The S4 & S3 bits may also be used as A21
& A20 to address four separate 1MB-memory banks.
Status Signals
Meaning
S4 S3
0 0 Extra Segment
0 1 Stack Segment
1 0 Code or No Segment
1 1 Data Segment
Bus High Enable. A LOW on this pin enables the most significant
BHE/S7 data bus (D8-D15) during a read or write operation. After BHE
information, comes the status S7 which always remains LOW.
Read signal. A LOW on this signal instructs the selected I/O or
RD
memory device to give its data content onto the data bus.
Slow peripheral or memory devices use it. A LOW on this input tells
the processor that the device is not yet ready for data transfer and
READY
thus causing processor to enter into wait states. A HIGH on this
input continues normal operation of 8086.
Interrupt Request. A level triggered interrupt. External hardware
INTR can used this pin to interrupt normal operation of processor. This
signal is recognized if and only if flag IF=1 in flag register.
Non Maskable Interrupt. A positive edge triggered interrupt.
NMI Always served by the 8086 irrespective of status of IF flag. Thus
always used for critical conditions.
Test input is sampled by WAIT instruction of 8086. If TEST=1 the
WAIT instruction waits for this signal to become 0. As soon as it
TEST
becomes 0 processor works further. If it is already 0 WAIT
instruction works as NOP.
Minimum/Maximum Mode. A LOW on this signal configures the
MN/MX 8086 in maximum mode and a HIGH configures it to minimum mode
of operation.
There are total 8-pins which have dual meaning and have different definitions in
minimum and maximum mode of operation. The maximum mode pin names are
indicated within the brackets in the logic diagram.
Status Bits. These bits indicate the function of current bus cycle. These
S2,S1,S0 pins are decoded externally by the 8288 bus controller. The below table
summarizes the function encoded on these bits.
STATUS BITS
MEANING
S2 S1 S0
0 0 0 Interrupt Acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 HALT
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive or Inactive
SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%
10K
RESET RESET
10
RES
uF
SYSTEM
RESET
CLK AMWC
Control C
Inputs
AEN 8288 AIOWC
CEN INTA
IOB DEN Addr Latch,
ALE Transceiver
Power Vcc
DT/R Controls
Supply
Gnd
MCE/PDEN
Logic Diagram 8288 BUS CONTROLLER
PIN FUNCTION
POWER SUPPLY
Vcc +5V +/- 10%
Gnd Ground pin connected to system ground.
STATU INPUTS
S0, S1, S2 Status Inputs. Connected to corresponding status pins of 8086.
CONTROL INPUTS
CLK Clock Input. It must be connected to CLK output pin of 8284.
Address Enable. A low on this input causes the 8288 to enable memory
AEN
control signals.
Control Enable. A high on this input enables the command output
CEN
signals of 8288.
I/O Bus Mode. A high on this input selects I/O bus mode while a low
IOB
selects system bus mode.
COMMAND SIGNALS
MRDC Memory Read Control Signal.
MWTC Memory Write Control Signal.
IORC I/O Read Control Signal.
IOWC I/O Write Control Signal.
Advance Memory Write Control Signal. Same as MWTC signal but the
AMWC
signal is activated one clock pulse earlier than the normal write.
Advance I/O Write Control Signal. Same as IOWC signal but the signal is
AIOWC
activated one clock pulse earlier than the normal write.
INTA Interrupt Acknowledge. Same as INTA of 8086
DT/R Same as DT/R of 8086.
ALE Same as ALE of 8086.
DEN Same as DEN of 8086. Note that it is active high signal in 8288.
Master Cascade/Peripheral Data. It selects master cascade operation
MCE/PDEN (MCE) for 8259 interrupt controller if IOB=0 and if IOB=1 it enables the
IO bus transceivers (PDEN) which is used in multibus configuration.