Grading System
Passing Grade=>60
Field Effect Transistor (FET)
Field Effect Transistor
• FET is generally a three terminal device which could be used in applications
wherein bipolar junction transistors are used.
• It is a voltage controlled device as compared to a BJT which is a current
controlled device.
– Output voltages and currents are controlled by the input voltage rather
than by the input current.
• The term field effect is used because for FETs, an electric field established by
the carriers controls the conduction path of the output current without the
need for direct contact between the input signal parameters and the output
signal parameters.
• It is a unipolar device because current flow is only dependent on either
electron flow (n channel) or hole flow (p channel).
– BJT is a bipolar device because current flow is always dependent on
electron flow (n material) and hole flow (p material).
FET and BJT Comparison
• FETs have very high input impedance (1 Mohm or higher), because the p-n
junction at the input is operated in the revere bias condition. This is higher
than those of BJTs.
• FETs are more temperature stable compared to BJTs.
• FETs are usually smaller than BJTs making them useful in integrated
circuits.
• FETs are less sensitive to changes in the applied signal compared to BJTs,
resulting to smaller voltage gains than BJT voltage gain.
• FETs are usually more sensitive to handling compared to BJT.
Basic Types of FET
• The three basic types of FET are:
– Junction field effect transistor (JFET)
– Metal oxide semiconductor field effect transistor (MOSFET), which
has two types:
• Depletion MOSFET
• Enhancement MOSFET
– Metal semiconductor field effect transistor (MESFET)
• FETs could also be classified as n-channel FET and p-channel FET.
• The n-channel FET is more dominant than the p-channel FET.
Junction Field Effect Transistor JFET
• JFETs have three terminals: Gate, Drain and the Source.
• The Gate is used to control the flow of current flowing through the drain and
the source.
• The drain current is the same as the source current. Both currents flow
through the channel of the FET.
• The construction of an n-channel and that of p-channel JFET are shown
below: Drain (D) Drain (D)
ID = drain current ID = drain current
p p n n
Gate (G) Gate (G)
n p
N-channel JFET with VGS= o volt and VDS is positive at the Drain
Junction Field Effect Transistor JFET
– Conventional current flows from Drain to Source through the channel,
and the current is only limited by the resistance of the n-channel between
the drain and the source.
– Drain current (ID) is equal to the Source current (IS).
– When Drain to Source voltage (VDS) increases, Drain current (ID) and
Source current (IS). also increase until VDS reaches the pinch off voltage
(Vp).
– When VDS increases beyond VP, Drain current (ID) does not increase and
practically remains at a constant saturation level called IDSS.
• This indicates that the Drain to Source resistance is approaching an
“infinite” value, as any increase in VDS does not result in an increase
in Drain current.
• This is caused by both depletion regions becoming very wide that they
“touch” each other, and that they almost close the n-channel (small
current path still exists).
• As the Drain to source voltage (VDS) increases beyond Vp, the region
of close contact between the two depletion region increases.
– IDSS is the maximum Drain current (Source current also, ID=IS) for the
JFET when VGS = 0 volt and VDS > |VP|, as long as VDS does not reach the
breakdown voltage.
Junction Field Effect Transistor JFET
– When VDS reaches the maximum allowed value (breakdown voltage –
VDS max , Drain current becomes very high and the FET could be damaged.
– For low values of VDS (VDS < VP) , resistance from drain to source is
relatively constant. In this region, JFET can be used as a constant
resistance source.
– Gate current (IG) is equal to zero because the p-n junctions are reverse
biased.
– For p-channel JFET, the same conditions exist, except the polarity of the
Drain to Source voltage (VDS) is reversed, and the direction of the Drain
current (IDS) is also reversed.
Junction Field Effect Transistor JFET
ID (mA)
Saturation Level
(IDSS) VGS = 0 v
Drain
saturation
current
VDS (V)
Vp
(pinch off
voltage)
ID (mA)
JFET Characteristic Curve When VGS = 0 volt
Junction Field Effect Transistor JFET
• The Drain current is typically controlled by varying the Gate to Source
voltage (VGS).
• When VGS is more negative than the Source (for n-channel) and the Drain to
Source voltage (VDS) is positive at the Drain, the following conditions exist:
– Gate to Source voltage (VGS) is more reverse bias than when Gate to
Source voltage is equal to zero.
9v
N-channel JFET with VGS= o volt and VDS is positive at the Drain
Junction Field Effect Transistor JFET
– The depletion region between the Gate and the Source is wider than when
the Gate to Source voltage is equal to zero.
– As the Gate to Source voltage becomes more negative at the Gate, the
saturation level of the Drain current decreases and saturation level occurs
at lower values of VDS.
• This is because the two depletion regions come into contact with each
other earlier than when the Gate to Source voltage is zero.
• The pinch off voltage (Vp) drops in a parabolic manner as VGS
becomes more and more negative.
• Eventually, the Drain current becomes equal to zero when VGS
becomes equal to the pinch off voltage (Vp) for that particular
condition. (Vp changes as VGS change). This particular Vp is also
called VGS (off) .
• When VGS becomes equal to VGS (off), the JFET is turned “off”.
– Gate current (IG) is equal to zero all throughout, because the two p-n
junctions are always reverse biased.
– The above conditions also exist for p-channel JFET, except that the
voltages are reverse in polarity and currents are opposite in direction.
Junction Field Effect Transistor (n-channel JFET)
Characteristic Curve
Saturation region
ro
rd = = Drain to Source Resistance (ohms)
(1 − VGS/Vp )2
• The saturation region is located at the right side of the locus of pinch off
voltages. It is also called constant current or linear amplification region. In
this region,
– the JFET can act as a constant current source, since any variations in VDS
does not result to changes in Drain current (IDSS).
– the JFET is typically employed as linear amplifier.
• The breakdown region is the region when the maximum Drain to Source
voltage (VDS max) is reached. In this region,
– Drain current becomes very high
– JFET could be damaged
– Drain current is limited by circuit components external to the JFET.
• As seen in the characteristic curve,
– ID ranges from 0 A to IDSS for all levels of VGS between 0 v and pinch off
voltage VGS(off) .
– IDSS is the maximum current and it occurs when VGS = 0 v.
Junction Field Effect Transistor (JFET) Schematic Symbols
• The schematic symbols for n-channel and p-channel JFET are shown below:
+ -
ID ID
Drain (D) Drain (D)
• Current direction and polarity of voltages are for typical JFET configuration.
• For typical biasing,
– Drain current is equal to the Source current.
– Gate to Source p-n junction and Gate to Drain p-n junction are reverse
biased.
– Gate current is equal to zero because both p-n junctions are reverse biased.
– Input signal is at the gate and output is taken from the drain or source.
Junction Field Effect Transistor (JFET) Typical Biasing
• Typical biasing for n-channel and p-channel JFET are shown below:
ID = Drain ID = Drain
current current
Typical Biasing for n-channel JFET Typical Biasing for p-channel JFET
Junction Field Effect Transistor (JFET) Transfer
Characteristics
• The relationship between drain current (ID) and the VGS is defined by Shockley’s
equation shown below:
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
VP
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = VGS off = Pinch off voltage when ID = 0 ampere (volts)
• The power dissipated by a JFET must not exceed its maximum allowable
value or the JFET could be destroyed.
• The maximum power which a JFET could have must be derated as the
operating temperature increases.
• The maximum allowable power dissipation decreases as the temperature of
the JFET increases.
• Derating value is given in specification sheets.
• A derating value of 2 miliwatt per 0C means the maximum power dissipation
of the JFET must be reduced by 2 miliwatts for every degree centigrade
increase in operating temperature.
Junction Field Effect Transistor Linear Operating Region
• The area bounded by the green lines/curves below is the linear operating
region of a JFET. This region is typically used when a JFET is used as a
linear amplifier.
Ohmic Breakdown
region Saturation region region
Saturation
Locus of Level
pinch off for ID when
voltages VGS= 0 v
ID (mA) PDS max
(IDSS)
Drain
Breakdown
saturation
(VDS =VDS max)
current for Linear Operating
VGS = 0 v region
VGS = VGS off = Vp
(pinch off
Voltage
ID = 0 mA VDS (V)
VDS max
• Usually, the values in the specification sheets has a minimum, typical and
maximum value. This must be considered in the design of JFET circuits.
Metal Oxide Semiconductor Field Effect Transistor
(MOSFET)
• MOSFET is one of the most important device in the construction of
integrated circuits, such as those used in digital electronics / computers.
• MOSFETs have the following advantages:
– better temperature stability compared to BJT
– very high input impedance compared to BJT.
• MOSFETs have the following disadvantages:
– It is more sensitive to static electricity which necessitates more care in
handling the device.
– It has lower power handling levels compared to BJT.
• MOSFETs are categorized as depletion type or enhancement type.
Depletion Type MOSFET
• Depletion type MOSFET has the same characteristics as JFET between cutoff
and saturation at IDSS.
• Another name for depletion-type MOSFET is Insulated Gate FET or IGFET.
• It has the added feature of being able to operate with positive and negative
values of VGS. (Unlike JFET which could operate only with negative values of
VGS for n-channel and positive values for p-channel).
• The basic construction of a n-channel depletion type MOSFET is shown
below.
SiO2 (insulator)
n-doped region
n-channel
Drain (D) n
Metal contacts
p Substrate (SS)
Gate (G) n (Silicon
SiO2 (insulator) substrate)
Source (S) n
ID Drain
(D)
n
Substrate
IG =0 (SS)
p
n
Gate (G)
Source n
(S) VDD
IS = ID = IDSS
N-Channel Depletion Type MOSFET Operation
• When the gate has a negative potential relative to the source and the Drain has
a positive potential relative to the Source, the following conditions exist:
– Electrons at the n-type channel will be repelled towards the p-type
substrate and holes at the p-type substrate will be attracted towards the
Gate.
– The electrons at the n-channel will recombine with the holes from the p-
substrate, resulting to lower Drain and Source current.
– The higher is the negative voltage at the gate, the higher is the
recombination rate, and the lower is the Drain and Source current.
Drain
ID (D)
n holes
Substrate Recombination of holes
IG =0 e + (SS) and electrons occur at
e p
+ the channel, resulting to
Gate (G) e lower ID and IS.
n +
Source n
electrons VDD
VGG (S)
IS
N-Channel Depletion Type MOSFET Operation
• When the gate has a positive potential relative to the source and the Drain has
a positive potential relative to the Source, the following conditions exist:
– Electrons at the p-type substrate will be attracted towards the n-channel
because of the leakage current and establish new electron carriers at the n-
channel.
– The electrons from the p-type substrate will produce higher Drain and
Source current.
– The higher is the positive voltage at the gate, the higher is the number of
electrons attracted to the Gate, and the higher is the Drain and Source
current. Drain
ID (D)
n electrons
Substrate Free electrons from the
IG =0 e (SS) substrate are attracted to
e p
the n-channel resulting
Gate (G) e to higher ID and IS.
n
Source n
VGG (S) VDD
IS
N-Channel Depletion Type MOSFET Characteristic Curve
• The characteristic curve for n-channel depletion type MOSFET is shown
below.
Depletion Mode Enhancement Saturation region Breakdown Region
Mode (VDS >=VDS max)
ID (mA)
ID (mA)
12 VGS = 1 v
11 Enhancement
10 Locus of pinch off Region
9 (IDSS) voltages (VGS>0volt)
ID= 8mA=IDSS 8 8 VGS = 0 v
7 7
6 6
5 5 VGS = -1 v Depletion
4 4 Region
3 3 (VGS<0volt)
2 2 VGS = -2 v
1 1 VGS = -3 v
VDS (V)
VGS 2 4 6 VGS = - 4 v =Vp
(volt) -4 -3 -2 -1 0 +1 ID = 0 mA = (VGS off
Vp
In this case)
(pinch off
ID= 0mA ID (mA) Voltage for
VGS = 0 v)
N- Channel Depletion Type MOSFET Characteristic Curve
N-Channel Depletion Type MOSFET Characteristic Curve
• The characteristic curve for depletion type MOSFET is similar to that of
JFET except that positive values of VGS are also present for n-channel and
negative values are also present for p-channel.
– When VGS is equal to Vp (VGS (off)), IDS is equal to 0 A.
– When VGS is equal to 0 v, IDS is equal to IDSS.
• The region for positive VGS is called enhancement region because in this
region, Drain current is increased (“enhanced”) due to the attraction of free
electrons from the p substrate to the n-channel.
• The region for negative VGS is called depletion region because in this region,
Drain current is lessened due to the recombination of electrons at the n-
channel and the holes coming from the p substrate.
• The depletion type MOSFET still follows Shockley’s equation for the Drain
current, both for positive and negative values of VGS.
– Proper sign of VGS must be carefully considered when using Shockley’s
equation.
• The characteristic curve for p-channel depletion type MOSFET is the same
as that of n-channel , but the direction of ID is reversed, the positive values of
VGS will be negative, and negative values of VGS will be positive, because the
polarity of VDD and VGG will be reversed.
P-Channel Depletion Type MOSFET Construction
• The basic construction of a depletion type MOSFET is shown below.
• The construction is the same as that of n-type, but the location of the p-type
and n-type materials are interchanged.
SiO2 (insulator)
p-doped region
p-channel
Drain (D) p
Metal contacts
n Substrate (SS)
Gate (G) p (Silicon
SiO2 (insulator) substrate)
Source (S) p
ID Drain
(D)
p
Substrate
IG =0 (SS)
n
p
Gate (G)
Source p
(S) VDD
IS = ID = IDSS
P-Channel Depletion Type MOSFET Operation
• When the gate has a positive potential relative to the source and the Drain has
a negative potential relative to the Source, the following conditions exist:
– holes at the p-type channel will be repelled towards the n-type substrate and
electrons at the n-type substrate will be attracted towards the Gate.
– The holes at the p-channel will recombine with the electrons from the n-
substrate, resulting to lower Drain and Source current.
– The higher is the positive voltage at the gate, the higher is the
recombination rate, and the lower is the Drain and Source current.
Drain
ID (D) holes
p
Substrate Recombination of holes
IG =0 + e and electrons occur at
e n (SS)
+ the channel, resulting to
Gate (G) e
+ lower ID and IS.
p
Source p
electrons VDD
(S)
IS
P-Channel Depletion Type MOSFET Operation
• When the gate has a negative potential relative to the source and the Drain has
a negative potential relative to the Source, the following conditions exist:
– Holes at the n-type substrate will be attracted towards the p-channel
because of the leakage current and establish new hole carriers at the p-
channel.
– The holes from the n-type substrate will produce higher Drain and Source
current.
– The higher is the negative voltage at the gate, the higher is the number of
holes attracted to the Gate, and the higher is the Drain and Source current.
Drain
ID (D)
p holes
Substrate Holes from the
IG =0 + (SS) substrate are attracted to
+ n
the p-channel resulting
Gate (G) p
+ to higher ID and IS.
Source p
(S) VDD
IS
P-Channel Depletion Type MOSFET Characteristic Curve
• The characteristic curve for p-channel depletion type MOSFET is shown
below.
Depletion Mode Enhancement Saturation region Breakdown Region
Mode (VDS >=VDS max)
ID (mA)
ID (mA)
12 VGS = -1 v
11 Enhancement
10 Locus of pinch off Region
9 (IDSS) voltages (VGS<0volt)
ID= 8mA=IDSS 8 8 VGS = 0 v
7 7
6 6
5 5 VGS = 1 v Depletion
4 4 Region
3 3 (VGS>0volt)
2 2 VGS = 2 v
1 1 VGS = 3 v
VDS (V)
VGS 2 4 6 VGS = 4 v =Vp
(volt) +4 +3 +2 +1 0 -1 ID = 0 mA = (VGS off
Vp
In this case)
(pinch off
ID= 0mA ID (mA) Voltage for
VGS = 0 v)
P- Channel Depletion Type MOSFET Characteristic Curve
Depletion Type MOSFET Schematic Symbols
• The schematic symbols for depletion type MOSFET are shown below:
+ -
ID ID
Drain (D) Drain (D)
Substrate Gate (G) Substrate V
Gate (G) (SS) VDS (SS) DS
- +
n-channel Depletion Type p-channel Depletion Type
MOSFET MOSFET
+ -
ID ID
Drain (D) Drain (D)
- +
n-channel Depletion Type p-channel Depletion Type
MOSFET MOSFET
Depletion Type MOSFET Parameters
• The following are typical depletion Type MOSFET parameters usually given
in specification sheets.
Functional Characteristic
– Noise Figure (NF)
• Usually, the values in the specification sheets has a minimum, typical and
maximum value. This must be considered in the design of MOSFET circuits.
Enhancement Type MOSFET
• The characteristics of enhancement type MOSFET are quite different from
those of depletion type MOSFET.
• Unlike depletion type MOSFET, the transfer characteristic is not defined by
Shockley’s equation.
• The Drain current is zero (cut off) until the gate to source voltage (VGS)
reaches a specific magnitude.
• For n-channel enhancement type MOSFET, current control at the Drain is
now done using positive voltages at the Gate, rather than negative voltages
used in n-channel JFET and n-channel depletion type MOSFET.
• For p-channel enhancement type MOSFET, current control is also opposite
that of p-channel JFET and p-channel depletion type MOSFET.
N-Channel Enhancement Type MOSFET Construction
• The construction of an n-channel enhancement type MOSFET is shown
below.
• The construction of n-channel enhancement type MOSFET is similar to that
of n-channel depletion type MOSFET, except that there is no n-channel
connecting the n-type regions at the Drain and the Source
SiO2 (insulator)
n-doped region
no channel
Drain (D) n
Metal contacts
p Substrate (SS)
Gate (G) (Silicon
SiO2 (insulator) substrate)
Source (S) n
ID=0 Drain
(D)
n
Substrate
IG =0 (SS)
p
Gate (G)
Source n
(S) VDD
IS = ID = 0
N-Channel Enhancement Type MOSFET Operation
• When the gate has a positive potential relative to the source and the Drain has
a positive potential relative to the Source, the following conditions exist:
– Electrons at the p-type substrate will be attracted towards the Gate and
holes at the p-type substrate will be repelled towards the substrate
terminal, thus producing free electrons at the area between the n-type
materials at the Drain and the Source.
– If the positive Gate voltage is high enough to attract a substantial number
of free electrons, an n-type channel is produced in the area between the two
n-type materials.
– The creation of an n-type channel results to current flow at the Drain and
the Source.
– The higher is the positive voltage at the gate, the higher is the number of
electrons attracted to the Gate, and the higher is the Drain and Source
current.
– The level of VGS that results to significant increase in ID is called Threshold
voltage (VT or VGS (TH)).
– If VGS =< VT , ID is equal to zero.
– Gate current is still equal to zero because of the insulating material.
N-Channel Enhancement Type MOSFET Operation
– If VGS is held constant at a positive value and VDS is increased positively, ID
will eventually reach a saturation level (VDS sat), and ID will not increase
even if VDS is increased.
• The saturation is due to pinching off of the channel (narrower channel)
near the Drain.
• If VDS is continuously increased after saturation has been reached, it will
eventually reach a breakdown value (VDS max) and ID will rise abruptly.
– Since there is no n-channel when VGS is equal to zero, and an n-channel is
created (enhanced) when VGS=VT, the device is called n-channel
enhancement type MOSFET. N-channel is created here
Drain if positive VGS is high
ID (D) enough (VGS > VT)
n
Substrate
IG =0 e + (SS)
e
Gate (G) +
e
+ p
Source n
Holes VDD
(S) electrons
IS
N-Channel Enhancement Type MOSFET Operation
– The saturation level for VDS (VDS sat) can be computed as:
VDSsat = VGS − Vgs (Th) = Drain to Source voltage saturation level (volts)
where : VGS = Gate to Source voltage (volts)
Vgs (Th) = Gate to Source Threshold voltage (volts)
– Different saturation level for VDS exist for different levels of VGS.
– The greater is the value of VGS, the greater is the saturation level for
VDS.
– For levels of VGS <= VT, the drain current (ID) is equal to zero.
– For levels of VGS > VT, the drain current (ID) can be computed as:
no channel
Drain (D) p
Metal contacts
n
Gate (G) (Silicon Substrate (SS)
SiO2 (insulator) substrate)
Source (S) p
ID=0 Drain
(D)
p
Substrate
IG =0 (SS)
n
Gate (G)
Source p
(S) VDD
IS = ID = 0
P-Channel Enhancement Type MOSFET Operation
• When the gate has a negaive potential relative to the source and the Drain has
a negative potential relative to the Source, the following conditions exist:
– Holes at the n-type substrate will be attracted towards the Gate and
electrons at the n-type substrate will be repelled towards the substrate
terminal, thus producing holes at the area between the p-type materials at
the Drain and the Source.
– If the negative Gate voltage is high enough to attract a substantial number
of holes, a p-type channel is produced in the area between the two p-type
materials.
– The creation of an p-type channel results to current flow at the Drain and
the Source.
– The higher is the negative voltage at the gate, the higher is the number of
holes attracted to the Gate, and the higher is the Drain and Source current.
– The level of VGS that results to significant increase in ID is called Threshold
voltage (VT or VGS (TH)).
– If VGS =< VT , ID is equal to zero.
– Gate current is still equal to zero because of the insulating material.
P-Channel Enhancement Type MOSFET Operation
– If VGS is held constant at a negative value and VDS is increased negatively, ID
will eventually reach a saturation level (VDS sat), and ID will not increase
even if VDS is increased negatively.
• The saturation is due to pinching off of the channel (narrower channel)
near the Drain.
• If VDS is continuously increased after saturation has been reached, it will
eventually reach a breakdown value (VDS max) and ID will rise abruptly.
– Since there is no p-channel when VGS is equal to zero, and a p-channel is
created (enhanced) when VGS=VT, the device is called p-channel
enhancement type MOSFET. p-channel is created here
Drain if positive VGS is negatively
ID (D) high enough (VGS > VT)
p
Substrate
IG =0 + e (SS)
+
Gate (G) e
+ e
p
Source p
Holes VDD
(S) electrons
IS
P-Channel Enhancement Type MOSFET Operation
– The saturation level for VDS (VDS sat) can be computed as:
VDSsat = VGS − VGS(Th) = Drain to Source voltage saturation level (volts)
where : VGS = Gate to Source voltage (volts)
VGS(Th) = VT = Gate to Source Threshold voltage (volts)
– Different saturation level for VDS exist for different levels of VGS.
– The greater is the value of VGS, the greater is the saturation level for
VDS.
– For levels of VGS <= VT, the drain current (ID) is equal to zero.
– For levels of VGS > VT, the drain current (ID) can be computed as:
- +
n-channel Enhancement Type p-channel Enhancement Type
MOSFET MOSFET
+ -
ID ID
Drain (D) Drain (D)
- +
n-channel Enhancement Type p-channel Enhancement Type
MOSFET MOSFET
MOSFET Handling
• MOSFETs are more sensitive to static electricity compared to BJT and JFET.
• Static electricity from surroundings are usually high enough to produce
destructive potential difference across the SiO2 insulator inside MOSFETs.
This could destroy the thin layer of SiO2 .
• The shorting foil / conductors connecting the leads when MOSFETs are
shipped should be kept in place until MOSFETs are installed.
– This will prevent potential difference from appearing across the terminals
of the device.
• Always touch the MOSFET at its casing to prevent introduction of static
electricity at its terminals.
• The power supply of circuits must be turned off before removing boards
containing MOSFETs to prevent surges from destroying the device.
• Two zener diodes placed back to back can be installed between the gate and
the source to prevent excessive voltages from being applied across the two
terminals.
Enhancement Type MOSFET Parameters
Switching Characteristics:
– Turn on delay (tdl) – time for device to start switching on after input signal is
applied
– Rise Time (tr) - time for device to reach on level after starting to switch on
– Turn off delay (td2) – time for device to start switching off after input is applied
– Fall time (tf) – time for device to fall to off condition after starting to switch off
Vertical Metal Oxide Silicon FET (VMOS)
n+ n+
p e e p
effective length
of channel
e e
n + substrate n + substrate
+
ID
Drain (D)
Gate (G)
- VDS
• Current direction and polarity of voltages are for typical MESFET configuration.
• For typical biasing, Drain current is equal to the Source current.
N-Channel Depletion Type MESFET Typical Biasing
• Typical biasing for n-channel depletion type MESFET is shown below.
• Gate current is equal to zero.
• Source current is equal to the Drain current.
ID = Drain
current
Drain (D)
Gate (G)
VDS
IG (Gate
Source (S)
Current)
=0 VGS IS = Source
VGG Source current
(S) IS=ID
IG = 0 A
IS = ID
• The preceding equations are applicable only when the devices are in the
active region.
• Like BJTs, FETs can be biased using many ways.
• Some of the most common used biasing techniques for FETs are:
– Fixed biased
– Self biased
– Voltage divider biased
JFET Fixed Bias Configuration
• Fixed bias configuration for common source n-channel JFET is shown
below.
ID = Drain
RD current Cc2
Cc1 IG= 0
Drain (D)
Gate (G) VDD
Assuming supply voltages and resistors allow JFET to operate in the active region, the following equation applies :
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
VP
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
JFET Fixed Bias Configuration
• Fixed bias configuration for common source p-channel JFET is shown
below.
ID = Drain
RD current Cc2
Cc1 IG = 0
Drain (D)
Gate (G) VDD
Assuming supply voltages and resistors allow JFET to operate in the active region, the following equation applies :
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
VP
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
JFET Fixed Bias Configuration
• RG is placed to make sure that the AC input voltage (Vi) appears at the gate.
• RD is placed to make sure that the AC signal between the Drain and the Source
appear at the output (Vo).
• VDD is the supply voltage for the Drain while VGG is the biasing voltage for the
Gate. VGG keeps the p-n junction at the gate reverse biased, thus gate current is
always equal to zero.
• CC1 and CC2 are coupling capacitors. CC1 prevents DC voltages at the input from
appearing at the gate of the JFET, while CC2 prevents DC voltages at Drain from
appearing at the output of the circuit.
• For DC analysis, CC1 and CC2 can be considered “open” circuits.
• For AC analysis, CC1 and CC2 can be considered “short” circuits.
• For the DC analysis:
IG = IGQ = 0 A
IS = ISQ = ID = IDQ= Drain Quiescent Current = Source Quiescent Current
VRG = Voltage across RG= (IG)(RG) = 0 volt
VGS = VGSQ = VGG - VRG = VGG = voltage between the Gate and the Source
2
VGS
ID = IDQ = IDSS 1 − = Drain current (Ampere)
VP
JFET Fixed Bias Configuration
• For a certain value of VGG , VGSQ can be determined .
• Once VGSQ and Vp are known, IDQ can be computed or determined from a
graph.
• The output loop equation can be written as follows:
• For a given value of VDD , and known values of ID and RD , VDS (also VDSQ)
can be computed.
• The following are conventions which are also encountered in DC analysis:
• The values determined above are quiescent values (values at Q point), and are
applicable for DC analysis.
JFET Fixed Bias Configuration
• The graphical approach is shown below:
– The graph below can be drawn using the following relationships:
When VGS = 0 ⇒ ID = IDSS
2
0.3VP IDSS
When VGS = 0.3VP ⇒ ID = IDSS 1 − =
VP 2
2
VP/2 IDSS
When VGS = 0.5 Vp ⇒ ID = IDSS 1 − =
VP 4
When VGS = Vp ⇒ ID = 0
ID (mA)
ID= IDSS
Q point
ID= IDQ
VGS 0
(volt)
VGSQ = - VGG
ID= 0mA
JFET Fixed Bias Configuration
• Example: Given Fixed Bias JFET circuit with the following parameters:
RG = 1.5 Mohm, RD = 2.5 kohm, VDD = 15 volts,
VGG= 2 volts, IDSS = 9 mA, Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS
When VGS = Vp = -7 V ID = 0 A
When VGS = Vp / 2 = - 3.5 V ID = IDSS / 4 = 9 x 10-3 / 4 = 2.25 x 10-3 A
When VGS = 0.3 Vp = - 2.1 V ID = IDSS / 2 = 9 x 10-3 / 2 = 4.5 x 10-3 A
When VGS = 0V ID = IDSS = 9 x 10-3 A
Assuming supply voltages and resistors allow JFET to operate in the active region, the following equation applies :
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
VP
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
JFET Self Bias Configuration
• Self bias configuration for common source p-channel JFET is shown
below.
RD ID = Drain
current Cc2
IG = 0
(Gate Current)
Drain (D) _
Gate (G) VDD
Cc1 + VDS
S +
VGS _ VO= Output voltage
_
Vi = IRG= 0 IS = Source
Input voltage RG RS current
IS=ID
+
Assuming supply voltages and resistors allow JFET to operate in the active region, the following equation applies :
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
VP
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
JFET Self Bias Configuration
• Self bias configuration for common gate n-channel JFET is shown
below.
RD ID = Drain
current Cc2
IG = 0
(Gate Current)
Drain (D) +
Gate (G) VDD
_
S _ VDS VO= Output voltage
VGS +
RS +
Vi =
IS = ID Input voltage Cc1
_
Assuming supply voltages and resistors allow JFET to operate in the active region, the following equation applies :
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
VP
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
JFET Self Bias Configuration
• The gate to source voltage (VGS) is now determined by the voltage across Rs.
• There is no DC current flowing across RG (voltage across RG = 0) , and VGS is
equal to the voltage across Rs which is a function of the Source or Drain current.
VGS is now a function of Drain current and is no longer fixed.
• VDD is the supply voltage for the Drain.
• CC1 and CC2 are coupling capacitors. CC1 prevents DC voltages at the input from
appearing at the gate of the JFET, while CC2 prevents DC voltages at Drain from
appearing at output of the circuit.
• For DC analysis, CC1 and CC2 can be considered “open” circuits.
• For AC analysis, CC1 and CC2 can be considered “short” circuits.
• For the DC analysis (Applicable for common Source or common Gate):
RG can be replaced by a short circuit since there is no current across RG .
IG = IGQ = 0 A
IS = ISQ = ID = IDQ = Drain Quiescent Current = Source Quiescent Current
VG = 0 v
VRS = Voltage across RS = (IS)(RS)
VGS = VGSQ = - VRS = - (IS)(RS) = - (ID)(RS)
2 2
VGS (ID )(RS)
ID = IDQ = IDSS 1 − = IDSS 1 −
= Drain current (Ampere)
VP VP
JFET Self Bias Configuration
• The resulting quadratic equation can be solved for ID.
• For a certain value of ID , VGSQ can be determined .
• The output loop equation can be written as follows:
• For a given value of VDD , and known values of ID, RD and RS, VDS (also VDSQ) can
be computed.
• The following are conventions which are also encountered in DC analysis:
• The values determined above are quiescent values (values at Q point), and are
applicable for DC analysis.
JFET Self Bias Configuration
• The graphical approach is shown below (applicable for common Source or
common Gate:
1. The point when VGS = 0 is when ID = 0 (VGS = - IDRS )
IDSS - IDSS RS
2. When ID = ⇒ VGS =
2 2
3. A straight line can be drawn between the points (VGS = 0 , ID = 0)
- IDSS RS IDSS
and VGS = ID =
2 2
4. Based on the intersection of the straight line and the transfer characteristic curve
for the FET, IDQ and VGSQ can be determined.
5. The values of the other parameters can then be computed.
ID= IDSS ID (mA)
VGS 0
(volt) VGSQ
JFET Self Bias Configuration
• Example: Given Self Bias JFET circuit with the following parameters:
RG = 1.5 Mohm, RD = 2.5 kohm, RS = 1 kohm, VDD = 15 volts,
IDSS = 9 mA, Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS
( )
2
- (ID )(1000)
ID = 9 x 10 −3 1 − = −3
− D + 20,408ID = −3
− 2.565ID + 183ID
2
9 x 10 1 285I 9 x 10
-7
0 = 9 x 10 −3 − 3.565ID + 183ID
2
When VGS = Vp = -7 V ID = 0 A
When VGS = Vp / 2 = - 3.5 V ID = IDSS / 4 = 9 x 10-3 / 4 = 2.25 x 10-3 A
When VGS = 0.3 Vp = - 2.1 V ID = IDSS / 2 = 9 x 10-3 / 2 = 4.5 x 10-3 A
When VGS = 0 V ID = IDSS = 9 x 10-3 A
The transfer characteristic curve is drawn based on these points.
ID (mA)
For ID = (VGSQ)(RS): 12
When ID = 7 mA, VGS = - (7 x 10-3)(1000) = - 7 volts 11
10
When ID = 0 mA, VGS = 0 volts ID= 9 mA = IDSS 9
A straight line is drawn between these two points 8
7
6
Based on graph, 5
VGS = - 7 v , ID = 7 mA
Q 4
VGSQ = -3v ,
3
IDQ is around 3 A 2
1
The values of the other parameters are computed VGS
as in the mathematical approach. (volt) -8 -7 -6 -5 -4 -3 -2 -1
VGS = 0 , ID = 0
JFET Voltage Divider Bias Configuration
• Voltage divider bias configuration for common source n-channel JFET
is shown below.
+ RD ID = Drain
IRG1 current Cc2
RG1 IG = 0
(Gate Current)
_ Drain (D) +
Gate (G) VDD
_
Cc1 + S _ VDS VO= Output voltage
VGS +
Vi = +
RG2 IS = Source
Input voltage IRG2 RS current
_
_ IS=ID
Typical Voltage Divider Bias Configuration For Common Source N-channel JFET
Assuming supply voltages and resistors allow JFET to operate in the active region, the following equation applies :
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
VP
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
JFET Voltage Divider Bias Configuration
• Voltage divider configuration for common source p-channel JFET is
shown below.
_ RD ID = Drain
IRG1 current Cc2
RG1 IG = 0
(Gate Current)
Drain (D) _
+ Gate (G) VDD
Cc1 + VDS
_ S +
VGS _ VO= Output voltage
_
Vi = RG2 IS = Source
Input voltage IRG2 RS current
IS=ID
+ +
Typical Voltage Divider Bias Configuration For Common Source P-channel JFET
Assuming supply voltages and resistors allow JFET to operate in the active region, the following equation applies :
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
VP
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
JFET Voltage Divider Bias Configuration
• Similar to voltage divider bias for BJT, except IG = 0 .
• CC1 and CC2 are coupling capacitors. CC1 prevents DC voltages at the input from
appearing at the gate of the JFET, while CC2 prevents DC voltages at Drain from
appearing at output of the circuit.
• For DC analysis, CC1 and CC2 can be considered “open” circuits.
• For AC analysis, CC1 and CC2 can be considered “short” circuits.
• Since Gate current must be equal to zero, IRG1 and IRG2 must be equal.
IG = 0 IRG1 = IRG2 = VDD / (RG1 + RG2)
• The voltage across RG1 and RG2 can be computed as:
V RG2 = VDD - V RG1 = (VDD)(RG2) / (RG1 + RG2)
• Applying Kirchoff’s voltage law along Gate to Source loop, the following
equation can be derived:
VG = VRG2 = VGS + VRS = VGS + (ID)(RS) = voltage at gate relative to ground
VGS = VG - VRS = VG - (ID)(RS) = VRG2 - (ID)(RS) =Voltage across gate and source
JFET Voltage Divider Bias Configuration
• Shockley’s equation can be used to compute for ID.
2 2
VGS VRG2 - (ID )(RS)
ID = IDQ = IDSS 1 − = IDSS 1 −
= Drain current (Ampere)
VP VP
• For a given value of VDD , and known values of ID, RD and RS, VDS (also VDSQ) can
be computed.
• The following are conventions which are also encountered in DC analysis:
• The values determined above are quiescent values (values at Q point), and are
applicable for DC analysis.
JFET Voltage Divider Bias Configuration
• Graphical approach can also be used.
VGS = VRG2 - (ID)(RS) = Voltage across gate and source
A straight line for the above equation can be drawn and the intersection of the
line and the transfer characteristic curve of the JFET can be determined, to
determine the quiescent values.
VGS = VRG2 , ID = 0
VGS 0
(volt) VGSQ
JFET Voltage Divider Bias Configuration
• Example: Given voltage divider bias JFET circuit with the following
parameters:
RG1 = 2.5 Mohm, RG2 = 250 kohm , RD =1.5 kohm, RS = 2.4 kohm, VDD =
15 volts, IDSS = 9 mA, Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS
= - 3.628 volts
When VGS = Vp = -7 V ID = 0 A
When VGS = Vp / 2 = - 3.5 V ID = IDSS / 4 = 9 x 10-3 / 4 = 2.25 x 10-3 A
When VGS = 0.3 Vp = - 2.1 V ID = IDSS / 2 = 9 x 10-3 / 2 = 4.5 x 10-3 A
When VGS = 0 V ID = IDSS = 9 x 10-3 A
The transfer characteristic curve is drawn based on these points.
VGS = VRG2 - (0)(RS) = VRG2 (when ID = 0 ) ID (mA)
= (VDD)(RG2) / (RG2 + RG1) 12
= 15 (250,000) / (250,000 + 2.5 x 106) 11
=1.364 volts (when ID = 0 ) 10
ID = VRG2 / RS (when VGS = 0) ID= 9 mA = IDSS 9
8
ID = 15 (250,000) / [(250,000 + 2.5 x 106)(2400)]
7
=0.568 X 10 – 3 A (when VGS = 0) 6
VGS = - 7 v , ID = 7 mA 5
A straight line is drawn between these two points. 4
ID = 0
Q 3
Based on graph,
2
VGSQ is around - 3.6 volts
1
IDQ is around 2.2 mA
VGS
(volt) -8 -7 -6 -5 -4 -3 -2 -1 1 2
The values of the other parameters are computed VGS = 0
as in the mathematical approach.
JFET with Drain and Source Supply Configuration
+ VDD = 18 volts
RD = 2K ID = Drain
current Cc2
IG = 0
(Gate Current)
Drain (D) +
Gate (G)
_
S _ VDS VO= Output voltage
VGS +
+
IS = ID RS = 1500
-
-VSS = - 5 volts
Assuming supply voltages and resistors allow JFET to operate in the active region, the following equation applies :
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
V P
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
JFET with Drain and Source Supply Configuration
• Example: Given the JFET circuit in the preceding slide with the following
parameters:
RD =2 kohm, RS = 1.5 kohm, VDD = 18 volts, VSS = -5 volts IDSS = 9 mA,
Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS
ID = 9 x 10 −3 1 − = 9 x 10 −3
[1.714 - 214.286ID]
2
-7
[
= 9 x 10 −3 2.938 - 734.572 ID + 45,918.49 ID 2 ]
0 = 26.44x 10 −3 − 7.611 ID + 413.266 ID
2
Typical Voltage Divider Bias Configuration For Common Source n-channel Depletion Type MOSFET
Assuming supply voltages and resistors allow MOSFET to operate in the active region, the following equation applies :
2
VGS
ID = IDSS 1 − = Drain current (Ampere)
VP
where : IDSS = Saturation Drain current when VGS = 0 v (Ampere)
VGS = Gate to Source voltage (volts)
VP = VP(off) = Pinch off voltage (volts) = VGS when ID = 0 ampere
Depletion Type MOSFET Voltage Divider Bias Configuration
• Similar to voltage divider bias for BJT, except IG = 0 .
• CC1 and CC2 are coupling capacitors. CC1 prevents DC voltages at the input from
appearing at the gate of the MOSFET, while CC2 prevents DC voltages at Drain
from appearing at output of the circuit.
• For DC analysis, CC1 and CC2 can be considered “open” circuits.
• For AC analysis, CC1 and CC2 can be considered “short” circuits.
• Since Gate current must be equal to zero, IRG1 and IRG2 must be equal.
IG = 0 IRG1 = IRG2 = VDD / (RG1 + RG2)
• The voltage across RG1 and RG2 can be computed as:
V RG2 = VDD - V RG1 = (VDD)(RG2) / (RG1 + RG2)
• Applying Kirchoff’s voltage law along Gate to Source loop, the following
equation can be derived:
VG = VRG2 = VGS + VRS = VGS + (ID)(RS) = voltage at gate relative to ground
VGS = VG - VRS = VG - (ID)(RS) = VRG2 - (ID)(RS) =Voltage across gate and source
Depletion Type MOSFET Voltage Divider Bias Configuration
• Shockley’s equation can be used to compute for ID.
2 2
VGS VRG2 - (ID )(RS)
ID = IDQ = IDSS 1 − = IDSS 1 −
= Drain current (Ampere)
VP VP
• For a given value of VDD , and known values of ID, RD and RS, VDS (also VDSQ) can
be computed.
• The following are conventions which are also encountered in DC analysis:
• The values determined above are quiescent values (values at Q point), and are
applicable for DC analysis.
Depletion Type MOSFET Voltage Divider Bias Configuration
A straight line for the above equation can be drawn and the intersection of the
line and the transfer characteristic curve of the JFET can be determined, to
determine the quiescent values.
VGS = VRG2 , ID = 0
VGS 0
(volt) VGSQ
Depletion Type MOSFET Voltage Divider Bias Configuration
• Example: Given voltage divider bias for n-channel depletion type MOSFET
circuit with the following parameters:
RG1 = 100 Mohm, RG2 = 8 Mohm , RD =2 kohm, RS = 800 ohm, VDD = 18
volts, IDSS = 9 mA, Vp= -7 volts. Determine:
a. VGSQ
b. IDQ
c. VDSQ
d. VD
e. VG
f. VS
g. IDQ and VGSQ when RS is changed to 100 ohms
= - 2.136 volts
VGSQ = VRG2 − ID RS
VDD RG2 (18) (8x106 ) −3
= − ID RS = − (9 .893x10 ) (100)
RG2 + RG1 8x106 + 100x106
= 0.344 volts (VGS is now positive. Positive VGS is possible for depletion type
MOSFETs)
• Specifications sheet typically indicate the threshold voltage VGSth and a level
of drain current (IDon) for a particular value of VGS (VGSon). Based on these
values, the constant k can be computed.
Enhancement Type MOSFET Feedback Bias Configuration
RD ID = Drain
current Cc2
RG IG = 0
(Gate Current)
Drain (D) +
VDD
Gate (G)
_
Cc1 S _ VDS VO= Output voltage
VGS +
Vi = IS = Source
Input voltage current
IS=ID
Typical Feedback Bias Configuration For Common Source n-channel Enhancement Type MOSFET
RD ID = Drain
current Cc2
RG IG = 0
(Gate Current)
Drain (D) +
VDD
Gate (G)
_
Cc1 S _ VDS VO= Output voltage
VGS +
Vi = IS = Source
Input voltage current
IS=ID
Typical Feedback Bias Configuration For Common Source P-channel Enhancement Type MOSFET
VD = VG
VDS = VGS
VDS = VDD – IDRD
VGS = VDD – IDRD
• The intersection of the line determined above and the transfer characteristic
curve of the device gives the Q point of the circuit.
Enhancement Type MOSFET Feedback Bias Configuration
(VGS − VGS(Th)) 2 (5 − 2) 2
+ I RD ID = Drain
RG1
IG = 0 current Cc2
RG1 (Gate Current) Drain (D)
_ +
Gate (G) VDD
_
Cc1 + S _ VDS VO= Output voltage
VGS +
Vi = +
RG2 IS = Source
Input voltage IRG2 RS current
_
_ IS=ID
Typical Voltage Divider Bias Configuration For Common Source N-channel enhancement type MOSFET
Enhancement Type MOSFET Voltage Divider Bias
Configuration
_ IRG1 RD ID = Drain
IG = 0 current Cc2
RG1 (Gate Current) Drain (D)
+ _
Gate (G) VDD
Cc1 _ S + VDS VO= Output voltage
VGS
_
Vi = RG2 IS = Source
Input voltage IRG2 RS current
+ + IS=ID
Typical Voltage Divider Bias Configuration For Common Source P-channel enhancement type MOSFET
Enhancement Type MOSFET Voltage Divider Bias Configuration
• CC1 and CC2 are coupling capacitors. CC1 prevents DC voltages at the input from
appearing at the gate of the JFET, while CC2 prevents DC voltages at Drain from
appearing at output of the circuit.
• For DC analysis, CC1 and CC2 can be considered “open” circuits.
• For AC analysis, CC1 and CC2 can be considered “short” circuits.
• Since Gate current must be equal to zero, IRG1 and IRG2 must be equal.
IG = 0 IRG1 = IRG2 = VDD / (RG1 + RG2)
• The voltage across RG1 and RG2 can be computed as:
V RG2 = VDD - V RG1 = (VDD)(RG2) / (RG1 + RG2)
• Applying Kirchoff’s voltage law along Gate to Source loop, the following
equation can be derived:
VG = VRG2 = VGS + VRS = VGS + (ID)(RS) = voltage at gate relative to ground
VGS = VG - VRS = VG - (ID)(RS) = VRG2 - (ID)(RS) =Voltage across gate and source
Enhancement Type MOSFET Voltage Divider Bias Configuration
• The following equation can be used to compute for ID.
• For a given value of VDD , and known values of ID, RD and RS, VDS (also VDSQ) can
be computed.
• The following are conventions which are also encountered in DC analysis:
• The values determined above are quiescent values (values at Q point), and are
applicable for DC analysis.
Enhancement Type MOSFET Voltage Divider Bias Configuration
A straight line for the above equation can be drawn and the intersection of the
line and the transfer characteristic curve of the MOSFET can be determined, to
determine the quiescent values.