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Chapter 1


1.1 Background of the Study

The development of an inexpensive wireless communication, computation and sensing has

created new generation of smart devices. Using ten to thousands of these devices in self-organizing

networks has created new technology called the wireless sensor networks (WSN). The potential of

this system is nothing short of revolutionary [1]. A WSN finds its applications in numerous fields

spanning from home automation, industrial monitoring and to battlefield tracking etc. Some

notable applications include environmental monitoring, fire detection, structural health monitoring

for buildings and bridges, precision monitoring. This system is a great solution for disaster risk


The main components of a wireless sensor node are a microcontroller, transceiver, external

memory power source and one or more sensors shown in Fig. 1. The transceiver enables the

wireless connectivity within the network, connecting an application platform at one end of the

network with one or more sensors. The sensors in a WSN is used to capture physical condition like

pressure and temperature. The power to the nodes are supplied by the batteries [2]. The

microcontroller performs the tasks, process data and controls the functionality of the other

components of the sensor node. An example of a microcontroller used in WSN is the openMSP430.

It is a synthesizable microcontroller compatible with Texas Intrumentss MSP430 family. MSP430

is designed for low cost and specifically low power consumption embedded applications.
External memory in a WSN is very vital for storage of program memory and data memory.

Flash memory is used as a program memory while data memory consists of Static Random

Memory (SRAM) and Electronically Erasable Programmable Read-Only Memory (EEPROM).

Flash memory is the most recent advancement in memory technology. It combines all the best

features of the memory devices [3]. Flash is a nonvolatile memory which can be electronically

erased and reprogrammed. This device was developed from an EEPROM, but unlike EEPROM

the flash memory is able to erase a block of a data in a flash. Flash memories are used due to

their cost and storage capacity. The memory requirements are very much application dependent.

Two categories of memory based on the purpose of the storage are: user memory used for storing

applications related or personal data, and program memory used for programming the device. The

program memory also contains identification data of the device if present. To be able to choose

the best flash memory to be used in a WSN, we must consider its compatibility with the

microcontroller to be used and the type of applications which the WSN would be dedicated.

Figure 1: Wireless Sensor Node block diagram.

1.2 Statement of the Problem
This project aims to provide a thorough understanding and analysis of a low power flash

memory IP and test its functionality and compatibility with the openMSP430 microcontroller via

RTL synthesis using Verilog. This also aims to provide a low power implementation of the flash

memory IP using the tools from Synopsys.

1.3 Objectives of the Study

Through this study, the researcher aims to provide and implement the following:

a.) To provide an understanding of the design architecture of a flash memory IP to

be compatible with the openMSP430 microcontroller core.

b.) To implement and verify the functionality of the RTL code.

c.) To provide a complete ASIC flow of the project.

d.) To provide a low power implementation of the flash memory architecture.

1.4 Significance of the Study

The WSN technology has the capability of quick capturing, processing and transmission

of critical data in real-time with high resolution. However, it has its own limitations such as

relatively low amounts of battery power and low memory availability compared to many existing

technologies. This is what drives the researchers present a low power flash memory with the

specifications compatible to the openMSP430 microcontroller core which will be used for a WSN

application with indoor light energy harvesting for building management and disaster risk

1.5 Scope and Limitations

This study is focused on verifying the functionality of the RTL code of the Flash Memory

IP given that

The flash memory IP to be analyzed in this study is the ST M25P40.

The flash memory will be modelled in Verilog.

The RTL verification and digital ASIC flow will use the tools by Synopsys.

1.6 Definition of Terms

To facilitate the understanding of this study, the following terms are defined:

1.) Wireless Sensor Network (WSN) is a collection of small randomly dispersed devices

that provides three essential functions; the ability to monitor physical and environmental

conditions, the ability to operate device such as switches, motors and actuators and the

ability to provide efficient, reliable communications via wireless networking. It is

composed of spatially distributed autonomous sensors to monitor physical and

environmental conditions and pass their data through the network to a main location.

2.) Sensor Node is a node in a WSN that is capable of performing some processing,

gathering sensory information and communicating with other nodes connected to the

network. Composed of a controller (MCU/other processors), transceiver, external memory,

power supply and sensors.

3.) Microcontroller (MCU) is a self-contained system with peripherals, memory and a

processor that can be used as an embedded system. It is a low-cost computer built for

purpose of dealing specific tasks.

4.) TI MSP430 a mixed-signal microcontroller family from Texas Instruments, built around

a 16-bit cpu and is designed for low cost and specifically low power consumption

embedded applications.

5.) openMSP430 core a synthesizable 16-bit microcontroller core written in Verilog. It is

compatible with TIs MSP430 microcontroller family and can execute code generated by

any MSP430 toolchain in a near cycle accuracy.

6.) Flash Memory a electronic non-volatile memory computer storage medium that can be

electrically erased and reprogrammed. Flash memory retains the data for an extended

period of time whether the flash equipped device is turned on or off.

7.) Register Transfer Level (RTL) - is a design abstraction which models

a synchronous digital circuit in terms of the flow of digital signals (data) between hardware

registers, and the logical operations performed on those signals.

8.) ASIC Application Specific Integrated Circuit or ASIC is an integrated circuit customized

for a particular use. It is a digital or mixed-signal circuit designed to meet specifications

set by a specific project.

9.) Verilog - Verilog HDL is a hardware description language used to design and document

electronic systems. Verilog HDL allows designers to design at various levels of abstraction.

It is the most widely used HDL with a user community of more than 50,000 active


10.) Intellectual Property IP cores that are designs purchased from a third-party as

sub-components of a larger ASIC. They may be provided as and HDL description or as

fully routed designs that could be printed directly onto an ASICs mask.
1.7 Theoretical Framework
This section will provide an overview of the major blocks used in the study and also its

specifications and theories of operation. This section will also present the technology being used

in the entire project:

Figure 1.2: openMSP430 design structure.

1.7.1 openMSP430 Microcontroller core

The openMSP430 core is a synthesizable 16-bit microcontroller core compatible

with Texas Instruments MSP430 family. It is based on a Von Neumann architecture, with a single

address space for instructions and data. Depending on the selected configuration, this design can

either be [5]:

FPGA friendly: the core doesnt contain any clock gate and has only a single clock

domain. As a consequence, in this mode, the Basic Clock Module peripheral has a

few limitations.
ASIC friendly: the core contains up to all clock management options (clock muxes

and low-power modes, fine grained clock gating,..) and is also ready for scan


The design architecture shown in Fig. 2 consists of the following blocks:

Frontend this module performs the instruction Fetch and Decode tasks. It also contains

the execution state machine.

Execution unit contains the ALU and the register file, this module executes the current

decode instruction according to the execution state.

Serial Debug Interface contains all the required logic for Nexus class 3 debugging unit

(without trace). Communication with the host is performed with a standard two-wire

interface following the UART 8N1 or I2C serial protocol.

Memory Backbone this block performs a simple arbitration between front end,

execution-unit, DMA and Serial-Debug interfaces for program, data and peripheral

memory access.

Basic Clock Module generates MCLK, ACLK, SMCLK and manage the low power


SFR Special Function Registers block contain diverse configuration registers (NMI,

Watchdog, and etc).

Watchdog although it is a peripheral, the watchdog is directly included in the core

because of its tight links with the NMI interrupts and PUC reset generation.

16x16 Multiplier the hardware multiplier peripheral is transparently supported

by the GCC compiler and is therefore located in the core. It can be included or excluded at

will through Verilog.

1.7.2 Flash Memory

Flash memory is an electronic non-volatile computer storage memory that can be

electrically erased and reprogrammed. It offers fast read access time (although not as fast as

volatile DRAM memory used for main memory in PCs) and better kinetic shock resistance than

hard disks. Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while

working for Toshiba circa 1980. According to Toshiba, the name flash was suggested by Dr.

Masuokas colleague, Mr. Shoji Ariizumi, because the erasure pressure of the memory contents

reminded him of flash of a camera [1]. Flash memory retains data for an extended period of time

even if the power is turned off.

Flash memory evolved from erasable programmable read-only memory (EPROM) and

electrically erasable programmable read-only memory (EEPROM). Flash is technically a variant

of EEPROM but the industry reserves the EEPROM for byte-level erasable memory and applies

the term flash memory to larger block-level erasable memory. Devices using flash memory erase

data at the block level and rewrite data at the byte level (NOR flash) or multiple-byte page level

(NAND flash). Flash memory is widely used for storage and data transfer in consumer devices,

enterprise systems and industrial applications [6]. Operations of Flash Memory
A basic flash memory cell consists of a storage transistor with control gate and a floating

gate which is insulated from the rest of the transistor by a thin dielectric material or oxide layer.

The floating gate stores the electrical charge and controls the flow of the electrical current.

Figure 1.3. Cross section of a Floating Gate Flash Memory cell.

Electrons are added to or removed from the floating gate to change the storage transistors

threshold voltage to program the cell to be a zero or a one. A process called Fowler-Nordheim

tunneling removes electrons from the floating gate. Either Fowler-Nordheim tunneling or a

phenomenon known as channel hot-electron injection traps the electrons in the floating gate.

When erasing through Fowler-Nordheim tunneling, a strong negative charge on the control

gate forces electrons off the floating gate and into the channel, where a strong positive charge

exists. The reverse happens when using Fowler-Nordheim tunneling to trap electrons in the

floating gate. Electrons are able to forge through the thin oxide layer to the floating gate in the

presence of a high electric field, with a strong negative charge on the cells source and the drain

and a strong positive charge on the control gate.

Figure 1.4: Fowler-Nordheim Tunneling

With channel hot-electron injection (or hot-carrier injection), electrons gain enough energy

from the high current in the channel and attracting charge on the control gate to break through the

gate oxide and change the threshold voltage of the floating gate. Electrons are trapped in the

floating gate, whether a device containing the flash memory cell is powered on or off, because of

the electrical isolation created by the oxide layer.

Figure 1.5: Channel Hot-Electron Injection

EPROM and EEPROM cells operate similarly to flash memory in writing, or

programming, data, but they differ from flash memory in the way they erase data. An EPROM is

erased by removing the chip from the system and exposing the array to ultraviolet light to erase
data. An EEPROM erases data electronically at the byte level, while flash memory erases data

electronically at the block level [8].

1.7.3 Comparison of NOR and NAND

NOR and NAND flash memory differ in architecture and design characteristics. NOR flash

uses no shared components and can connect individual memory cells in parallel, enabling random

access to data. A NAND flash cell is more compact in size, with fewer bit lines, and strings together

floating-gate transistors to achieve greater storage density. NAND is better suited to serial rather

than random data access.

NOR flash is fast on data reads, but it is typically slower than NAND on erases and writes.

NOR flash programs data at the byte level. NAND flash programs data in pages, which are larger

than bytes but smaller than blocks. For instance, a page might be 4 kilobytes (KB), while a block

might be 128 KB to 256 KB or megabytes in size. NAND flash uses less power than NOR flash

for write-intensive applications.

Flash is the least expensive form of semiconductor memory. Unlike dynamic random

access memory (DRAM) and static RAM (SRAM), flash memory is nonvolatile, offers lower

power consumption and can be erased in large blocks. Also on the plus side, NOR flash offers fast

random reads, while NAND flash is fast with serial reads and writes.
Figure 1. 6. NAND and NOR performance comparison.

A solid-state drive (SSD) with NAND flash memory chips delivers significantly higher

performance than traditional magnetic media such as hard disk drives (HDDs) and tape. Flash

drives also consume less power and produce less heat than HDDs. Enterprise storage systems

equipped with flash drives are capable of low latency, which is measured

in microseconds or milliseconds.

The main disadvantages of flash memory are the wear-out mechanism and cell-to-cell

interference as the dies get smaller. Bits can fail with excessively high numbers of program/erase

cycles, which eventually break down the oxide layer that traps electrons. The deterioration can

distort the manufacturer-set threshold value at which a charge is determined to be a zero or a one.

Electrons may escape and get stuck in the oxide insulation layer leading to errors. Anecdotal

evidence suggests NAND flash drives are not wearing out to the degree once feared. Flash drive

manufacturers have improved endurance and reliability through error correction

code algorithms, wear leveling and other technologies. In addition, SSDs do not wear out without

warning. They typically alert users in the same way a sensor might indicate an underinflated tire.

1.7.4 NAND Flash Memory

NAND flash semiconductor manufacturers have developed different types of memory

suitable for a wide range of data storage uses cases. The following are the various types of NAND

flash memory:

Single-level cell (SLC). Stores one bit per cell and two levels of charge and has higher

performance, endurance and reliability than other types of NAND flash but is more expensive than

other types of NAND flash. It is primarily used in enterprise storage and mission-critical


Multilevel cell (MLC). Can store multiple bits per cell and multiple levels of charge. The

term MLC equates to two bits per cell. Cheaper than SLC and enterprise MLC (eMLC), and also

has a high density but lower endurance than SLC and eMLC and is slower than SLC. Commonly

used in consumer devices and enterprise storage.

Enterprise MLC (eMLC). Typically stores two bits per cell and multiple levels of charge; uses

special algorithms to extend write endurance. Less expensive than SLC flash and has greater

endurance than MLC flash. The disadvantage of eMLC is that it is more expensive than MLC but

slower than SLC. It used in enterprise applications with high write workloads.

Triple-level cell (TLC). Stores three bits per cell and multiple levels of charge. Also referred to

as MLC-3, X3 or 3-bit MLC. Lower cost and higher density than MLC and SLC but lower

performance and endurance than MLC and SLC. It used in mass storage consumer applications,
such as USB drives, flash memory cards, smartphones, and client SSDs and datacenter SSDs for

read-intensive workloads.

Vertical/3D NAND. Stacks memory cells on top of each other in three dimensions vs. traditional

planar NAND technology. Has higher density, higher write performance and lower cost per bit vs.

planar NAND but has higher manufacturing cost than planar NAND and is difficult to manufacture

using production planar NAND process. It also has lower data retention. Used in consumer and

enterprise storage.

Note: NAND flash wear-out is less of a problem in SLC flash than it is in less expensive types of

flash, such as MLC and TLC, for which the manufacturers may set multiple threshold values for a

charge. The commonly cited industry wear-out figures are 100,000 program/erase (write/erase)

cycles for SLC NAND flash, 30,000 for eMLC, 10,000 or fewer for MLC, and 3,000 or fewer for

TLC. Actual endurance figures may be higher.

1.7.5 NOR Flash Memory

The two main types of NOR flash memory are parallel and serial (also known as serial

peripheral interface). NOR flash originally was available only with a parallel interface. Parallel

NOR offers high performance, security and additional features; its primary uses include industrial,

automotive, networking, and telecom systems and equipment. Serial NOR flash has lower pin

counts and smaller packaging and is less expensive than parallel NOR. Use cases for serial NOR

include personal and ultra-thin computers, servers, HDDs, printers, digital cameras, modems and

routers [8].
1.7.6 Register Transfer Level (RTL)

In digital circuit design, register-transfer level (RTL) is a design abstraction which models

a synchronous digital circuit in terms of the flow of digital signals (data) between hardware

registers, and the logical operations performed on those signals. A synchronous circuit consists of

two kinds of elements: registers and combinational logic. Registers (usually implemented as

D flip-flops) synchronize the circuit's operation to the edges of the clock signal, and are the only

elements in the circuit that have memory properties. Combinational logic performs all the logical

functions in the circuit and it typically consists of logic gates. When designing digital integrated

circuits with a hardware description language, the designs are usually engineered at a higher level

of abstraction than transistor level (logic families) or logic gate level. In HDLs the designer

declares the registers (which roughly correspond to variables in computer programming

languages), and describes the combinational logic by using constructs that are familiar from

programming languages such as if-then-else and arithmetic operations. This level is called register-

transfer level. The term refers to the fact that RTL focuses on describing the flow of signals

between registers [9]. Using an EDA tool for synthesis, this description can usually be directly

translated to an equivalent hardware implementation file for an ASIC or an FPGA.

The synthesis tool also performs logic optimization. At the register-transfer level, some types of

circuits can be recognized. If there is a cyclic path of logic from a register's output to its input (or

from a set of registers outputs to its inputs), the circuit is called a state machine or can be said to

be sequential logic. If there are logic paths from a register to another without a cycle, it is called

a pipeline.
RTL is used in the logic design phase of the integrated circuit design cycle. An RTL

description is usually converted to a gate-level description of the circuit by a logic synthesis tool,

for example Design Compiler by Synopsys. The synthesis results are then used

by placement and routing tools to create a physical layout [9].

1.7.7 Application Specific Integrated Circuit (ASIC)

An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized

for a particular use, rather than intended for general-purpose use. Application-specific standard

products (ASSPs) are intermediate between ASICs and industry standard integrated circuits like

the 7400 or the 4000 series. As feature sizes have shrunk and design tools improved over the years,

the maximum complexity (and hence functionality) possible in an ASIC has grown from

5,000 gates to over 100 million. Modern ASICs often include

entire microprocessors, memory blocks including ROM, RAM, EEPROM, flash memory and

other large building blocks. Such an ASIC is often termed a SoC (system-on-chip). Designers of

digital ASICs often use a hardware description language (HDL), such as Verilog or VHDL, to

describe the functionality of ASICs [10].

1.7.8 ST M2540

The M25P40 is a 4Mbit (512k x8) Serial Flash memory with advanced write protection

mechanisms, accessed by high speed SPI-compatible bus. The memory can be programmed 1 to

256 bytes at a time, using the Page Program Instruction.

The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes

wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes. The

whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the

Sector Erase instruction. Figure 1.7 shows the memory schematic and Table 1.1 explains the pin


Figure 1.7. M25P40 Table 1.1. Memory Pin Description



This chapter includes the related studies and topics wherein the researcher came up in

realization of the flash memory. Referring to the previous studies on flash memory published and

patented and books on Microelectronics are of enormous help.

2.1 Microcontrollers

The key element of each mote is its microcontroller. Therefore, it is necessary to select the

most suitable one. Table 1 shows a list of state-of-the-art microcontrollers which are typically used

for wireless sensor network hardware. It can be seen that the ARM9 microcontroller has a very

high processing power and a lot of peripherals but also the highest power consumption. It is very

difficult to integrate such a microcontroller in a power-aware application. However, an ARM9

core microcontroller is used for the JavaTM Sun SPOT. Java needs the processing power to adapt

the software to a wide range of application areas.

Table 3.1: Comparison of microcontrollers. (Wake-up time from stand-by mode after an interrupt)

The MSP430 microcontroller has a better performance and lower power consumption than

the Atmega128L microcontroller. Only the on-board flash memory is smaller. The Atmega128L

microcontroller is used for the Mica2 and MicaZ motes from Crossbow Technology. The

MSP430F1611 is integrated in the TelosB mote. In a WSN platform for monitoring coral reefs is

introduced. They use an MSP430 microcontroller, too. The hardware is placed into a watertight

housing and it is placed at the ocean surface level to allow communication. They also mentioned

a low power hardware design using P-channel MOSFETs to power down the sensors during sleep

state [12].

2.1.2 The Microcontroller for sensor nodes

The chip footprint used in microcontroller contains complicated structure. It uses lower

powered or lower energy microcontrollers. The microcontroller is generally used in many types of

embedded systems. These sensor nodes have its flexibility to connect to other devices. These

devices have low cost, ease of programming, and low power or low energy consumption. The

general purpose of microprocessor generally has higher power consumption than a previously used

microcontroller. Therefore, it is not considered a suitable choice for a sensor node in wireless

sensor networks environment [13].

2.1.3 MSP430 Architecture

This section begins to show the available CPUs and peripheral devices at the beginning in

an overview before it is handled in the various chapters in detail. It provides a comprehensive

description of the MSP430 architecture, covering its main characteristics: (1) address space

(describing the interrupt vector table, flash/ROM, information and boot memories for flash devices

RAM peripheral modules and special function registers); (2) the orthogonal (and simply

programmable) RlSC structure of RISC 16-bit Central Processing Unit (CPU) compared to the

CISC-extensions of the (CISC) 16-bit MSP430X CPU. As a general rule, the CPUX architecture

is present in devices that have greater than 64kB flash memory size, clarifying on where devices

the CPUX is present; (3) the seven addressing modes (Register; Indexed; Symbolic; Absolute;

Indirect register; Indirect auto increment; Immediate) either supported for the source operand and

for the destination operand, presenting as example the number of CPU clock cycles required for

an instruction, depending on the instruction format and the addressing modes used; and the (4)

instruction set composed of 27 base op-codes and 24 emulated instructions. These topics are

exposed gathering the information presented by [14].

2.2.1 Direct Memory Access (DMA)

The MSP430 is well suited to low-power applications, and the Direct Memory Address

(DMA) controller is a very useful facility to have in order to achieve this. This module is supported

by some devices in the MSP430 family providing the capability to move data from one location to

another, without CPU intervention. This increases the throughput of peripheral modules and also
allows the CPU to remain in a low-power mode, without needing to wake up to perform the data

transfer. This gives the benefit of reduced power consumption. Data transfers to/from peripherals

can be initiated by external and internal events, using triggers [15].

2.2.2 Write Improvement Strategies for Serial NOR Dataflash Memory

This work presents a low energy write optimization strategy called masked overwriting to

increase serial NOR Dataflash lifetime, decrease energy consumption per operation and reduce

average time per write operation. The result of this work supports the ability to do in-place append

operations or bit manipulations for serial NOR Dataflash and provides an analysis of device

performance based on write patterns.

This strategy reduces the complexity of data management as well as reducing energy costs

and extending serial NOR Dataflash field life through lower write cost and a lower ratio of erase

to writes on device. Use cases are presented, demonstrating the significant advantages of this

strategy [16].

2.2.3 Flash Programming

To use the MSP430 in a stand-alone embedded application, the application code needs to

be stored in the flash memory. The MSP430 flash memory module is bit-, byte-, and word

addressable and programmable, using a controller that supervises the programming and erase

operations. The controller has three (or four) registers, a timing generator, and a voltage generator

to supply program and erase voltages. Two different methods of writing to the flash memory are

studied. The first method requires the CPU execution of the code resident in flash memory, so
whenever a flash write or erase operation occurs, the CPU access to this memory is automatically

inhibited. The operation of this device is monitored using a digital output port [17].

2.2.4 Mapping Structures for Flash Memories: Techniques and Open Problems

Flash memory is a type of electrically erasable programmable read-only memory

(EEPROM). Because flash memories are nonvolatile and relatively dense, they are now used to

store files and other persistent objects in handheld computers, mobile phones, digital cameras,

portable music players, and many other computer systems in which magnetic disks are

inappropriate. Flash, like earlier EEPROM devices, suffers from two limitations. First, bits can

only be cleared by erasing a large block of memory. Second, each block can only sustain a limited

number of erasures, after which it can no longer reliably store data. Due to these limitations,

sophisticated data structures and algorithms are required to effectively use flash memories. These

algorithms and data structures support efficient not-in-place updates of data, reduce the number of

erasures, and level the wear of the blocks in the device.

In this paper, their aim was to survey flash-management techniques in order to provide

both practitioners and researchers with a broad overview of existing techniques. Due to lack of

space in this abstract, they are not able to describe in detail every technique; the full paper presents

such descriptions. They hope that their paper will encourage researchers to analyze these

techniques, both theoretically and experimentally. In particular, they hope that the clear description

of open theoretical problems in Section 4 of this paper will lead to theoretical research in this area.

They also hope that this paper will facilitate the development of new and improved flash-

management techniques [18].



A WSN typically consists of a high number of sensor nodes, also called motes, and of one

or few gateway nodes. The gateway node is connected with a computer to access the data of the

WSN. Each mote collects information about its environment using the attached sensors. This

information is forwarded to gateway nodes in a multi-hop manner as shown in Figure 1. Usually,

it is necessary to preprocess the measured data before it can be transmitted.

Figure 3.1. Typical structure of a wireless sensor network

In this work, they demonstrated the adaptability of a mote to a specific application area

using an MSP430 microcontroller. It showed low power design techniques. It also demonstrates

the possibility to supply the mote continuously using ultra capacitors as energy storage


2.3.2 Brazilian Energy-Efficient Architectural Node

Wireless sensor networks present fascinating challenges for the application of distributed

signal processing and distributed control. These systems challenge the applications of appropriate

techniques to construct cheap processing units with sensing nodes considering energy constraints.

In this study, they have designed a computer platform, called BEAN, that includes software

and hardware components, which is a wireless sensor node prototype. It allows to test and

demonstrate energy efficient networking algorithms to be developed in the Sensornet project. This

embedded system is capable of performing all tasks of a wireless sensor node with energy,

memory, and processing power restrictions. In our knowledge, BEAN is the first sensor node that

allow measuring the power consumption of each component and it is the first sensor node

prototype designed in Brazil. In this WSN they used ST M25P40, a serial flash memory that is fast

and can be switched to a low power mode when it is not used.

The M25P40 is a 4 Mbit (512K x 8) Serial Flash Memory, with write protection

mechanisms, accessed by a high speed SPI-compatible bus. The memory can programm 1 to 256

bytes at a time, using the Page Program instruction. The memory is organized as 8 sectors, each

containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as

consisting of 2048 pages, or 524,288 bytes. The whole memory can be erased using the Bulk Erase

instruction, or a sector at a time, using the Sector Erase instruction [20].

2.3.3 The ScatterWeb MSB-A2 Platform for Wireless Sensor Networks

Scatterweb is a platform for self-configuring wireless sensor networks. Research of wireless

sensor networks is often focused on algorithms and simulations. While these aspects abstract from

the properties, deficiencies, and specifications of real hardware platforms. Energy efficiency is a

factor that is always the prime concern of these networks as the devices have limited power
resources. They therefore introduce the MSB-A2 sensor node as the newest member of the

ScatterWeb research family. Although the data specification of the hardware lets assume a shorter

lifetime,, the MSB-A2 could be as efficient as former platform.

In this paper they presented the new scatterweb MSB-A2 hardware platform for wireless

sensor networks which they believe will enable access to a broad range of computation intense

real-life application, while still being reasonably energy efficient [21].

Table 3.2. Key features of the modular sensor board MSB-A2

Chapter 3

This chapter will discuss the design and the methods for the implementation of the study.
This chapter includes the procedures and methods to come up with a solution to address the
objectives of this study. The review of related literature has been a great help for coming up with
a solution.
3.1 Flow chart


RTL Description

RTL verification

RTL functionality


Use Design Compiler
for Logic Synthesis

no Layout function &

Timing verified?
no Netlist Logic and
Timing verified?

yes Physical Post Layout

Implementation Timing Verification
using ICC using Primetime
The flowchart shows the process of verification and optimization of the flash memory IP

using Synopsys tools, Verilog Compiler Simulator (VCS), Design Compiler (DC), IC Compiler

(ICC) and PrimeTime.

3.1.1 Synopsys Verilog Compiler Simulator (VCS)

Synopsys Verilog Compiler Simulator is a tool from Synopsys specifically designed to

simulate and debug designs. This tutorial basically describes how to use VCS, simulate a verilog

description of a design and learn to debug the design. VCS also uses VirSim, which is a graphical

user interface to VCS used for debugging and viewing the waveforms. There are three main steps

in debugging the design, which are as follows:

1. Compiling the Verilog/VHDL source code.

2. Running the Simulation.

3. Viewing and debugging the generated waveforms.

3.1.2 Design Compiler

The Design Compiler is a synthesis tool from Synopsys. The synthesis tool takes an RTL

hardware description (design written in either Verilog/VHDL) and standard cell library as input

and the resulting output would be a technology dependent gate-level netlist. The gate-level netlist

is nothing but structural representation on only standard cells based on the cells in the standard

cell library. The synthesis tool internally performs many steps which is listed below and is shown

in the Figure 3.2.

Figure 3.2. Synthesis Flow

1.) The Design Compiler reads in technology libraries, DesignWare libraries and symbol

libraries to implement synthesis.

During the synthesis process, Design Compiler [DC] translates the RTL description to

components extracted from the technology library and DesignWare library. The technology

library consists of basic logic gates and flip-flops. The DesignWare library contains more

complex cells for example adders and comparators which can be used for arithmetic building

blocks. DC can automatically determine when to use Design Ware components and it can then

efficiently synthesize these components into gate-level implementations.

2.) Reads the RTL hardware description written in Verilog/VHDL.

3.) The synthesis tool now performs many steps including high-level RTL optimization, RTL
to unoptimized Boolean logic, technology independent optimizations, and finally

technology mapping to the available standard cells in the technology library, known as

target library. This resulting gate-level-netlist also depends on constrains given.

Constraints are the designers specification of timing and environmental restrictions (area,

power, process etc) under which synthesis is to be performed.

3.1.3 IC Compiler

The physical design stage of the ASIC design flow is also known as the place and route

stage. This is based upon the idea of physically placing the circuits, which form logic gates and

represent a particular design, in such a way that the circuits can be fabricated. This is a generic,

high level description of the physical design (place/route) stage. Within the physical design stage,

a complete flow is implemented as well. This flow will be described more specifically, and as

stated before, several EDA companies provide software or CAD tools for this flow. Synopsys

software for the physical design process is called IC Compiler. The overall goal of this

tool/software is to combine the inputs of a gate-level netlist, standard cell library, along with timing

constraints to create and placed and routed layout. This layout can then be fabricated, tested, and

implemented into the overall system that the chip was designed for.

The first of the main inputs into the ICC are:

1. Gate-level Netlist. Which can be in the form of Verilog or VHDL. This netlist is produced

during logical synthesis which takes place prior to the physical design stage.

2. Standard Cell Library. This is a collection of logic functions such as OR, AND, XOR,

etc. The representation in the library is that of the physical shapes that will be fabricated.

This layout view or depiction of the logical function contains the drawn mask layers

required to fabricate the design properly.

3. Design Constraints. These constraints are identical to those which were used during the

front-end logic synthesis prior to physical design. These constraints are derived from the

system specifications and implementation of the design being created. Common constraints

among most designs include clock speeds for each clock in the design as well as any input

or output delays associated with the input/output signals of the chip. These same constraints
using during logic synthesis are used by ICC so that timing will be considered during each

stage of place and route. The constraints are specific for the given system specification of

the design being implemented [8].

3.2 ASIC Flow

As deep sub-micron semiconductor geometries shrink, traditional methods of chip design

have become increasingly difficult. In addition, an increasing number of transistors are being

packed into the same die-size, making validation of the design extremely hard, if not impossible.

Furthermore, under critical time-to-market pressure the chip design cycle has remained the

same, or is constantly being reduced. To counteract these problems, new methods and tools have

evolved to facilitate the ASIC design methodology.

Figure 3.3. Tradition ASIC flow

The traditional ASIC flow design is outlined with the following steps:

Architectural and Electrical specifications

RTL coding in HDL (Verilog/VHDL)

DFT memory BIST insertion, for designs containing memory elements.

Exhaustive dynamic simulation of the design, in order to verify the functionality of the


Design environment setting. This includes the technology library to be used, along with

the other environmental attributes.

Constraining and synthesizing the design using scan insertion.

Block level static timing analysis, using Design Compliers built in static timing analysis


Formal verification of the design RTL compared against synthesized netlist, using


Pre-layout static timing analysis on the full design through Primetime.

Forward annotation of timing constraints to the layout tool.

Initial Floorplanning with timing driven placement of cells, clock tree, insertion and globa


Transfer of clock tree to the original design (netlist) residing in the Desgin Compiler.

In-place optimization of the Design Compiler.

Formal verification between the synthesized netlist and clock tree inserted netlist, using


Extraction of estimated timing delays from the layout after the global routing step.

Back annotation of estimated timing data from the global routed design using Primtime.
Static timing analysis using Primtime, using the estimated delays extracted after

performing global route.

Detailed routing of the design.

Extraction of real timing delays from the detailed routed design.

Back annotation of the real extracted timing data to PrimeTime.

Post-layout static timing analysis using PrimeTime.

Functional gate-level simulation of the design with post-layout timing (if desired)

Tape out after LVS and DRC verification.

Once the chip (silicon) is back from fab, it needs to be put in a real environment and tested

before it can be released into Market. Since the simulation speed (number of clocks per second)

with RTL is very slow, there is always the possibility to find a bug in Post silicon validation[7].

3.3 Power Compiler

The Power Compiler automatically minimizes power consumption at the RTL and gate

level, and enables concurrent timing, area, power and test optimizations within the Design

Compiler synthesis solution. It performs advanced clock gating and low power placement to

reduce dynamic power consumption, and performs leakage optimization to reduce standby power.

Power Compiler along with Design Compiler Graphical utilizes concurrent multi-corner multi-

mode (MCMM) optimization to reduce iterations and provide faster time-to-results. With power

intent defined by the standardized IEEE 1801 Unified Power Format (UPF), designers can use

Power Compiler to implement advanced low power techniques such as multi-voltage, power

gating, and state retention.

Figure 3.4.Complete, comprehensive power synthesis within
Design Compiler

Power Compiler enables complete and comprehensive power-aware synthesis within

Design Compiler. By applying Power Compilers power reduction techniques during synthesis,

designers can perform concurrent timing, area, power and test optimization. The key features of

Synopsys Power Compiler are: advanced clock gating and low power placement for lower

dynamic power, leakage power optimization for lower standby power, concurrent multi-corner

multi-mode based optimization for faster time-to-results and automated implementation of UPF-

driven advanced low power techniques [11]. This process can be used in the low power

implementation of flash memory IP to be used as an external memory for the WSN application

using an openMSP430 application.





[4] Gautam, Kamlesh and Gautam, Narendra. (2014) . Memory Required for Wireless Sensor

Nodes on the Basis of Characteristics and Behaviour when using TinyOs. International Journal

of Emerging Technology and Advanced Engineering, 4(1), 2250-2459.


[6] Volpe, Leonardo Steinfield.(2013) Energy-eficient memories for wireless

sensor networks. retrieved from:

[7] Bhatnagar, Himanshu. (2002). Advance ASIC Chip Synthesis Using Synopsys Design

Compiler Physical Compiler and PrimeTime. NY: Kluwer Academic Publishers.

[8] Kommuru, Hima Bindu and Mahmoodi, Hamid. (2009). ASIC Design Flow Tutorial Using

Synopsys tools. San Francisco State University.