SERVICE MANUAL
CD MECHANISM BASIC CD MECHANISM : 3ZG-2 E2
TYPE
CS3DM
CS3NDM
YCS3NDM
This Service Manual is the "Revision Publishing" and replaces "Simple Manual"
(S/M Code No. 09-99A-336-9T2).
SI ON
VI
RE
TA
DA
2
ELECTRICAL MAIN PARTS LIST
REF. NO PART NO. KANRI DESCRIPTION REF. NO PART NO. KANRI DESCRIPTION
NO. NO.
IC C128 87-010-313-080 CAP, CHIP 18P
C130 87-A10-893-040 CAP,E 220-10 M PW
87-A20-547-010 C-IC,CXA1992AR C131 87-010-264-040 CAP,E 100-10 5L
87-A20-919-040 C-IC,BA5915FP C132 87-010-178-080 CHIP CAP 1000P
87-A20-917-010 C-IC,CXD2540Q-1/2 C133 87-010-264-040 CAP,E 100-10 5L
8A-ZG2-613-010 C-IC,M30622M8-762FP
87-017-825-010 IC,GP1F32T C134 87-010-196-080 CHIP CAPACITOR,0.1-25
C135 87-010-196-080 CHIP CAPACITOR,0.1-25
87-017-760-080 IC,M51943BML C136 87-010-196-080 CHIP CAPACITOR,0.1-25
87-A20-602-040 C-IC,M5291FP C137 87-010-196-080 CHIP CAPACITOR,0.1-25
87-A20-905-040 C-IC,BA033FP C138 87-010-197-080 CAP, CHIP 0.01 DM
87-A20-925-040 C-IC,BA05FP
87-A21-307-010 C-IC,CL8820-P160 C139 87-010-197-080 CAP, CHIP 0.01 DM
C140 87-016-251-040 CAP,E 220-16 SMG
8A-ZG2-615-040 C-IC,MSM534031E-20GS-K(R1) C141 87-010-196-080 CHIP CAPACITOR,0.1-25
87-A20-921-040 C-IC,SN74LVU04APW C142 87-010-196-080 CHIP CAPACITOR,0.1-25
87-A21-547-040 C-IC,AS4LC256K16EO-35TC C143 87-010-213-080 C-CAP,S 0.015-50 B
87-A21-309-040 C-IC,HD74LV74A
87-A20-918-040 C-IC,SM5878AM C144 87-010-805-080 CAP, S 1-16
C145 87-010-805-080 CAP, S 1-16
87-001-982-010 IC,TA7291S C146 87-010-805-080 CAP, S 1-16
87-A21-305-010 C-IC,BU1427K C148 87-016-251-040 CAP,E 220-16 SMG
87-A21-311-040 C-IC,LC74772V-9015-TLM C149 87-010-197-080 CAP, CHIP 0.01 DM
4
REF. NO PART NO. KANRI DESCRIPTION REF. NO PART NO. KANRI DESCRIPTION REF. NO PART NO. KANRI DESCRIPTION
NO. NO. NO.
C401 87-010-403-040 CAP,E 3.3-50 SME C707 87-010-196-080 CHIP CAPACITOR,0.1-25 VIDEO SW C.B
C402 87-010-403-040 CAP,E 3.3-50 SME C708 87-010-197-080 CAP, CHIP 0.01 DM
C501 87-016-350-040 CAP,E 470-4 MA GAS C709 87-010-196-080 CHIP CAPACITOR,0.1-25 CON801 87-A60-109-010 CONN,2P V S2M-2W
C502 87-010-805-080 CAP, S 1-16 C710 87-010-196-080 CHIP CAPACITOR,0.1-25 SW801 87-A91-573-010 SW,SL 1-1-3 SSSU L9
C503 87-010-078-040 CAP,E 47-6.3 5L C711 87-010-178-080 CHIP CAP 1000P
C514 87-010-805-080 CAP, S 1-16 CN6 87-A60-160-010 CONN,12P H FE Chip Resistor Part Coding
C515 87-010-805-080 CAP, S 1-16 CN101 87-A60-424-010 CONN,16P V TOC-B
C516 87-010-178-080 CHIP CAP 1000P CN102 87-009-034-010 CONN,6P PH V 8 8
C517 87-010-805-080 CAP, S 1-16 CN301 87-A60-154-010 CONN,6P H FE
C518 87-010-805-080 CAP, S 1-16 FC1 86-ZG1-605-010 CABLE,FFC 16P
A
C519 87-010-805-080 CAP, S 1-16 FC2 86-ZG1-667-010 F-CABLE,8P 1.25 175MM BLACK Figure
C520 87-012-140-080 CAP 470P FC3 86-ZG1-609-010 CONN ASSY,6P
C521 87-010-805-080 CAP, S 1-16 J701 87-A60-414-010 JACK,PIN 1P YLW YKC21-3527 Resistor Code
C522 87-010-197-080 CAP, CHIP 0.01 DM L101 87-005-432-080 COIL,10UH Value of resistor
C523 87-010-318-080 C-CAP,S 47P-50 CH L102 87-005-432-080 COIL,10UH
C524 87-012-140-080 CAP 470P L151 87-005-440-080 COIL,47UH FLR50 Chip resistor
C525 87-012-140-080 CAP 470P L302 87-A50-517-080 COIL,10UHK FLR88 Dimensions (mm) :A
C551 87-016-350-040 CAP,E 470-4 MA GAS L303 87-A50-586-010 COIL,68UH RCR110D Wattage Type Tolerance Symbol Form L W t Resistor Code : A
C552 87-010-197-080 CAP, CHIP 0.01 DM L501 87-A50-518-080 COIL,68UHK FLR88
C555 87-010-805-080 CAP, S 1-16 L551 87-005-428-080 COIL 4.7UH K FLR50 1/16W 1005 5% CJ 1.0 0.5 0.35 104
L
C559 87-010-805-080 CAP, S 1-16 L701 87-005-440-080 COIL,47UH FLR50 1/16W 1608 5% CJ t 1.6 0.8 0.45 108
C560 87-010-805-080 CAP, S 1-16 L702 87-A50-518-080 COIL,68UHK FLR88 1/10W 2125 5% CJ 2 1.25 0.45 118
W
C561 87-010-805-080 CAP, S 1-16 L721 87-005-802-080 C-COIL, 1.8UH FLC32
C562 87-010-805-080 CAP, S 1-16 M601 87-045-305-010 MOTOR, RF-500TB DC-5V (2MA) 1/8W 3216 5% CJ 3.2 1.6 0.55 128
C563 87-010-805-080 CAP, S 1-16 R130 87-022-364-080 C-RES,S 82K-1/10W F
C584 87-010-154-080 CAP CHIP 10P X581 87-A70-125-080 VIB,XTAL 27MHZ 50PPM
C585 87-010-154-080 CAP CHIP 10P
C588 87-010-805-080 CAP, S 1-16
C601 87-010-805-080 CAP, S 1-16 LED C.B<CS3DM>
C602 87-010-112-040 CAP,E 100-16
LED701 87-017-733-080 LED,SEL1250SM<CS3DM>
C603 87-010-805-080 CAP, S 1-16 LED702 87-017-350-080 LED,SEL1550CM<CS3DM>
C604 87-010-196-080 CHIP CAPACITOR,0.1-25 LED703 87-017-733-080 LED,SEL1250SM<CS3DM>
C605 87-010-196-080 CHIP CAPACITOR,0.1-25
C608 87-010-178-080 CHIP CAP 1000P
C610 87-010-197-080 CAP, CHIP 0.01 DM T-T C.B
5 6
SCHEMATIC DIAGRAM-1 (VCD 1/2)
MODEL
11 12
SCHEMATIC DIAGRAM-2 (VCD 2/2)
13 14
IC BLOCK DIAGRAM
IC, BA5915FP
6.65K 6.65K
6.65K 6.65K
CH1
MUTE
IC, M5291FP
IC, TA7291S
STOP
BRAKE
: HI IMPEDANCE
NOTE : INPUT “H” ACTIVE
PROTECTOR
CIRCUIT
(TSD)
17
IC DESCRIPTION
IC, CXA1992AR
Pin No. Pin Name I/O Description
Output terminal for focus error amplifier. Internally connected to window comparator
1 FEO O
input for bias condition.
2 FEI I Input terminal for focus error.
3 FDFCT I Capacitor connection terminal for time constant used when there is defect.
This pin is connected to GND via capacitor when high frequency gain of the focus
4 FGD I
servo is attenuated.
This is a pin where the time constant is externally connected to raise the low frequency
5 FLB I
gain of the focus servo.
6 FE_O O Focus drive output.
7 FEM I Focus amplifier inverted input pin.
This is a pin where the time constant is externally connected to generate the focus
8 SRCH I
search waveform.
This is a pin where the selection time constant is externally connected to set the
9 TGU I
tracking servo the high frequency gain.
This is a pin where the selection time constant is externally connected to set the
10 TG2 I
tracking high frequency gain.
11 FSET I Pin for setting peak of the phase compensator of the focus tracking.
12 TA_M I Tracking amplifier inverted input pin.
13 TA_O O Tracking drive output.
14 SL_P I Sled amplifier non-inverted input pin.
15 SL_M I Sled amplifier inverted input pin.
16 SL_O O Sled drive output.
The current which determines height of the focus search, track jump and sled kick is
17 ISET I
input with external resistance connected.
18 Vcc I Power supply.
19 LOCK I “L” setting starts sled disorder-prevention circuit. (Not pull-up resistance)
20 CLK I Clock input for serial data transfer from CPU. (No pull-up resistance)
21 XLT I Latch input from CPU. (No pull-up resistance)
22 DATA I Serial data input from CPU. (No pull-up resistance)
23 XRST I Reset system at “L” setting. (No pull-up resistance)
24 C_OUT O Signal output for track number counting.
FZC, DFCT1, TZC, BALH, TGH, FOH, or ATSC is output depending on the
25 SENS1 O
command from CPU.
26 SENS2 O DFCT2, MIRR, BALL, TGL or FOL is output depending on the command from CPU.
27 FOK O Output terminal for focus OK comparator.
28 CC2 I Input pin where the DEFECT bottom hold output is capacitance coupled.
DEFECT bottom-hold output terminal. Internally connected to interruption comparator
29 CC1 O
input.
30 CB I Connection terminal for DEFECT bottom-hold capacitor.
Connection terminal for MIRR hold-capacitor.
31 CP I
Anti-reverse input terminal for MIRR comparator.
18
Pin No. Pin Name I/O Description
32 RF_I I Input terminal by capacity combination of RF summing amplifier.
33 RF_O O Output terminal of RF summing amplifier. Checkpoint of Eye pattern.
Anti-reverse input terminal for RF summing amplifier.
34 RF_M I The gain of RF amplifier is decided by the connection resistance between RF_M and
RFO terminals.
This is a pin where the selection time constant is externally connected to control the
35 RFTC I
RF level.
36 LD O APC amplifier output terminal.
37 PD I APC amplifier input terminal.
RFI-V amplifier inverted input pin.
38, 39 PD1, PD2 I These pins are connected to the A+C and B+C pins of the optical pickup, receiving by
currents input.
40 FEBIAS I/O Bias adjustment pin of the focus error amplifier.
F and EIV amplifier inverted input pins.
41, 42 F, E I These pins are connected to the F and E of the optical pickup, receiving by current
input.
Gain adjustment pin of the I-V amplifier E. (When not in use of BAL automatic
43 EI —
adjustment)
44 VEE — GND connection pin.
45 TEO O Output terminal for tacking-error amplifier. Output E-F signal.
46 LPFI I BAL adjustment comparator input pin. (Input through LPF from TEO)
47 TEI I Input terminal for tracking error.
48 ATSC I Window-comparator input terminal for detecting ATSC.
49 TZC I Input terminal for tracking-zero cross comparator.
50 TDFCT I Capacitor connection pin for the time constant used when there is defect.
51 VC O Output terminal for DC voltage reduced to half of VCC+VEE.
52 FZC I Input terminal for focus-zero cross comparator.
19
IC, CXD2540Q
Pin No. Pin Name I/O Description
1 FOK I Focus OK input. Used for SENS output and the servo auto sequencer.
2 FSW O Spindle motor output filter switching output.
3 MON O Spindle motor on/off control output.
4 MDP O
Spindle motor servo control.
5 MDS O
High, when sampled value of GFS at 460Hz is high.
6 LOCK O
Low, when sampled value of GFS at 460Hz is low by 8 times successively.
7 NC — Not used.
8 VCOO O Analog EFM PLL oscillation circuit output.
9 VCOI I Analog EFM PLL oscillation circuit input. fLOCK=8.6436MHz.
10 TEST I TEST pin.
11 PDO O Analog EFM PLL charge pump output.
12 VSS — GND.
13 PWMI I Spindle motor external control input.
14 V16M O VCO2 oscillation output for the wide-band EFM PLL.
15 VCTL I VCO2 control voltage input for the wide-band EFM PLL.
16 VPCO O Wide-band EFM PLL charge pump output.
17 VCKI I VCO2 oscillation input for the wide-band EFM PLL.
18 FILO O Multiplier PLL (slave=digital PLL) filter output.
19 FILI I Multiplier PLL filter input.
20 PCO O Multiplier PLL charge pump output.
21 AVSS — Analog GND.
22 CLTV I Multiplier VCO1 control voltage input.
23 AVDD — Analog power supply (5V).
24 RF I EFM signal input.
25 BIAS I Constant current input of the asymmetry circuit.
26 ASYI I Asymmetry comparator voltage input.
27 ASYO O EFM full-swing output.
28 ASYE I Low: asymmetry circuit off; high: asymmetry circuit on.
29 NC — Not used.
30 PSSL I Audio data output mode switching input. Low: serial output; high: parallel output.
31 WDCK O D/A interface for 48-bit slot. Word clock f=2Fs.
32 LRCK O D/A interface for 48-bit slot. LR clock f=Fs.
33 VDD — Power supply (5V).
DA16 (MSB) output when PSSL=1.
34 DA16 O
48-bit slot serial data (two’s complement, MSB first) when PSSL=0.
35 DA15 O DA15 output when PSSL=1. 48-bit slot bit clock when PSSL=0.
DA14 output when PSSL=1.
36 DA14 O
64-bit slot serial data (two’s complement, LSB first) when PSSL=0.
37 DA13 O DA13 output when PSSL=1. 64-bit slot bit clock when PSSL=0.
38 DA12 O DA12 output when PSSL=1. 64-bit slot LR clock when PSSL=0.
20
Pin No. Pin Name I/O Description
39 DA11 O DA11 output when PSSL=1. GTOP output when PSSL=0.
40 DA10 O DA10 output when PSSL=1. XUGF output when PSSL=0.
41 DA09 O DA09 output when PSSL=1. XPLCK output when PSSL=0.
42 DA08 O DA08 output when PSSL=1. GFS output when PSSL=0.
43 DA07 O DA07 output when PSSL=1. RFCK output when PSSL=0.
44 DA06 O DA06 output when PSSL=1. C2PO output when PSSL=0.
45 DA05 O DA05 output when PSSL=1. XRAOF output when PSSL=0.
46 DA04 O DA04 output when PSSL=1. MNT3 output when PSSL=0.
47 DA03 O DA03 output when PSSL=1. MNT2 output when PSSL=0.
48 DA02 O DA02 output when PSSL=1. MNT1 output when PSSL=0.
49 DA01 O DA01 output when PSSL=1. MNT0 output when PSSL=0.
Aperture compensation control output.
50 APTR O
This pin outputs a high signal when the right channel is used.
Aperture compensation control output.
51 APTL O
This pin outputs a high signal when the left channel is used.
52 VSS — GND.
53 XTAI I Crystal oscillation circuit input.
54 XTAO O Crystal oscillation circuit output.
55 XTSL I Crystal selector input.
56 FSTT O 2/3 frequency divider output for Pins 53 and 54.
57 FSOF O 1/4 frequency divider output for Pins 53 and 54.
58 C16M O 16.9344MHz output. (V16M output in CLV-W and CAV-W modes)
59 MD2 I Digital-out on/off control. High: on; low: off
60 DOUT O Digital-out output.
Outputs a high signal when the playback disc has emphasis, and a low signal when
61 EMPH O
there is no emphasis.
62 WFCK I WFCK (write frame clock) output.
63 SCOR O Outputs a high signal when either subcode sync S0 or S1 is detected.
64 SBSO O Sub P to W serial output.
65 EXCK I SBSO readout clock input.
66 SQSO O Sub Q 80-bit and PCM peak, level metter and internal status outputs.
67 SQCK I SQSO readout clock input.
68 MUTE I High: mute; low: release
69 SENS — SENS output to CPU.
70 XRST I System reset. Reset when low.
71 DATA O Serial data input from CPU.
72 XLAT O Latch input from CPU. Serial data is latched at the falling edge.
73 VDD Power supply (5V).
74 CLOK O Serial data transfer clock input from CPU.
75 SEIN I SENS input from SSP.
76 CNIN I Track jump count signal input.
21
Pin No. Pin Name I/O Description
77 DATO O Serial data output to SSP.
78 XLTO O Serial data latch output to SSP. Latched at the falling edge.
79 CLKO O Serial data transfer clock output to SSP.
Mirror signal input. Used when the number of tracks is 128 or more for the 2N-track
80 MIRR I
jump and M track move of the auto sequencer.
Notes)
• The 64-bit slot is an LSB first, two’s complement output, and the 48-bit slot is an MSB first, two’s complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
• XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point
coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µ.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
22
IC, M30622M8-762FP
Pin No. Pin Name I/O Description
1 DATA O DSP/SSP DATA.
2 CLOCK O DSP/SSP CLOCK.
3 XLAT O DSP/SSP LATCH.
4 OSD-CS O OSD LATCH.
5 OSD-DATA O OSD DATA.
6 (RESERVE) O (OPEN)
7 OSD-CLK O OSD CLOCK.
8 BYTE I Pulled down.
9 CNVSS I “H” during FLASH writing.
10 NSP O “L” is output during double-speed rotation (peak switching).
11 XVCD O “L” is output during VCD and CVD (spindle gain switching).
12 XRESET I RESET input.
13 XOUT O Connected to the 10 MHz ceramic oscillator.
14 VSS — Ground.
15 XIN I Connected to the 10 MHz ceramic oscillator.
16 VCC — Connected to 5 V.
17 XMNI I Pulled up.
18 SCOR I Sub-code sync input. “H” during S0 and S1 input.
19 CVD-INT I CVD INT input.
20 V-SYNC I V-SYNC input.
21 D-MUTE O DSP MUTE output.
22 MD2 O DIGITAL OUT control output.
23 NT/PAL O NTSC/PAL switching output. PAL at “H”.
24 PAL60 O PAL60 switching output. PAL60 at “H”.
25 EMPHA I Emphasis input.
26 XTSL O DSP XTSL output. “H” at double-speed mode.
27 I/O-BUSY I/O HOST communication BUSY input/output.
28 I-CLK I HOST communication: CLOCK input.
29 COMMAND I HOST communication: COMMAND input.
30 STATUS O HOST communication: STATUS input.
31 F-TX I FLASH TX.
32 F-RX O FLASH RX.
33 F-CLK I FLASH CLK.
34 F-RTS I FLASH RTS.
35 (RESERVE) O (OPEN)
36 SQSO I Input such as SUBQ.
37 SQCK O Clock output for SCOR read-out.
38 — I (OPEN)
39 CVD-WAIT I CVD WAIT.
40 (RESERVE) O (OPEN)
41 F-HOLD O FLASH HOLD.
23
Pin No. Pin Name I/O Description
42, 43 (RESERVE) O (OPEN)
44 CVD-RD O CVD RD
45 (RESERVE) O (OPEN)
46 F-XWRL/CVD-XWR O FLASH XWRL/CVD XWR.
47 XV MUTE O (OPEN)
48 CVD-CS O CVD CS.
49 — O (OPEN)
50 O-EMPHA O Emphasis output.
51 RBPLS O Tracking balance fraction output.
52 AMUTE O AUDIO MUTE. MUTE at “H”.
53 XRST O DSP/SSP RESET output.
54 XHRST O MPEG/OSD/DAC RESET input.
55-61 — O (OPEN)
62 VCC — Connected to 5 V.
63 — O (OPEN)
64 VSS — Ground
65-69 — O (OPEN)
70-72 HADDRS2-0 O CVD ADDRESS BUS: 2-0.
73 CHK3 O Check output for development: 3 (PICTURE-V).
74 CHK2 O Check output for development: 2 (PLAY “L”).
75 CHK1 O Check output for development: 1.
76 CHK0 O Check output for development: 0.
77 LOGO I Starts up in VIDEO CD LOGO when “L” is set.
78 *2PB I Starts up in double-speed play mode when “L” is set.
79 MCHK I Starts up in the MOMORY CHK MODE when “L” is set.
80 DISP I Performs the OSD display of the self-adjustment data when “L” is set.
81-88 HDATA7-0 I/O CVD DATA BUS: 7-0
89 FOK I FOK input.
90 GFS I GFS input.
91 — I (OPEN)
92 ILSW I PICKUP INSIDE input. “L” during INSIDE detection
93 SENS I DSP SENS input.
94 SENS2 I SENSE2 input.
95 IVSW I NTSL/PAL AUTO/PAL input.
96 VSS — Ground.
97 HALT I HALT input. HALT when input is beyond the specified value.
98 AVREF I Connected to 5 V.
99 AVDD — Connected to 5 V.
100 (RESERVE) I (OPEN)
24
IC, CL8820
Pin No. Pin Name Description
1 VCC3 Connected to 3.3 V.
2 MDATA46 Connected to D-RAM DATA LINE #46.
3 GND Connected to ground.
4 MDATA45 Connected to D-RAM DATA LINE #45.
5 MDATA44 Connected to D-RAM DATA LINE #44.
6 MDATA43 Connected to D-RAM DATA LINE #43.
7 MDATA42 Connected to D-RAM DATA LINE #42.
8 MDATA41 Connected to D-RAM DATA LINE #41.
9 MDATA40 Connected to D-RAM DATA LINE #40.
10 MDATA39 Connected to D-RAM DATA LINE #39.
11 VCC3 Connected to 3.3 V.
12 MDATA38 Connected to D-RAM DATA LINE #38.
13 GND Connected to ground.
14 MDATA37 Connected to D-RAM DATA LINE #37.
15 MDATA36 Connected to D-RAM DATA LINE #36.
16 GND Connected to ground.
17 MDATA35 Connected to D-RAM DATA LINE #35.
18 MDATA34 Connected to D-RAM DATA LINE #34.
19 VCC3 Connected to 3.3 V.
20 MDATA33 Connected to D-RAM DATA LINE #33.
21 MDATA32 Connected to D-RAM DATA LINE #32.
22 MDATA31 Connected to D-RAM DATA LINE #31.
23 MDATA30 Connected to D-RAM DATA LINE #30.
24 MDATA29 Connected to D-RAM DATA LINE #29.
25 MDATA28 Connected to D-RAM DATA LINE #28.
26 MDATA27 Connected to D-RAM DATA LINE #27.
27 MDATA26 Connected to D-RAM DATA LINE #26.
28 MDATA25 Connected to D-RAM DATA LINE #25.
29 MDATA24 Connected to D-RAM DATA LINE #24.
30 GND Connected to ground.
31 MDATA23 Connected to D-RAM DATA LINE #23.
32 MDATA22 Connected to D-RAM DATA LINE #22.
33 MDATA21 Connected to D-RAM DATA LINE #21
34 VCC3 Connected to 3.3 V.
35 MDATA20 Connected to D-RAM DATA LINE #20.
36 MDATA19 Connected to D-RAM DATA LINE #19.
37 MDATA18 Connected to D-RAM DATA LINE #18.
38 MDATA17 Connected to D-RAM DATA LINE #17.
39 MDATA16 Connected to D-RAM DATA LINE #16.
40 MCE Connected to S-ROM CE.
41 MDATA15 Connected to D-RAM DATA LINE #15.
25
Pin No. Pin Name Description
42 MDATA14 Connected to D-RAM DATA LINE #14.
43 VCC3 Connected to 3.3 V.
44 MDATA13 Connected to D-RAM DATA LINE #13.
45 GND Connected to ground.
46 MDATA12 Connected to D-RAM DATA LINE #12.
47 MDATA11 Connected to D-RAM DATA LINE #11.
48 GND Connected to ground.
49 MDATA10 Connected to D-RAM DATA LINE #10.
50 MDATA9 Connected to D-RAM DATA LINE #9.
51 MDATA8 Connected to D-RAM DATA LINE #8.
52 VCC3 Connected to 3.3 V.
53 MDATA7 Connected to D-RAM DATA LINE #7.
54 MDATA6 Connected to D-RAM DATA LINE #6.
55 MDATA5 Connected to D-RAM DATA LINE #5.
56 MDATA4 Connected to D-RAM DATA LINE #4.
57 MDATA3 Connected to D-RAM DATA LINE #3.
58 MDATA2 Connected to D-RAM DATA LINE #2.
59 MDATA1 Connected to D-RAM DATA LINE #1.
60 MDATA0 Connected to D-RAM DATA LINE #0.
61 MRAS1 Not connected.
62 GND Connected to ground.
63 MRAS0 Connected to RAS of DRAM.
64 MCAS1 Connected to CAS of higher bits DRAM.
65 MWE Connected to WE of DRAM.
66 MCAS0 Connected to CAS of lower bits DRAM.
67 MADDR8 Connected to D-RAM ADDRESS LINE #8.
68 VCC3 Connected to 3.3 V.
69 MADDR7 Connected to D-RAM ADDRESS LINE #7.
70 MADDR6 Connected to D-RAM ADDRESS LINE #6.
71 MADDR5 Connected to D-RAM ADDRESS LINE #5.
72 MADDRH4 Connected to high D-RAM ADDRESS LINE #4.
73 MADDR4 Connected to D-RAM ADDRESS LINE #4.
74 MADDR3 Connected to D-RAM ADDRESS LINE #3.
75 VCC3 Connected to 3.3 V.
76 MADDR2 Connected to D-RAM ADDRESS LINE #2.
77 GND Connected to ground.
78 MADDRH1 Connected to high D-RAM ADDRESS LINE #1.
79 MADDR1 Connected to D-RAM ADDRESS LINE #1.
80 MADDR0 Connected to D-RAM ADDRESS LINE #0.
81 GND Connected to ground.
82 VCLK Inputs 27 MHz.
26
Pin No. Pin Name Description
83 VDATA0 Connected to VIDEO DAC DATA #0.
84 VDATA1 Connected to VIDEO DAC DATA #1.
85 VDATA2 Connected to VIDEO DAC DATA #2.
86 VDATA3 Connected to VIDEO DAC DATA #3.
87 VCC3 Connected to 3.3 V.
88 VDATA4 Connected to VIDEO DAC DATA #4.
89 VDATA5 Connected to VIDEO DAC DATA #5.
90 VDATA6 Connected to VIDEO DAC DATA #6.
91 VDATA7 Connected to VIDEO DAC DATA #7.
92 VSYNC Y-SYNC output.
93 HSYNC H-SYNC output.
94 GND Connected to ground.
95 DA-DATA AUDIO DAC DATA output.
96 DA-LRCK AUDIO DAC LRCK output.
97 DA-BCK AUDIO DAC BCK output.
98 DA-XCK AUDIO DAC CLOCK output.
99 IEC-958 Not connected.
100 CD-DATA CD I/F DATA input.
101 CD-LRCK CD I/F LRCK input.
102 VCC3 Connected to 3.3 V.
103 CD-BCK CD I/F BCK input.
104 CD-C2PO CD I/F C2P0 input.
105 NC Not connected.
106 VDDMAX VDD potential of control microprocessor is given.
107 NC Not connected.
108 VCC3 Connected to 3.3 V.
109 NC Not connected.
110 GND Connected to ground.
111 NC Not connected.
112 GND Connected to ground.
113 REQUEST Not connected.
114 CASTROBE Pulled down to ground.
115 DACK Pulled down to 3.3 V.
116 ERROR Pulled down to ground.
117 SYSCLK Inputs 27 MHz.
118 NC Not connected.
119 RESET Reset input.
120 HDATA0 Parallel communication data line with control microprocessor #0.
121 HDATA1 Parallel communication data line with control microprocessor #1.
122 VCC3 Connected to 3.3 V.
123 HDATA2 Parallel communication data line with control microprocessor #2.
27
Pin No. Pin Name Description
124 HDATA3 Parallel communication data line with control microprocessor #3.
125 HDATA4 Parallel communication data line with control microprocessor #4.
126 HDATA5 Parallel communication data line with control microprocessor #5.
127 GND Connected to ground.
128 HDATA6 Parallel communication data line with control microprocessor #6.
129 HDATA7 Parallel communication data line with control microprocessor #7.
130 WAIT Parallel communication WAIT control line with control microprocessor.
131 INT Parallel communication INT control line with control microprocessor.
132 RD Parallel communication RD control line with control microprocessor.
133 R/W or WR Parallel communication R/W control line with control microprocessor.
134 AVCC Connected to clearer 3.3 V.
135 CS Parallel communication WAIT control line with control microprocessor.
136 AGND Connected to clearer ground.
137 HADDR0 Parallel communication address line with control microprocessor #0.
138 HADDR1 Parallel communication address line with control microprocessor #1.
139 HADDR2 Parallel communication address line with control microprocessor #2.
140 MDATA63 Connected to D-RAM DATA LINE #63.
141 MDATA62 Connected to D-RAM DATA LINE #62.
142 MDATA61 Connected to D-RAM DATA LINE #61.
143 MDATA60 Connected to D-RAM DATA LINE #60.
144 VCC3 Connected to 3.3 V.
145 MDATA59 Connected to D-RAM DATA LINE #59.
146 VCC3 Connected to 3.3 V.
147 MDATA58 Connected to D-RAM DATA LINE #58.
148 GND Connected to ground.
149 MDATA57 Connected to D-RAM DATA LINE #57.
150 GND Connected to ground.
151 MDATA56 Connected to D-RAM DATA LINE #56.
152 MDATA55 Connected to D-RAM DATA LINE #55.
153 MDATA54 Connected to D-RAM DATA LINE #54.
154 MDATA53 Connected to D-RAM DATA LINE #53.
155 MDATA52 Connected to D-RAM DATA LINE #52.
156 MDATA51 Connected to D-RAM DATA LINE #51.
157 MDATA50 Connected to D-RAM DATA LINE #50.
158 MDATA49 Connected to D-RAM DATA LINE #49.
159 MDATA48 Connected to D-RAM DATA LINE #48.
160 MDATA47 Connected to D-RAM DATA LINE #47.
28
IC, SM5878AM
Pin No. Pin Name I/O Description
MODE = H: Soft mute ON/OFF terminal. (Mute at H).
1 MUTE I
MODE = L: Attenuator level DOWN/UP terminal. (DOWN at H).
2 DEEM I De-emphasis ON/OFF terminal. (De-emphasis ON at H).
3 CKO O Oscillator clock output. (16.9344 MHz).
4 DVSS — Digital VSS terminal.
5 BCKI I Bit clock input terminal.
6 DI I Serial data input terminal.
7 DVDD — Digital VDD terminal.
8 LRCI I Sample rate clock (fs) input terminal. (H = L ch/L = R ch).
9 TSTN I Test input. (“H” or open during normal operation)
10 TO1 O Test output 1. (Normally low level output).
11 AVDDL — Analog VDD terminal. (For L ch).
12 LO O Left channel analog output terminal.
13 AVSS — Analog VSS terminal.
14 RO O Right channel analog output terminal.
15 AVDDR — Analog VDD terminal. (For R ch).
16 MUTEO O Infinity zero detection output.
17 XVDD — X’tal system VDD terminal.
18 XTI I X’tal oscillator terminal. (Or external clock input terminal of 16.9344 MHz).
19 XTO O X’tal oscillator terminal.
20 XVSS — X’tal system VSS terminal.
21 DS I Double-speed/normal playback selection. (Double-speed at H).
22 RSTN I Reset terminal. (Reset at L).
23 MODE I Soft mute/Attenuator mode selection. (Soft mute at H).
24 ATCK I Attenuator level setup clock (Ignored when MODE = H).
29
MECHANICAL EXPLODED VIEW 1/1
A 10
A
9 11
13
12
14
45
E
16
42 17
19 18
15
20
P.C.B
P.C.B
22
8 21
23
7 24
6
D
5
4 3
2
B
26
40 25
28
33
1 34 41
35 29
36 30
P.C.B 31
27
37 32 43
D C
38
P.C.B 39
3ZG-2 E2
CUSH CD A
44
30
MECHANICAL PARTS LIST 1/1
REF. NO PART NO. KANRI DESCRIPTION REF. NO PART NO. KANRI DESCRIPTION
NO. NO.
1 86-ZG1-001-410 TRAY,5CD 26 86-ZG1-210-110 SLIDER,CAM R(*)
2 84-ZG1-267-010 PULLEY,LOAD MO 8 27 87-045-305-010 MOTOR, RF-500TB DC-5V (2MA)
3 87-A90-036-010 MOT ASSY,RF-300CA-11 28 84-ZG2-228-010 PULLEY,MOT
4 86-ZG1-228-110 GEAR,TT-B 29 83-ZG3-211-010 PLATE,DISC
5 86-ZG1-227-110 GEAR,TT-A 30 83-ZG3-604-010 RING,MAG 2
31
CD MECHANISM EXPLODED VIEW 1/1
3
1
A
6 M21
SW1
5
P.C.B
6 83-ZG2-253-010 SHAFT,SLIDE 5
A 87-261-032-210 V+2-3
32
REFERENCE NAME LIST
ELECTRICAL SECTION MECHANICAL SECTION
DESCRIPTION REFERENCE NAME DESCRIPTION REFERENCE NAME
WHL WHEEL
WORM-WHL WORM-WHEEL
33
2–11, IKENOHATA 1–CHOME, TAITO-KU, TOKYO 110-8710, JAPAN TEL:03 (3827) 3111
931261 Printed in Singapore