LABORATORY MANUAL

DEPARTMENT OF
MECHANICAL ENGINEERING
FACULTY OF ENGINEERING

BTME 4533
Digital Electronics and Microprocessors
 Content

Experiment Title Page

number
1 Introduction to the FX8031 IDE Software and Programming 2~5
Fundamentals

2 Data Transfer and Addressing Modes 6~8

3 Logical Operations 9 ~ 11
4 Arithmetic Operations 12 ~ 13
5 Interrupt and Timer Instructions 14 ~ 15
- Appendixes 16 ~ 23

1
 Experiment 1:
Introduction to the FX8031 IDE Software and Programming Fundamentals

Objectives:
To demonstrate program development procedures using the FX8031 Integrated
Development Environment (IDE) interface.
To learn and understand programming fundamentals of 8051 microcontroller.

FX8031 Development Environment

FX8031 IDE is an Integrating Development Environment for 8051 microcontroller
system which includes:
a source code editor,
assembler,
linker
list file
hex codes view
programmer
virtual machine
wizards

Virtual Machine Features

Virtual machine simulates most of AT89S8252/1 core in PC. It allows single stepping
(step in and step over), run to cursor, run until RET, run and pause. In addition, it
simulates AT89S8252/1 hardware capabilities also.
These hardware simulations are:
I/O ports
Timer 0
Timer 1
Timer 2
Interrupt masking and priority
UART
Watchdog timer

2
Experiment 1A: FX8031 Development Kit Start Up

This experiment is to let you know how to start writing your own program or assembly
code. Among the processes involved are writing, assembling, compiling and debugging an
Intel 8051 assembly code. Now, lets start our experiment by following the step-by-
step guidance given as follows.

Figure 1 : FX8031 IDE

1. Go to FX8031 Development kit and click on FX8031 IDE.

2. A new window, NONAME.FXP will show up.
3. Click PROJECT > SAVE AS and save your project name as EXP1.FXP.
4. Click FILE > NEW and you can see NONAME.ASM
5. Type in the following assembly codes.

CSEG ; start of code segment

ORG 0000H ;program code bytes start at address 0000H
MOV A, #28H
MOV R0, #29H
ADD R0, A
ENDS ;end of code segment
END ;end of program

6. Click FILE > SAVE AS and save your file name as exp1a.asm.
7. Under the Project tab, add your exp1a.asm file by right clicking and ADD FILE.
8. Also add the include file, at89c51.inc using the same way as exp1a.asm.
at89c51.inc can be located at C:\program files\FX8031\include\.
9. You can now compile your program by selecting BUILD from PROJECT menu.
10. If there is no error, a successful message will show on the output window and
3
 the HEX file will be generated.
11. Correct your program if error message appear.
12. Every single time your codes are changed, you must SAVE it again before
compiling and running it.
13. To run the software simulate, click START from the VIRTUAL MACHINE
(CTRL + D)
14. Simulate your program by pressing F7 button for single stepping. (Single step
means that you run the program line by line).

Verify the contents of A and R0 after executing the program in Experiment

1A.
Check the status bits of CY, AC and P in PSW.

Question:

1. Which part of the code is in error? Explain why.

__________________________________________________________________
__________________________________________________________________
__________________

2. Write the corrected code below:

3. What is the final content of Accumulator (A) and register R0?

_____________________________________________________________

4. What are the status of CY, AC and P at the end of the program execution?

__________________________________________________________________
__________________________________________________________________

Experiment 1B: Programming Exercise II - Familiarization with Register A, PSW

and DPTR

1. Try out the following program.

MOV A, #17H
4
 MOV R2, #24H
ADD A, R2
MOV PSW, #18H
MOV R2, A
MOV DPTR, #0AABBH
MOV R0, DPL
MOV R1, DPH
2. Simulate the program and tabulate the result in Table 2 of your lab report.

Answer:

Instruction Result
MOV A, #17H Content of A =

MOV R2, #24H Address of R2 = , Content of R2 =

ADD A, R2 Content of A =

MOV PSW, #18H Content of PSW in bits =

MOV R2, A Address of R2 = , Content of R2 =

MOV DPTR, #0AABBH Content of DPTR =

MOV R0, DPL Address of R0 = , Content of R0 =

MOV R1, DPH Address of R1 = , Content of R1 =

5
 Experiment 2:
Data Transfer and Addressing Mode

Objective: To learn different modes of data transfer by using various addressing modes

A computer typically spends more time moving data from one location to another
than it spends on any other operation.
Data is stored at a source address and moved to a destination address.
The ways by which these addresses are specified are called the addressing modes.
8051 memory is divided into the following four distinct physical parts:
Internal RAM
Internal special-function registers
External RAM
Internal and External ROM

Figure 2.1 Block diagram of 8051 memory

The following four addressing modes are commonly used to access data:
Immediate addressing mode
Register addressing mode
Direct addressing mode
Indirect addressing mode

6
Experiment 2A: Programming Exercise - Put the number 8DH in RAM locations
03H to 07H.

Method 1: Use the immediate number and direct address.

MOV 03H, #8DH ; Copy the number 8DH to address 03H

MOV 04H, #8DH ; Copy the number 8DH to address 04H
MOV 05H, #8DH ; Copy the number 8DH to address 05H
MOV 06H, #8DH ; Copy the number 8DH to address 06H
MOV 07H, #8DH ; Copy the number 8DH to address 07H

Method 2: Use the accumulator and direct address.

MOV A, #8DH ; Copy the number 8DH to the accumulator

MOV 03H, A ; Copy the number 8DH from A to address 03H
MOV 04H, A ; Copy the number 8DH from A to address 04H
MOV 05H, A ; Copy the number 8DH from A to address 05H
MOV 06H, A ; Copy the number 8DH from A to address 06H
MOV 07H, A ; Copy the number 8DH from A to address 07H

Method 3: Use the accumulator, A and Registers

MOV A, #8DH ; Copy the number 8DH to the accumulator

MOV R3, A ; Copy the contents of A to location R3
MOV R4, A ; Copy the contents of A to location R4
MOV R5, A ; Copy the contents of A to location R5
MOV R6, A ; Copy the contents of A to location R6
MOV R7, A ; Copy the contents of A to location R7

Method 4: Using indirect addressing mode with R0 as pointer

MOV R0, #03H ; make R0 point to location 03H

MOV A, #8DH ; load number 8DH into accumulator
REP: MOV @R0, A ; copy the content of A into location pointed by R0
INC R0 ; increase the value in R0, i.e. point to the next location
CJNE R0, #08H, REP ; location 08H reached, if not, go to REP to repeat
; the operation

1. Compile and observe the functions of each method.

2. Find the start address, machine code, number of byte and number of cycle for
each instruction.
3. Fill in table 1 to 4 .
4. Compare all the methods and write down your conclusion in your report.

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 Address Code (Hex) Instruction Byte Cycle
0000H 75 03 8D MOV 03H,#8DH 3 2

Total
Table 1: Method 1

Address Code (Hex) Instruction Byte Cycle

Total
Table 2: Method 2

Address Code (Hex) Instruction Byte Cycle

Total
Table 3: Method 3

Address Code (Hex) Instruction Byte Cycle

Total
Table 4: Method 4

Conclusion: Which programming method is the best? State the reason.

8
Experiment 3: Logical Operation

Objective: To learn the use of logical operation that concerns Boolean algebras.

One of 8051s functions is machine control.

A large part of machine control concerns sensing the on/off states of external
switches, making decision based on the switch states, and then turning external
circuits on or off. Implementation of machine control includes byte and bit
opcodes that operate on data using Boolean operators.

Experiment 3.1: Logical Operations

Compile the following program and record the result after every instruction has been
executed in the table below.

MOV A, #0FFH
MOV R0, #77H
ANL A, R0
MOV 15H, A
CPL A
ORL 15H, #80H
XRL A, 15H

Instruction Result
MOV A, #0FFH Content of A =

MOV R0, #77H Content of R0 =

ANL A, R0 Content of A =

MOV 15H, A Content of 15H=

CPL A Content of A =

ORL 15H, #80H Content of 15H=

XRL A, 15H Content of A=

Table 3.1

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Experiment 3.2 Rotate and Swap Operations

.
Compile the following programs:

Program 3.2

MOV A, #0A5H
CLR C
RRC A
RL A
SWAP A
RLC A
SWAP A

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Instruction Result of destination operand CY Content of A in binary P
MOV A, #0A5H
CLR C
RRC A
RL A
SWAP A
RLC A
SWAP A

Table 3.2

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 Experiment 4: Arithmetic Operation

Objective: To learn methods of manipulating data using the arithmetic operation and the
flags which are affected by the operation.

The 8051 has 3 arithmetic flags:

i) Carry (C )
ii) Auxiliary Carry (AC)
iii) Overflow (OV)

Experiment 4.1 Multiplication

Type and compile the following program. Fill in table 4.1

MOV A, #7BH
MOV 0F0H, #02H
MUL AB
MOV R0, B
MOV B, #0FEH
MUL AB
MOV R0, B

Instruction Result of destination operand

Table 4.1

Results: High byte = H, Low byte = H

Value in decimal =

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Experiment 4.2 Division

Type and compile the following program. Fill in table 4.2

MOV A, #0FFH
MOV 0F0H, #2CH
DIV AB
MOV R0, B

Instruction Result of destination operand

Table 4.2
Results: Quotient = H, Remainder = H
Values in decimal =

Experiment 4.3 Subtraction

Type and compile the following program. Fill in table 4.3

CLR C
MOV A, #64H
SUBB A, #0FH

Instruction Result of destination operand CY AC OV P

Table 4.3
Experiment 4.4 Addition

Type and compile the following program. Fill in the table 4.4

MOV A, #5FH
ADD A, #0BDH

Instruction Result of destination operand CY AC OV P

Table 4.4

13
Experiment 5: Program Interrupt and Timer Instructions

Objective: To study the interrupt and timer instructions

AT89S8252 has 6 interrupts

* 2 external interrupts (INT0 & INT1)

* 3 Timer interrupts (Timer 0,1,2)

* Serial Port interrupts

External Interrupt INT0 and INT1

Use when an important external event occurrence need the attention of the CPU
while the CPU is attending another task
Once interrupt conditions is detected, CPU will push the current PC value to the
Stack Memory and load the PC with the Interrupt vectors.
However, the above will happen if and only if the Global Interrupt Enable bit
(EA) and the Interrupt masking bits are enabled. i.e EX0 (INT0) and EX1
(INT1).
INT0 & INT1 Interrupt Vectors locations

External Vector Enable Interrupt

Bits Flags
Interrupt

INT0 0003h EX0 IE0

INT1 0013h EX1 IE1

Experiment 5A: Programming Exercise INTERRUPT

LED1 equ P1.0

LED2 equ P1.1

cseg
org RESET_VECTOR
sjmp START
ends

cseg
org EX0_VECTOR
14
EX0_ISR:
jb LED1,EX0_ISR1
setb LED1
reti
EX0_ISR1:
clr LED1
reti
ends

cseg
org EX1_VECTOR
EX1_ISR:
jb LED2,EX1_ISR1
setb LED2
reti
EX1_ISR1:
clr LED2
reti
ends

cseg
START:
mov SP,#80h
clr P1 ; Light up all LEDs
setb IT0 ; Set EX0 as falling edge trigger

; Enable INT0, INT1 and global interrupts

mov IE,#%10000101
HANG:
sjmp HANG
ends
end

APPENDIX A: Intel 8051 opcode map

15
16
APPENDIX B: Intel 8051 Instruction Set Summary

Mnemonic Description Byte Cycle

Arithmetic Operations
ADD A,Rn Add register to accumulator A 1 1
ADD A,direct Add direct byte to accumulator A 2 1
ADD A,@Ri Add indirect RAM to accumulator A 1 1
ADD A,#data Add immediate data to accumulator A 2 1
ADDC A,Rn Add register to accumulator A with carry flag 1 1
ADDC A,direct Add direct byte to accumulator A with carry flag 2 1
ADDC A,@Ri Add indirect RAM to accumulator A with carry flag 1 1
ADDC A,#data Add immediate data to accumulator A with carry flag 2 1
SUBB A,Rn Subtract register from accumulator A with borrow 1 1
SUBB A,direct Subtract direct byte from accumulator A with borrow 2 1
SUBB A,@Ri Subtract indirect RAM from accumulator A with borrow 1 1
SUBB A,#data Subtract immediate data from accumulator A with borrow 2 1
INC A Increment accumulator A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 1
INC @Ri Increment indirect RAM 1 1
DEC A Decrement accumulator A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 1
DEC @Ri Decrement indirect RAM 1 1
INC DPTR Increment data pointer 1 2
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 4
DA A Decimal adjust accumulator A 1 1
Logic Operations
ANL A,Rn AND register to accumulator A 1 1
ANL A,direct AND direct byte to accumulator A 2 1
ANL A,@Ri AND indirect RAM to accumulator A 1 1
ANL A,#data AND immediate data to accumulator A 2 1
ANL direct,A AND accumulator A to direct byte 2 1
ANL direct,#data AND immediate data to direct byte 3 2
ORL A,Rn OR register to accumulator A 1 1
ORL A,direct OR direct byte to accumulator A 2 1
ORL A,@Ri OR indirect RAM to accumulator A 1 1
ORL A,#data OR immediate data to accumulator A 2 1
ORL direct,A OR accumulator A to direct byte 2 1
ORL direct,#data OR immediate data to direct byte 3 2
XRL A,Rn Exclusive OR register to accumulator A 1 1
XRL A,direct Exclusive OR direct byte to accumulator A 2 1
XRL A,@Ri Exclusive OR indirect RAM to accumulator A 1 1
XRL A,#data Exclusive OR immediate data to accumulator A 2 1
XRL direct,A Exclusive OR accumulator A to direct byte 2 1
XRL direct,#data Exclusive OR immediate data to direct byte 3 2
CLR A Clear accumulator A 1 1
CPL A Complement accumulator A 1 1
RL A Rotate accumulator A left 1 1
RLC A Rotate accumulator A left through carry 1 1
RR A Rotate accumulator A right 1 1
RRC A Rotate accumulator A right through carry 1 1
SWAP A Swap nibbles within the accumulator A 1 1

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APPENDIX B: Intel 8051 Instruction Set Summary

Mnemonic Description Byte Cycle

Data Transfer
MOV A,Rn Move register to accumulator A 1 1
MOV A,direct Move direct byte to accumulator A 2 1
MOV A,@Ri Move indirect RAM to accumulator A 1 1
MOV A,#data Move immediate data to accumulator A 2 1
MOV Rn,A Move accumulator A to register 1 1
MOV Rn,direct Move direct byte to register 2 2
MOV Rn,#data Move immediate data to register 2 1
MOV direct,A Move accumulator A to direct byte 2 1
MOV direct, Rn Move register to direct byte 2 2
MOV direct,direct Move direct byte to direct byte 3 2
MOV direct,@Ri Move indirect RAM to direct byte 2 2
MOV direct,#data Move immediate data to direct byte 3 2
MOV @Ri,A Move accumulator A to indirect RAM 1 1
MOV @Ri,direct Move direct RAM to indirect RAM 2 2
MOV @Ri,#data Move immediate data to indirect RAM 2 1
MOV DPTR,#data16 Load data pointer with 16-bit constant 3 2
MOVC A,@A+DPTR Move code byte relative to DPTR to accumulator A 1 2
MOVC A,@A+PC Move code byte relative to PC to accumulator A 1 2
MOVX A,@Ri Move external RAM (8-bit address) to accumulator A 1 2
MOVX A,@DPTR Move external RAM (16-bit address) to accumulator A 1 2
MOVX @Ri,A Move accumulator A to external RAM (8-bit address) 1 2
MOVX @DPTR,A Move accumulator A to external RAM (16-bit address) 1 2
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A,Rn Exchange register with accumulator A 1 1
XCH A,direct Exchange direct byte with accumulator A 2 1
XCH A,@Ri Exchange indirect RAM with accumulator A 1 1
XCHD A,@Ri Exchange low-order nibble indirect RAM with 1 1
accumulator A
Boolean Variable Manipulation
CLR C Clear carry flag 1 1
CLR bit Clear direct bit 2 1
SETB C Set carry flag 1 1
SETB bit Set direct bit 2 1
CPL C Complement carry flag 1 1
CPL bit Complement direct bit 2 1
ANL C,bit AND direct bit to carry flag 2 2
ANL C,/bit AND complement of direct bit to carry flag 2 2
ORL C,bit OR direct bit to carry flag 2 2
ORL C,/bit OR complement of direct bit to carry flag 2 2
MOV C,bit Move direct bit to carry flag 2 1
MOV bit,C Move carry flag to direct bit 2 2

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APPENDIX B: Intel 8051 Instruction Set Summary

Mnemonic Description Byte Cycle

Program and Machine Control
ACALL addr11 Absolute call to subroutine 2 2
LCALL addr16 Long call to subroutine 3 2
RET Return from subroutine 1 2
RETI Return from interrupt 1 2
AJMP addr11 Absolute jump 2 2
LJMP addr16 Long jump 3 2
SJMP rel Short jump 2 2
JMP @A+DPTR Jump indirect relative to the DPTR 1 2
JZ rel Jump if accumulator is zero 2 2
JNZ rel Jump if accumulator is not zero 2 2
JC rel Jump if carry flag is set 2 2
JNC rel Jump if carry flag is not set 2 2
JB bit,rel Jump if direct bit is set 3 2
JNB bit,rel Jump if direct bit is not set 3 2
JBC bit,rel Jump if direct bit is set and clear bit 3 2
CJNE A,direct,rel Compare direct byte to accumulator A and jump if not 3 2
equal
CJNE A,#data,rel Compare immediate data to accumulator A and jump if 3 2
not equal
CJNE Rn,#data,rel Compare immediate data to register and jump if not equal 3 2
CJNE @ri,#data,rel Compare immediate data to indirect RAM and jump if not 3 2
equal
DJNZ Rn,rel Decrement register and jump if not zero 2 2
DJNZ Direct,rel Decrement direct byte and jump if not zero 3 2
NOP No operation 1 1

19
APPENDIX C: ASCII Printable Characters

Binary Oct Dec Hex Binary Oct Dec Hex

Glyph Glyph
010 0000 040 32 20 SP 101 0000 120 80 50 P
010 0001 041 33 21 ! 101 0001 121 81 51 Q
010 0010 042 34 22 " 101 0010 122 82 52 R
010 0011 043 35 23 # 101 0011 123 83 53 S
010 0100 044 36 24 $ 101 0100 124 84 54 T
010 0101 045 37 25 % 101 0101 125 85 55 U
010 0110 046 38 26 & 101 0110 126 86 56 V
010 0111 047 39 27 ' 101 0111 127 87 57 W
010 1000 050 40 28 ( 101 1000 130 88 58 X
010 1001 051 41 29 ) 101 1001 131 89 59 Y
010 1010 052 42 2A * 101 1010 132 90 5A Z
010 1011 053 43 2B + 101 1011 133 91 5B [
010 1100 054 44 2C , 101 1100 134 92 5C \
010 1101 055 45 2D - 101 1101 135 93 5D ]
010 1110 056 46 2E . 101 1110 136 94 5E ^
010 1111 057 47 2F / 101 1111 137 95 5F _
011 0000 060 48 30 0 110 0000 140 96 60 `
011 0001 061 49 31 1 110 0001 141 97 61 a
011 0010 062 50 32 2 110 0010 142 98 62 b
011 0011 063 51 33 3 110 0011 143 99 63 c
011 0100 064 52 34 4 110 0100 144 100 64 d
011 0101 065 53 35 5 110 0101 145 101 65 e
011 0110 066 54 36 6 110 0110 146 102 66 f
011 0111 067 55 37 7 110 0111 147 103 67 g
011 1000 070 56 38 8 110 1000 150 104 68 h
011 1001 071 57 39 9 110 1001 151 105 69 i
011 1010 072 58 3A : 110 1010 152 106 6A j
011 1011 073 59 3B ; 110 1011 153 107 6B k
011 1100 074 60 3C < 110 1100 154 108 6C l
011 1101 075 61 3D = 110 1101 155 109 6D m
011 1110 076 62 3E > 110 1110 156 110 6E n
011 1111 077 63 3F ? 110 1111 157 111 6F o
100 0000 100 64 40 @ 111 0000 160 112 70 p
100 0001 101 65 41 A 111 0001 161 113 71 q
100 0010 102 66 42 B 111 0010 162 114 72 r
100 0011 103 67 43 C 111 0011 163 115 73 s
100 0100 104 68 44 D 111 0100 164 116 74 t
100 0101 105 69 45 E 111 0101 165 117 75 u
100 0110 106 70 46 F 111 0110 166 118 76 v
100 0111 107 71 47 G 111 0111 167 119 77 w
100 1000 110 72 48 H 111 1000 170 120 78 x
100 1001 111 73 49 I 111 1001 171 121 79 y
100 1010 112 74 4A J 111 1010 172 122 7A z
100 1011 113 75 4B K 111 1011 173 123 7B {
100 1100 114 76 4C L 111 1100 174 124 7C |
100 1101 115 77 4D M 111 1101 175 125 7D }
100 1110 116 78 4E N 111 1110 176 126 7E ~
100 1111 117 79 4F O

20
APPENDIX D: Summary of the 8051 on-chip data memory

21
APPENDIX E: Jump Instruction Ranges

22
APPENDIX F: PSW register

The Program Status Word (PSW) contains status bits that reflect the current MPU state.

23