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International Journal of Pure and Applied Mathematics

Volume 115 No. 7 2017, 423-427


ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version)
url: http://www.ijpam.eu
Special Issue
ijpam.eu

IMPLEMENTATION OF QUARTER CYCLE KEY CRYPTOGRAPHIC ALGORITHM


USING VERILOG HDL

Deekshatha A1, Fazal Noorbasha2, Harikishore Kakarla3, P.G.Mounika4, N.GangaDheeraj5,


6
M. Manasa
1,2,3,4,5,6
Department of Electronics and Communication Engineering,
K L University, Vaddeswaram, Guntur, A.P. India 522502
2
fazalnoorbasha@kluniversity.in, 6manasamuliki@kluniversity.in

Abstract:The increasing concerns regarding the the data into cryptographic cipher and then there by
security purposes led to the use of encryption during increasing more security by further processing it so that
the transmission of information. Encryption is the the information is more secured and hidden for the
process of converting information or data into a code, outer sources. Thus the data encryption standards are
especially to prevent authorized access. In this paper made by the agencies within contexts of a total security
we developed a three level data encryption process. A programs like security procedures, confidential
cryptography algorithm has implemented using the information, computer systems and network access
Verilog HDL language. This code employed shall controls [10-11].
encrypt the message data at three different levels on the
2. Encryption Methodology and Implementation
transmitter and receiver side to increase security. In this
paper we go for the three level encryption processes
where the encryption is made first by XORing data
with the key phases and then second hamming code and
finally bits shuffling for additional security. We have
used 8-bit data as input and got 13-bit encrypted data.
As we go for the higher level encryption we get the
higher level security for the information.
Key Words: - Encryption, XOR, Hamming code,
Shuffling, Verilog, FPGA.
1. Introduction
In this modern world where the technology is very
advanced and where its importance is enhanced and so
the protection of the information is very essential [1-3]. Figure 1. Flow chart of data encryption
The application of the technology selection and the In this paper, we have three levels. During our first
related safeguard procedures are important level, we take an 8-bit input data (as the binary data is
responsibilities of every prominent organisation in to be expressed as 2-Radix). Then we use QPSK
providing the sufficient security to its electronic data principle. In QPSK, the modulator shifts carrier to one
systems [4-6]. Thus we go for cryptography which is of four possible phases corresponding to the four
the manipulation of the actual message where the actual possible values of the input symbol. We are
message is sent with protection where the confidential implementing the quarter cycle implementation where
data is secured so that the actual content is deciphered the whole cycle of the signal is divided into four parts
by the right agencies. There are many methods for this with phases 45, 90,180 and 360 degrees.As QPSK
information transmission like bfsk, bpsk and qask but gives higher bandwidth, we have incorporated its
we use the principle of qpsk as it has got low bit principle in our encryption process. Now we convert
accuracy error rate and it also has the higher bandwidth the phases 45, 90,180 and 360 degrees into their binary
efficiency [7-9]. values as to be compatible with the input 8-bit binary
This proposed work specifies the quarter cycle data. Figure 1 shows the flow chart of data encryption
cryptographic algorithm methods. Protection of the process. The respective binary values are represented in
information during the transmission is very essential table1.
and also the integrity and the security of the data must
be enhanced while storing the data during the process. Table 1. binary value of phases and their respective
This algorithm explicitly defines the steps to transform selections

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International Journal of Pure and Applied Mathematics Special Issue

Let us see the whole process by taking an example of


8-bit input data 01011001.
The number of bits in the binary value of 360 is Table 6.XORed and Roundup the MSB bits with even
nine. In order to have common number of bits we add parity (Level 1)
zeroes for 180, 90 and 45 at their MSB values. So we
will have nine bit representation for all our four phases.
We also add an even parity bit at the MSB of our eight
bit input data. Therefore now we have a nine bit input
data which will be XORed with the 9 bit binary value
of the respective phases based on the selection lines
show in table 1.
In our second level, the output of the first level is Table 7. Hamming code encrypted data of table 5
taken as the nine bit input data to perform hamming (Level 2)
code. Hamming code is an improvement over parity
check method. Here a code is implemented in Verilog
in which 9 bit of information data is transmitted with
four redundancy bits [12].
Table 2. Hamming code bit placement

Table 8. Shuffling bits of tabe 6 (Level 3)


d1 to d9 bits are input bits and p1 to p4 bits are parity
bits. Table 3 is showing the parity bit calculation
process from the table 2.
Table 3.Parity bit calculation

Using input data we can calculate the parity value 3. Synthesis and Simulation Results
using the table 3. Finally we are getting a 13-bit Table 9 give the number of gates that have been used
hamming code data. Therefore the output of our second and the operations and the cycles also the error reports
level is the thirteen bit data. Further in our third level and also the utilisation and also the number of LUTs.
we divide the output of the second level data into five So this report helps us to get the entire details of the
blocks where first four blocks consists of 3 bits each devices used and their number. So we get the number
and the fifth block contains one bit as shown in the of devices or gates or LUTs placed in each level for
Table 4. the performance of the project.
Table 4. Representation of block division of 13-bit data Table 9.Logic utilization table of different phases

Now as our third level encryption we shuffle the


information data with respect to the selection lines.The
choice of shuffling is shown in table 5.
Table 5. selection for the shuffling blocks

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International Journal of Pure and Applied Mathematics Special Issue

Conference on Electrical, Electronics and


Computer Science, 2016, PP. 1-4.

Figure 2 Simulation waveforms of Encryption process [2] Indra Raj Sharma, Vipin Gupta Comparative
Analysis of DES and S-DES, Encryption Algorithm
Thus from step1 output we understand the data bits Using Verilog Coding, International Journal of
d[7:0] which are 8 bit binary numbers are EXOR ed Innovative Research in Electrical, Electronics,
with the phases which are converted into binary bits Instrumentation and Control Engineering, Vol. 1,
dk[8:0] using selection lines s[1:0] where we get an Issue 9, December 2013, PP. 469-473.
exored output of y[8:0] as output.
[3] T. Narendra Babu, Fazal Noorbasha, M. Harita, N.
Tejashree and K. Vamsi Krishna, FPGA
Implementation of High Speed Error Detection
and Correction of Orthogonal Codes using
Figure 3. Simulation waveforms of Hamming code Segmentation Method, Indian Journal of Science
process and Technology, Vol 9(30), August 2016, PP. 1-7.
In step 2 we get the output c[13:1] of 13 binary bits by
applying hamming code to the input which is the output [4] P. M. Durai Raj Vincent, Syed Amber Iqbal, Karan
of the step 1 and then they are converted into 13 bit Bhagat and Kamal Kant Kushwaha,
output by adding parity bits to the input d[9:1] by using Cryptography: a Mathematical Approach, Indian
selection lines s[1:0]. Journal of Science and Technology, Vol 6(12),
December 2013, PP 56075611.

[5] Narendra Babu T., Fazal Noorbasha, Sai Krishna


Ch., Sai Charan K. and R. S. V. S. Sai Kalyan,
Figure 4 Simulation waveforms of Shuffling data bits FPGA implementation of cryptographic system
using BODMAS sequence of operations, ARPN
In step 3 we get the output y[13:1] of the three level
Journal of Engineering and Applied Sciences, Vol.
encrypted data by taking the output obtained by step 2 as
11, No. 19, October 2016, PP. 11475- 11479.
input d[13:1] thus by further dividing it into five blocks
which are shuffled as required and thus the three level
[6] Tulasimani Lakshmanan, Madheswaran
encrypted data of the input data is obtained.
Muthusamy, A Novel Secure Hash Algorithm for
4. Conclusion Public Key Digital Signature Schemes, The
International Arab Journal of Information
We developed a simple and a new encryption process
Technology, Vol. 9, No. 3, May 2012.
using XOR, Hamming code and shuffling process. In
this process an 8-bit data is converting into a 13-bit
encrypted data. Here we have used three level of [7] Upputuri Neelima, Fazal Noorbasha, Data
Encryption and Decryption using Reed-Muller
encryption process. Hamming code is used for error
Techniques, International Journal of Engineering
detection and correction purpose. Xilinx simulation tool
and Technology (IJET), Vol 8, No 1, Feb-Mar
used to perform the code operations and so the number
2016, PP 83-91.
of gates and LUTs used can be verified and this
security pattern can be used to help for the lengthier
[8] Xiao-Bie Liu, Soo Ngee Koh, Chee-Cheon Chui
blocks of bits. Thus quarter cycle makes it very
difficult for the intruders to get on the information from and Xin-Wen Wu, A study on reconstruction of
linear scrambler using dual words of channel
the transmitters and while holding the information and
encoder, IEEE Transactions on Information
helps the receivers to decode it very easily and with
more security. This work can further be extended to the Forensics and Security, Vol. 8, No. 3, March 2013,
PP. 542-552.
decryption of the more protected and more hidden and
well protected data where we concentrated only on the
[9]Cncio Monteiro, Yasuhiro Takahashi, Toshikazu
encryption part which is an advanced one for the
Sekine, Low-power secure S-box circuit using
security to hold and to send confidential details. Thus
this could further be extended to decrypting the data charge-sharing symmetric adiabatic logic for
advanced encryption standard hardware design,
which we hope can be extended to the future.
IET Circuits, Devices & Systems, Vol.9, Iss.5,
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