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Time-frequency Quasi-matched Intelligence Receiver to

LPI Radar Signal

Deguo Zeng*, Hao Cheng, Keyu Long, Xiaodong Zeng, Haiyan Gu, Xiaodong He, Bin Tang

*School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China
Email: zedg@sina.com

beyond the abilities of the classical interception architecture.


Abstract Moreover, the developments of the phased array radar,
synthetic aperture radar and other new LPI radar systems
An intelligence receiver quasi-matched to the received undermine the advantages of the intelligence receiver. The
LPI radar signals in time and frequency domain is presented. mismatch between traditional signal processing model and
The architecture and prototype using FPGA and DSP are new radar systems leads to a upgrading of the existed
shown. The presented receiver works especially well when intelligence receiver system.
the received signals are complex and time-varying.
2. The model of the received radar signal and the
Keywords: intelligence receiver, time frequency, quasi- interception architectures
matched, electronic warfare, radar signal.

2.1 Signal Model


1. Introduction
The classical models for radar signals are mainly based
In modern electronic warfare, the radar takes over almost on the linear frequency modulation (LFM) and phase shift
the entire electromagnetic spectrum from high frequency to keying (PSK), and they are too simple to describe the
microwave, millimetre wave, infrared, even laser, etc. Further, received signals in new radar systems. Known to all, one of
the density of the radar signals is increasing over time and it the best ways to describe a signal is to choose the most
is generally believed that the full-band stream of pulses per similar signal model to fit the unknown one. The complex
second is from 300000 to 2000000. Its not an easy task for radar waveforms mentioned above could be modelled as the
the intelligence receiver to intercept signals within the whole hybrid of the polynomial phase signal, frequency agility and
frequency range under such a high signal density. Whats PRI transition, so we combine the polynomial phase signal
more, the use of low probability of intercept (LPI) radar, such and encoding signal model as the new LPI radar model which
as the pulse compression radar, makes the modern electronic could be uniformly expressed as
warfare environment more complex for the intelligence M 1 N 1
Q 1

receiver to deal with. r (t ) exp j M (m, n)  2S f (m, n)t  a (m, n)t
q
q

(1)
m 0 n 0 q 0
The currently available LPI technologies are mainly
P (t  nTr1  mTr 2 )
based on the operation or design of a radar. The operations of
LPI radar limit the transmission time as much as possible, and 1, 0 d t  TP
where P (t ) , TP is the sub pulse width, Tr1 the PRI
prefer to use indirect identification information by detecting 0, otherwise
the specified target region with external radiation source of subpulse, Tr 2 the PRI, N the number of subpulse, Q the
searching. Lots of design methods are also adopted to achieve order of polynomial phase and M the number of pulse.
lower peak power, including the increase of accumulation M (m, n) , f (m, n) and aq (m, n) are the phase code, frequency
time and the instantaneous bandwidth, the use of high gain,
code and polynomial coefficient of the (m, n)th subpulse,
low sidelobe, high load factor, high sensitivity receiver and
the control of transmitter power, etc. respectively. Tr 2 ! NTr1 , if Tr1 ! TP the signal is pulse-hybrid,
In addition, the technologies can be extended using pulse else the signal is continuous-hybrid. The parameter relations
compression to widen the instantaneous bandwidth, of the signal model are shown in Fig. 1.
transmitting multiple beams with different frequencies
simultaneously to reduce the total scan time which limits the
accumulation time, changing the parameters of waveform
randomly to confuse the recognition and sorting of the
intelligence receiver, or copying the enemys waveform
properties to avoid to be recognized [1]. 
As one of the most important LPI technologies, the LPI Fig.1 the parameter relations of the signal model.
radar adopts a variety of complex radar waveforms, including The model includes broadband frequency agility,
broadband frequency agility, waveform agility, pulse waveform agility, parameter agility, frequency shift keying
repetition interval (PRI) and pulse transition, beam hopping, (FSK), FSK/PSK, FM/PSK and FSK/FM modulation, etc.
and complex or hybrid modulation. The primary task of the The model fully reflects the mechanism of the LPI radar, and
intelligence receiver is the detection because the signal theoretically predicts possible new LPI radars.
analysis is on the premise of it. However, the detection is
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978-1-4244-8443-0/11/$26.00 2011 IEEE

2.2 Interception Architecture receiver has a large data stream after A/D. To reduce the
burden of follow-up processors, there will be no difference
The good interception architectures for the discussed between short and long time signal decimation, leading to the
kinds of signals should be based on the properties of LPI lack of information for burst signal processing, hence we
signals. The properties of LPI could be summarized as wide cannot effectively extract the desired signal parameters.
in frequency, continuous wave in time with weak energy,
burst in time with strong energy or beam mutation resulting in 3. Architecture of the time-frequency quasi-matched
a larger dynamic range, and all of these lead to the signal intelligence receiver (TFQMR)
interception difficult. The intelligence receiver could also be
summarized as three kinds of architectures, namely the fixed In the radar receiver, the radar echo signal is matched
architecture, predictive one and adaptive one. with the transmitted signal to obtain a high gain. In the
The fixed architecture selects the focus area and intelligence receiver, the signal cannot be predicted in
frequency range for interception according to a prior of the advance about the information such as frequency and symbol,
theatre, and the signal could be targeted for interception when therefore we have no local signal to match the echo one. To
the hostile signal come into the band range of interception. this end, we propose the time-frequency quasi-matched
The interception architecture is a strong way targeted and has intelligence receiver (TFQMR) as shown in Fig.2. The
very high sensitivity, large dynamic range and specific signal TFQMR uses the most suitable spectrum for the signal
processing capability in the selected area and frequency band. detection and the most suitable time width determined by
The architecture is often with narrow bandwidth. precision of the signal processing to realize the quasi-matched
The predictive architecture intercepts signals in the interception. The TFQMR uses multiple time-bandwidth
battlefield by real-time spectrum sensing and predict the analysis units to analyse the time width and bandwidth of the
possible next parameters of the agile signal and then received signal and the units will cover the whole monitoring
configure the receiver in real-time or near real-time to receive signal frequency. For signals with different time width and
the signal matched or quasi-matched. This architecture is bandwidth, the TFQMR could use adaptive signal processing
particularly suitable for interception of the wideband algorithms, which is suitable for interception of signals with
frequency agility signal. However, the prediction strategy is agile time width or bandwidth. When the requirements for the
relatively complex which should have a strong intelligence. interesting signals of the intelligence receiver increase, we
This architecture is one of the directions of the intelligence just need to add the units to complete the high probability of
receiver. interception. The TFQMR could be realized in time,
The adaptive architecture selects the most of the regions frequency, time-frequency or other domains. The TFQMR
and some bands for interception according to a prior. The has different dilution algorithms for different pulse width
signal could be intercepted when the hostile signal come into signals and could lower the decimation factor of the burst
the band range of interception. This architecture has no signal to assure the precision of parameter estimation and
special target in general, and then the requirement for the recognition. The architecture could deal with the discussed
amount of the receivers, the required signal number to signals above.
simultaneously deal with and the flexibility for signal
processing are higher than the ones with fixed architecture.
Since the adaptive architecture has wider bandwidth, it has ADC
lower sensitivity and dynamic range.
The researches of the architectures mainly focused on
the fixed and adaptive ones because the predictive one is hard
PW Spectral
for implementation. For the fixed and adaptive ones, the analysis analysis
Filter

solution technologies include: Nyquist-Shannon sampling Time frequency analysis


using high speed A/D, channelized sampling using hybrid unit 1 Digital
filter banks [2], high speed interleaving/multiplexing data- signal
acquisition system [3], ultra-wideband A/D via signal processing
expansion [4] and non-linear spectrum compression (FPGA+
DSP)
technology [5], etc. These architectures have different
advantages in performance.
A LPI radar often uses continuous wave, interrupted
continuous wave or the spread spectrum technology to PW Spectral
Filter
analysis analysis
transmit signals with low peak power. The radar receiver can
get high processing gain by pulse compression of large time Time frequency analysis
unit N
bandwidth product signal or long accumulation time. As the
peak power of these radar signals is very low, the output Fig.2 Architecture of TFQMR.
signal to noise ratio (SNR) will become very low even for a
high sensitivity detection receiver, making the conventional 4. Implementation
radar interception of such signals very difficult or the
detection be impossible. Further, some typical burst LPI With the development of the large scale integrated
radars transmit relatively short signals in the time domain, circuit, high-speed analog-to-digital converter (A/D), ultra-
resulting in signal interception and processing difficult using large-scale field programmable gate array (FPGA) and high-
the classical interception receive. The channelized digital speed digital signal processor (DSP) have made great


progress, and the intelligence receiver has entered a new 4.1 Sample
digital field.
Although the ADC and DSP have rapid development, High-speed A/D is the first important sector of the
the work rate gap between the two still exists, and there intelligence receiver, and its performance is directly related to
would be no significant improvement in a short term. To the performance of the entire receiver. The important
alleviate this contradiction, the intelligence receiver needs an parameters related to the performance of the intelligence
additional data rate conversion system which will turn high- receiver are the resolution, effective number of bits (ENOB),
speed data streams into low-speed ones, ensuring that the maximum conversion rate and bandwidth. The dynamic range
signal information will not lose and easing pressure on the is closely related to the ENOB. In the design of circuits of
follow-up DSP. A/D, we try to reduce the mutual interference between the
Since the electromagnetic environment of the electronic digital part and the analog one. In order to reduce data latency,
warfare are more and more complex, a simple data-rate we try to keep the data lines to the equal length, and retain
conversion system is not enough to meet the actual needs, isolation around the data lines to further reduce interference.
then the enhanced digital signal processing capability has To reduce the requirement for the maximum conversion
become another way. This promotes the restructuring of the rate and the difficulty to design the anti-aliasing filter, the
FPGA, and the mainstream FPGA vendors have enhanced analog front end uses the combination of superheterodyne and
signal processing capabilities. For example, the XC5VSX95T channelized structures to mix the different channel signals
of XLINX integrates a 640 DSP48E and 8784Kb RAM, into the same intermediate frequency (IF). The IF is between
providing hard-core support for the multiply-accumulate hundreds of MHz to several GHz, and the bandwidth of IF is
operations for FFT and FIR filtering. At the same time, a the bandwidth of analog channel and the receivers
series of complex calculation cores have been developed, instantaneous processing bandwidth, which is about 1GHz.
such as the coordinate rotation digital computer (CORDIC) The basic structure of high-speed A/D is based on high speed
and direct digital synthesizer (DDS). To enhance the external interleaving/multiplexing sampling, such as NS Companys
memory expansion capability, the interface cores based on ADC083000, which is actually realized by the two low-speed
DDRI, DDRII and DDRIII have also been developed, making A/D.
the FPGA be a powerful data cache. In this system, the IF is 1.5GHz-2.5GHz, and we use the
The FPGA has become responsible for some ADC083000 by 2.7GHz undersampling which has simple
sophisticated signal processing algorithms, such as FFT architecture and the ability to receive multiple signals.
operations, FIR filter operation, and arctangent operation. The
DSP is responsible for the most complex calculations. In 4.2 Data buffer and data rate conversion
calculation, the array of the FPGA and DSP becomes a
When the input signal is digitized, the data rate is very
popular hardware structure for digital signal processing.
high. For this system, the sampling rate is 2.7GHz with 8-bits,
From a design perspective, we hope that the application
and the bus data rate and single line data rate are up to
of the DSP array will lead to increased processing power, but
21.6Gb/s and 2.7Gb/s, respectively. In order to reduce the
the actual situation is not so simple. The use of the DSP array
difficulty of receiving data, high-speed A/D would generally
will introduce computing resource allocation, data cache,
have a deserializer. The deserializer works as 1:4, and the
status updates and a series of complex logic problems, and
single line data rate is 675Mb/s, which is acceptable for the
these problems are directly related to the processing power of
major of devices. If the follow-up of the FPGA can widen the
the DSP array. In order to realize the logic management of the
data bus to 16bit and the speed of the processing clock should
DSP array, we added a control system to the intelligence
be 337.5MHz, the additional data storage is unnecessary.
receiver. The control system not only needs a rational
However, even if some modules of the FPGA can operate on
allocation of computing resources within the processor, but
this clock, it is just based on the cost of consumption of
also is responsible for data communications with peripheral
FPGA resources which is very important in signal processing.
equipment.
From the application view, the intelligence receiver would
prefer to lose little pulses, especially when the pulse is in a
high intensity, to extract more information from pulses. In
conclusion, the data storage is very necessary.
The most important high-speed data storages are the first
in first out (FIFO) and synchronous dynamic random access
memory (SDRAM).
The FIFO is a data buffer, and the difference between
normal memories is that there is no external line for reading
and writing. The FIFO is easy to use with constrains that the
data first in must be read first. As the rapid development of
microelectronic technology, the capacity of a new generation
Fig.3 The top view of the PCB of TFQMR. of the FIFO chip increases with smaller and smaller size.
We have implemented the TFQMR using high speed As a new large scale integrated circuit with flexible,
A/D, FPGA and DSP. The top view of the printed circuit convenient and efficient characteristics, the FIFO is gradually
board (PCB) is shown in Fig.3. The PCB of the TFQMR and widely used in high speed data acquisition, processing,
includes the sample, data rate conversion, time frequency transmission and multi-core processing system. The
quasi-match, central control and the follow-up signal
processing sectors.


72T36135M of Integrated Device Technology (IDT) works at the detection results of time-frequency quasi-matched units.
the clock of 225MHz, 36bit, and 18-Mbits cache. The central control will evaluate the processing priority based
The synchronization of the SDRAM is that the SDRAM on the time of arrival (TOA) of pulses and flags of the buffer.
needs to synchronize the clock to data transmission and send Moreover, the modifications of TOA and pulse width are also
control commands. The dynamic is to constantly refresh the finished in the central control. The central control receives the
storage array to ensure data is not lost. The random means data from the buffer with slow data rate, the data from the
that the data is not linear sequence storage, but could be first unit and the second unit. We can improve the ability of
freedom to read and write in the specified address. short time signal processing. In addition, the central control is
In this system, if we use the FIFO as a buffer, there are also responsible for the communication between DSPs and
at least four parallel FIFOs whose clock is 168.75MHz, bit other devices.
width is 128-bits and the cache capacity is 72-Mbits; while if
we use the DDR as a buffer, there are at least four parallel 4.5 Follow-up signal processing
DDR SDRAMs whose clock is also 168.75MHz, bit width is
64bits because the SDRAM transfers data both edges, cache The follow-up signal processing technologies include the
capacity is 2048Mbits. In electronic warfare, the pulse width intra-pulse analysis and signal deinterleaving. The first part
of a LPI radar signal may be as long as a few hundred consists of automatic modulation classification and parameter
microseconds. We set the pulse width to be 100s and the estimation of radar signals to give the pulse description word
data size of a single pulse to be 2Mbits. If we adopt the FIFO (PDW) including TOA, direction of arrival (DOA), carrier
as a buffer, we can store up to 36 pulses, which is difficult to frequency (CF), pulse width (PW), pulse amplitude (PA) and
meet the actual requirements. 1024 pulses can be stored if we intra-pulse modulation (PM). The signal deinterleaving will
use the DDR, which is enough for the intelligence receiver. In provide the antenna scan period (ASP) and pulse repetition
addition, as the DDR is a single port RAM, the data could be interval (PRI). The final result is the emitter description word
implemented using a ping pong buffer to achieve independent (EDW). These are implemented by the FPGA and DSP.
reading and writing, and the buffer capacity will be increased
twice. Thus, the DDR is suitable for high-speed data buffer. 5. Conclusions
In this paper, we have presented an architecture denoted
4.3 Time-frequency quasi-matched
as time-frequency quasi-matched for the intelligence receiver.
The time-frequency quasi-matched architecture uses This structure is suitable for interception of most LPI radar
several time-bandwidth analysis units to analyse the received signals, especially for the agile signals widely used in
signals, and we used three units in this system. Here, we electronic warfare. We also showed the implementation of the
adopt the efficient implementation architecture which is based architecture and its key technologies. This architecture will be
on the poly-phase filter bank and IDFT structure. We have useful for the modern electronic warfare.
realized the channelized frequency by two FPGAs.
The time-frequency quasi-matched architecture consists References
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