Course Description
Basic theory, techniques for testing digital circuits and systems. Design techniques for fault
tolerant and early diagnosable systems. Test generation for combinational and sequential logic
circuits, checking experiments. Gate level fault simulation, and its application to diagnosis.
Design techniques using static and dynamic redundancy for reliable systems. Design for
testability (DFT) including full and partial internal scan and boundary Scan. Memory test, delay
test and at speed testing. Built In Self Test (LBIST, MBIST). Reliability basics its relation
toaccelerated testing.
Prerequisites
Students taking this course should understand the material in ECE 620 or consent of the
instructor.
I. Introduction to testing
A.Basic Concepts
Diagnosis
Reliability
Fault Tolerance
B.Fault Models
B.Algebraic Methods
Boolean Difference
C.Path Sensitization Methods (Algorithmic test procedures)
D-algorithm
-FAN, PODEM Algorithm
Critical path Test
ASSESSMENT METHODS
Agrawal, V.D. and Seth, S.C., Test generation for VLSI chips, IEEE Computer Society Press, 1988.
Butler, Kenneth M., Assessing Fault Model and Test Quality, Kluwer Academic Publishers, 1992
Cheng, K.T. and Agrawal, V.D., Unified Methods for VLSI Simulation and Test Generation, Kluwer
Academic Publishers, 1989.
Eichelberger, Edward B., ed., Structured Logic Testing, Prentice Hall, 1991
Fujiwara, Hideo, Logic Testing and Design for Testability, MIT Press, 1985
Hnatek, Eugene R., Digital Integrated Circuit Testing from a Quality Perpective (New York: Van
Nostrand Reinhold, 1993)
Miczo, Alexander, Digital Logic Testing and Simulation, Harper & Row, 1986
Rajsuman, Rochit, Digital Hardware Testing (Boston: Artech House, 1992)
Tsui, Frank, LSI/VLSI Testability Design, McGraw-Hill, New York, 1987
Wang, Francis, Digital Circuit Testing (San Diego: Academic Press, 1991)
Bleeker, Harry, van den Eijden, Peter, de Jong, Frans, Boundary Scan Test. A Practical Approach,
Kluwer Academic Publishers, 1993, ISBN 0-7623-9296-5
Maunder, Colin, The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1991,
ISBN 0-201-56513-7
Bardell, P.H., McAnney, W.H., Savir, J., Built-In Test for VLSI: Pseudorandom Techniques, Wiley
Interscience, 1987
Goessel, M., Graf, S., Error Detection Circuits, McGraw-Hill, ISBN 0-07-707438-6
IDDQ Testing
The Journal of Electronic Testing (JETTA), Vol.3, No.4, Dec. 1992 (Special Issue devoted to IDDQ
testing with good tutorial material and the most recent papers.)
Gulati, Ravi, et.al., IDDQ Testing of VLSI Circuits, hardcover version of the JETTA issue, Kluwer
Academic Publishers.
Maliya, Y. and Rajsuman, R., Bridging Faults and IDDQ Testing, IEEE Computer Society Press
Technology Series (Order number 3215-05), Library of Congress Number 92-30950, IEEE Catalog
number EH0357-4, ISBN 0-8186-3215-1
1. Memory Testing
Van de Goor, A., Testing Semiconductor Memories, Willey, ISBN 0-471-92586-1
2. SystemTesting
Simpson, William R., and Sheppard, W., System Test and Diagnosis, Kluwer Academic Publishers,
1994, ISBN 0-7923-9475-5
3. TestIntegration
Parker, Kenneth, Integrating Design and Test: Using CAE tools for ATE Programming, IEEE order
number EH0261-8, IEEE Service Center
4. TransistorLevelModeling
Rajsuman, R., Digital Hardware Testing, Transistor-Level Fault Modeling and Testing, Artech House,
ISBN 0-89006-580-2
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