Active Source Current Filtering to Minimize the

DC-Link Capacitor in Switched Reluctance Drives

Annegret Klein-Hessling, Bernhard Burkhart, Rik W. De Doncker
Institute for Power Electronics and Electrical Drives (ISEA), RWTH Aachen University
Jaegerstrasse 17/19, 52066 Aachen, Germany
post@isea.rwth-aachen.de http://www.isea.rwth-aachen.de

AbstractSwitched reluctance machines receive increased at-
tention by the automotive industry because of their cost efficiency.
However, the comparatively larger inverter is a disadvantage of
this machine type. This paper evaluates the effects of the usage
of a dc-dc converter to reduce the size of the dc-link capacitor by
active filtering of the source current. The active filter is compared
to a passive filter. Besides, the influence of a variable dc-link
voltage level on the machine is investigated.
I. I NTRODUCTION
Switched reluctance machines (SRMs) need a comparatively
large dc-link capacitor to smoothen the dc-link voltage due
to the high amount of magnetization energy that oscillates
between the dc-link and the machine [1]. A high ripple on the
dc-link voltage is unwanted to avoid the risk of over voltage
across the semiconductor. A ripple on the dc-link voltage also
results in a source current ripple, if the dc-link is directly
connected to a voltage source (e.g. a battery). This current
ripple produces ohmic losses on the internal resistance of the
source. For a 20 kW-SRM in an automotive application these
losses can reach a few hundreds watts.
A large dc-link capacitor increases the size, weight and
prize of the SRM inverter compared to inverters for conven-
tional three phase drives based on an induction machine or
synchronous machine. Recent publications recommend phase
switching techniques to minimize the size of the dc-link ca-
pacitor [1], [2]. These switching techniques aim to commutate
the magnetization energy stored in one phase to the next active
phase without buffering it in the dc-link capacitor. However
the switching techniques assume an overlap between the SRM
phases. This assumption is only fulfilled by SRMs with at least
three phases. Additionally, the current in the SRM has to be
still active controllable. Therefore, these switching techniques
are not applicable for a two-phase SRM and/or an SRM in
single-pules operation.
[2] additionally proposes a passive input filter to reduce
the ripple on the source current. The presented passive input
filter consists of an inductance LDC and a dc-link capacitance
CDC .
The active filter proposed in this paper is a bidirectional dc-
dc boost converter. The converter switches allow to actively
control the current between the dc-link and the voltage source
and, therefore, the switches are reducing the ripple on the
source current.
In addition, the use of a boost converter might have ad-
vantages because it is able to eliminate the effects of a
dc-link voltage level variation due to the battery state of
charge (SOC) [3]. Common 400 V automotive batteries suffer
a voltage drop of around 100 V in the discharge state. On
SRMs in single-pulse operation this might have a considerable
effect on the machine efficiency.
II. ACTIVE F ILTERING U SING A DC-DC C ONVERTER
An equivalent circuit model of the proposed filter topology,
the battery, the cable and the SRM inverter is shown in Fig. 1.
The battery is modeled as an ideal voltage source ubat and
an internal resistance Ri,bat . The cable which connects the
battery with the inverter is assumed as series connection of a
resistance Rcable and an inductance Lcable . The SRM inverter
consists of a dc-link capacitance CDC and an asymmetric half
bridge with the switches S1 and S2 .
The dc-dc converter consists of two switches SDC,1 and
SDC,2 , an inductance LDC and an input capacitance Cin . The
depicted dc-dc converter in Fig. 1 is a boost converter, hence
uin < uDC . To allow the SRM being operated in motor and
generator mode the dc-dc converter has to be bidirectional.
When the SRM operates as a motor the current through
the inductor (iL > 0) is controlled with the switch SDC,1 .
When the SRM operates as a generator the current (iL < 0)
is controllable with the switch SDC,2 . Hence, the energy
flow between the battery and the dc-link capacitor can be
controlled.
The aim of the boost converter is to supply the SRM
converter with a reference dc-link voltage uDC and simulta-
Fig. 1. Equivalent circuit of SRM with proposed active filter
neously filter the source current ibat . Filtering of the source
current means holding the current through the inductor iL
on a nearly constant level and therefore suppress greater
oscillation on the source current. This can be achieved by
controlling the average dc-link voltage uDC instead of the
instantaneous dc-link voltage uDC . In a stationary operating
point the instantaneous dc-link voltage then is periodic with
the electric frequency of the SRM times the number of SRM
phases.
The control of the dc-link voltage is shown in Fig. 2. At
the start of each voltage period the average reference dc-link
voltage uDC is compared with the actual average voltage of the
last period uDC . The difference is the input to a PI-controller
which provides the reference value for the inductor current
iL . Afterwards a current controller determines the switching
signals for the boost converter.
The current through the inductor can either be controlled by
hysteresis control or pulse-width modulation (PWM). Figure 3
depicts the two approaches. For hysteresis control only the
instantaneous current iL is required. Dependent on the current
the states of the switches are chosen. Therefore the switching
frequency is not constant. The maximal switching frequency
depends on the hysteresis width I, the boost inductance LDC
and the voltages uDC and uin .
For the PWM approach before each PWM period T the duty
cycle d has to be calculated. The current through an inductor is
determined by the integration of the voltage across it divided
by its inductance:
Zt
1
iL (t) = iL (t0 ) + uL ( ) d
LDC
t0
With this equation the predicted current in the next discrete
PWM step k + 1 can be determined.
iL (k + 1)
dT (1 d)T
iL (k) + uin (k) + (uin (k) uDC (k)) (2)
LDC LDC
Fig. 2. Control of average DC-link voltage with active filter
(a) Hysteresis control (b) Center aligned PWM control
Fig. 3. Approaches for current controller
For simplification voltage drops across the switches and
diodes are not considered in the shown equation but used in
the controller. The duty cycle for in the next PWM step k + 1
can be determined by solving the equation for d. As mentioned
before, only one switch of the bidirectional dc-dc converter is
controlled. For a positive current iL the duty cycle d is > 0
and is applied on SDC,1 . Vice versa, in the case of a negative
current the switch SDC,2 has to be used and the calculated
duty cycle is < 0.
The usage of the measured voltages uin (k) and udc (k) at
the end of the last PWM step k is another simplification. It
assumes that the voltages between two PWM steps do not vary.
This does not necessary apply for the dc-link voltage. The
difference between udc (k) and udc (k + 1) depends on CDC
and the length of the PWM period T . To improve the PWM
current controller the voltage udc (k+1) can be predicted. With
this an average voltage within the PWM step can be calculated
and used in (2).
The PWM current controller provides a constant switching
frequency. At the same time compared to the hysteresis
approach the measurement and calculation effort for the in-
stantaneous values is higher. Additionally, the ripple on the
current is not constant.
To reduce the current through the inductor and increase
the effective total switching frequency it is possible to use
an interleaved dc-dc converter [4]. The interleaved dc-dc
converter consists of multiple single dc-dc converter connected
in parallel as depicted in Fig. 4.
(1) For an interleaved dc-dc converter the PWM current control
approach is recommended. When phase shifting the PWM
periods of each individual phase one to each other, the total
switching frequency of the converter can be increased by
keeping the switching frequency of each phase unchanged. In
contrast, when applying a hysteresis current controller to each
phase, due to the variable switching frequency, the positive and
negative peaks of the single phases do not necessarily overlap
each other.
Fig. 4. Equivalent circuit of active filter with interleaved dc-dc converter
 III. S IMULATION R ESULTS
For the comparison of the different topologies simulations
are carried out using MATLAB Simulink [5] coupled with
PLECS [6]. The SRM is modeled by look-up tables obtained
from a stationary 2D finite element analysis (FEA)
A 2-phase SRM with rated speed of 7500 rpm at 22 kW
for a range extender application is used. Therefore, the SRM
operates as a generator and the source current is negative. The
rated dc-link voltage of the SRM is 300 V. At rated speed the
SRM operates in single-pulse operation [7].
The active filter is compared to two topologies: a con-
ventional dc-link capacitor and a passive filter as presented
in [2]. The passive filter consists of a dc-link capacitor and an
inductor in series with the cable connecting the battery and
the SRM inverter. For all topologies a real cable and a battery
with an internal resistance are modeled.
The comparison of the resulting battery currents ibat and
the dc-link voltages udc for the rated operation point of the
SRM is shown in Fig. 5. It depicts the simulation results for
two dc-link configurations: reduced capacitance (Cdc = 1 mF)
and needed capacitance (Cdc = 5 mF). Only the larger dc-link
capacitance suppresses the battery current reversal. The ripple
on the current however is still around 75 %.
The passive filter is able to reduce the current ripple with
the reduced capacitance of Cdc = 1 mF to the same level as
a 5 mF dc-link capacitance without any filter. The active filter
decreases the current ripple on the battery current even further.
In this simulation an active filter with two dc-link phases is
used. In this case the dc-dc converter and the SRM inverter
can be build up using two B6 modules. For the dc-dc converter
the PWM current control is applied.
The comparison of the dc-link voltages shows that only the
topology with the big capacitance reduces the ripple to about
4 % of the average voltage uDC = 310 V. All topologies with
50
Current ibat in A
0 no filter:
50
100
150
0 90 180 270 360
Voltage uDC in V
350
325
300
275
0 90 180 270 360
Electrical Position in el
Fig. 5. Influence of different filters on source current and dc-link voltage at
mechanical input power Pmech = 22 kw and speed n = 7500 rpm
a dc-link capacitance of Cdc = 1 mF experience a similar
voltage ripple of approximately 20 %. Due to the 2-phase SRM
the ripple appears twice per electric period of the SRM.
Since the active filter is a dc-dc boost converter the average
dc-link voltage of the active filter (uDC = 335 V) is higher
than the voltage of the other topologies. The filter ability of
the dc-dc converter can only be used if udc > uin . Otherwise,
the diode of switch SDC,1 conducts and the current iL is no
longer actively controllable.
The ripple on the dc-link voltage has only a slight influence
on the SRM behavior. Due to the higher voltage at the
unaligned position ( = 180 el) the phase can be magnetized
a little faster. The influence of the average dc-link voltage level
on the SRM behavior will be discussed in section III.B.
A. Influence of Different Operating Points
The passive filter is designed for one specific operating
point. In this paper for a better comparison between the
topologies the passive filter is designed for the rated operating
point of the SRM. In [2] a design for the worst operating
point is recommended. For the observed SRM in this paper
this operating point would be at low speed and high power.
The design for this point would result in a big value for the
inductance or the capacitance. A big inductance limits the
dynamic behavior of the SRM, e.g. during speed up. Fast
changes of the SRM load are no longer possible because of
the slower current gradient (diL/dt 1/LDC ).
A comparison of the resulting battery current ibat and the
dc-link voltage udc for two different speeds for the passive and
the active filter is displayed in Fig. 6. The mechanical input
power of the switched reluctance generator for all operating
points is 22 kW. It can be seen, that in case of the passive
filter the current ripple increases with decreasing speed. At
4500 rpm the peak current reaches up to 0 A while the peak-
to-peak ripple is about 200 % of the average source current.
0
Current ibat in A
CDC = 1 mF 50
no filter: 100
CDC = 5 mF
150 passive filter: 4500 rpm
passive filter: 7500 rpm
passive filter: 0 90
CDC = 1 mF active filter: 4500 rpm
LDC = 100 H active filter: 7500 rpm
Voltage uDC in V
350
active filter:
CDC = 1 mF
LDC = 100 H 300
Cin = 0.1 mF
250
0 90 180 270 360
Electrical Position in el
Fig. 6. Influence of variable speed on active and passive current filter at
mechanical input power Pmech = 22 kW
 The same simulations are carried out for the active filter.
In this case the different operating points have no influence
on the ripple of the battery current. The battery current stays
nearly constant for both speeds. The ripple in the dc-link
voltage is affected similar for both filters by the different
operating points. Therefore, the big advantage of the active
filter compared to the passive filter is, that its behavior and
filter capability is independent of the operation point.
B. Influence of DC-Link Voltage on SRM
Besides filtering the source current, the dc-dc converter can
be used to adjust the dc-link voltage level. The average dc-link
voltage has an influence on the phase current iph and the phase
flux linkage ph of the SRM. Both values are important for
the losses occurring in the SRM and, therefore, the efficiency
of the drive system.
Figure 7 shows the effect of the different dc-link voltages
on the trajectories of phase current and phase flux-linkage for
one electrical period at the rated operating point (7500 rpm,
22 kW). The SRM is rated for a battery with a voltage of 300 V.
The minimum voltage at a low SOC level is assumed to be
200 V. 400 V is assumed to be the maximum boosted voltage
of the dc-dc converter. Each operating point is optimized for
the best efficiency as presented in [9]. The gradient of the flux
linkage is proportional to the dc-link voltage. Therefore, the
conduction time per period increases with decreasing dc-link
voltages. The efficiency optimization of the parameters results
in an increased free-wheeling time with increasing the dc-link
voltages.
Due to the efficiency optimization the peak value of the
phase currents remain nearly constant for the different voltage
levels. The rms value of the phase current however increases
for decreased dc-link voltages, as a longer conduction time is
required.
400
Current iph in A
300 udc = 400 V
udc = 300 V
200 udc = 200 V
100
0
0 90 180
Flux Linkage ph in Vs
0.1
0.05
0
0 90 180
Electrical Position in el
Fig. 7. Phase current and flux-linkage trajectories for different dc-link voltages
at mechanical input power Pmech = 22 kw and 7500 rpm
The SRM losses are determined by a coupled 2D-FEA sim-
ulation using MATLAB Simulink [5] and FLUX 2D [10]. The
simulation considers copper losses Pcu including eddy current
losses in the windings [8] and iron losses Pfe in the rotor
and stator [11]. Due to the non-sinusoidal flux waveforms for
the iron loss calculation the improved generalized Steinmetz
equation (iGSE) is used [12].
The losses in the semiconductor of the SRM inverter Pinv
are calculated according to data sheets provided by the manu-
facturer. Switching and conduction losses in the switches and
diodes are considered. The modeled SRM inverter is based on
HybridPACK Light IGBT modules provided by Infineon [13].
The resulting total losses of the SRM and the SRM inverter
for the rated operating point at a mechanical input power of
22 kW and 7500 rpm are shown in Fig. 8. The copper and
the inverter losses are strongly dependent on the rms current
and, therefore, are reduced by higher voltages. The iron losses
depend on the peak flux-linkage and the gradient of the flux
linkage d/dt. According to the observation from Fig. 7 the
iron losses increase with increased dc-link voltage level.
In total the overall losses decrease with an increasing dc-
link voltage level. Between 200 V and 300 V the efficiency
improves by 1.6 % and stays nearly constant up to 400 V
when exceeding 300 V. If only the SRM and its inverter are
considered it is recommended to operate the SRM at a dc-link
voltage of 300 V or higher.
C. Influence of DC-Link Voltage on DC-DC Converter
Similar to the SRM and its inverter the efficiency of the
dc-dc converter also depends on the choice of the average dc-
link voltage. As visible in (2) the current through the inductor
depends on the input voltage uin and the difference between
the input voltage and the dc-link voltage u = uin uDC .
The inductor current and dc-link voltage trajectories for
a battery voltage of ubat = 200 V at 22 kW and 7500 rpm
for different levels of average dc-link voltages are shown in
Fig. 9. The PWM current control approach with a switching
frequency f = 15 kHz for all cases is chosen.
2000 Pinv
Pfe
270 360 1500
Losses P in W
Pcu
1000
500
0
270 360 200 250 300 350 400
DC-Link Voltage UDC in V
Fig. 8. Influence of different dc-link voltage on SRM losses
 The average inductor current iL is independent of the
average dc-link voltage. It is determined by the battery voltage,
the mechanical power of the SRM and the number of dc-
dc converter phases. The ripple on the current increases with
the voltage difference u because the gradient diL/dt during
the current decreasing time is proportional to this difference.
The gradient of the current during the increasing time is
proportional to the input voltage (eq. (2)), hence this gradient
is constant for all cases.
Figure 9 also shows that the ripple on the dc-link voltage
depends on the average dc-link voltage level. The ripple
decreases at increased voltage levels.
The resulting inductors losses PL as well as the losses in
the IGBTs and diodes of the dc-dc converter are depicted in
Fig. 10. The semiconductor losses are separated into switching
losses Psw and conduction losses Pcond . The switching losses
of the IGBTs depend on the switching frequency, the voltage
across the device and the instantaneous current during turn-
on and turn-off. The switching frequency is the same for
all investigated average dc-link voltage levels. The negative
current peaks and the voltage difference between input and
dc-link voltage increase for higher average dc-link voltages
(Fig 9). Therefore also the switching losses of the IGBTs
increase.
The conduction losses are mainly affected by the rms
current through the semiconductors. The duty cycle determines
the ratio of the period in which the switch is closed and current
is conducted through it. The average absolute duty cycle |d| per
electrical period decreases with increasing the average dc-link
voltage. Therefore, according to the duty cycle the conduction
losses of the IGBT decrease while the conduction losses of
the diode increase for an increasing dc-link voltage. The total
semiconductor losses of the inverter increase for an increased
dc-link voltage.
Similar to the losses in an SRM the losses occurring in
Current iL in A
25
50
75
udc
udc
0 90 180
udc
udc
Voltage uDC in V
400
300
200
0 90 180 270
Electrical Position in el
Fig. 9. Inductor current trajectories for different average dc-link voltages at
ubat = 200 V
the inductors consist of iron losses and copper losses. For
the simulation, inductors with ferrite cores and litz wire are
considered. The flux density in the inductor is calculated
with an analytical approach. Due to the non-sinusoidal current
waveform again the improved generalized Steinmetz equation
(iGSE) is used [12]. For the copper loss calculation of the
windings eddy currents are neglected because litz wire is
used. For the considered operating points the copper losses
clearly dominate the iron losses. Therefore, the inductor losses
increase only slightly with the increasing average dc-link
voltage as the rms inductor current slightly increases with the
higher current ripple.
In total, the losses in the dc-dc converter are mainly de-
termined by the switching losses. The switching losses also
depend on the switching frequency of the converter. Figure 11
shows this dependency for a battery voltage of 200 V and
an average dc-link voltage of 235 V. This average dc-link
voltage is the minimum value for which at ubat = 200 V
the necessary condition uDC > uin is always fulfilled. At
around 90 el and 270 el the voltage difference u becomes
nearly zero. Therefore, the gradient of the inductor current
becomes also very small. This results in reduced switching
losses. Additionally, a decreased switching frequency reduces
the switching losses. The reduction of the switching frequency
is limited by the saturation of the inductor at the negative peak
current.
D. Total Efficiency of the Electric Drive Train
At a switching frequency of 6 kHz the efficiency of the
dc-dc converter is above 99 %. Figure 12 presents the total
losses of the electric drive train comprising a dc-dc converter,
a machine inverter and an SRM (solid lines). For each set of
voltage levels (ubat , udc ) the switching frequency is adapted
to minimize the dc-dc converter losses without operating the
inductors in saturation. Additionally, the occurring losses in
the drive train with a big capacitor and without the use of
the dc-dc converter are shown in Fig. 12 (dashed line). The
400
Psw,IGBT
Psw,diode
= 400 V 300
PL
Losses P in W
= 350 V
Pcond,diode
= 300 V
200 Pcond,IGBT
= 250 V
100
0
250 300 350 400
360
Average DC-Link Voltage uDC in V
Fig. 10. Semiconductor losses for different average dc-link voltages at
ubat = 200 V
 Current iL in A
A range extender in an electric car is mostly operated when
25 the SOC and the battery voltage are at low level. Therefore, it
50
can be assumed that the system efficiency is not reduced with
the additional dc-dc converter.
75
IV. C ONCLUSION
0 90 180 270 360 The investigations in this paper have shown that by using
Electrical Position in el a dc-dc converter it is possible to actively filter the source
400
current. By this measure the size of the dc-link capacitor can
f = 6 kHz
be reduced by 80 %. Contrary to the behavior of a passive
f = 9 kHz
filter, the operating point of the SRM has no effect on the
f = 12 kHz
300 filter quality. Additionally, the investigations have shown that
f = 15 kHz
Losses P in W

the ability of the dc-dc converter to adjust the dc-link voltage

independent of the state of charge of the battery improves the
200 Psw,IGBT
efficiency of the switched reluctance machine and its inverter.
Psw,diode The total efficiency of the electric drive train, therefore,
100 PL remains nearly unchanged despite the extra losses in the dc-dc
Pcond,diode
converter.

0 Pcond,IGBT ACKNOWLEDGMENTS
6 9 12 15 The research was funded by the German Federal Ministry
Switching Frequency f in kHz of Economic Affairs and Energy (BMWi) within the public
project HiREX (FKZ: 01MY14003A). The work was addition-
Fig. 11. Inductor current and total converter losses for different switching ally supported by the German Research Foundation (DFG) as
frequencies at ubat = 200 V and udc = 235 V
part of the post graduate program mobilEM (GRK 1856).
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Average DC-Link Voltage uDC in V
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