Chapter11 PDF

Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Arithmetic Circuits
January, 2003
1
Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
A Generic Digital Processor
MEM ORY
INPUT-OUTPUT
CONTROL
DATAPATH
2
Digital
Arithmetic Circuits
Building Blocks for Digital Architectures
Arithmetic unit
- Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
3
Digital
Arithmetic Circuits
An Intel Microprocessor
9-1 Mux
5-1 Mux
a g64
CARRYGEN
node1
SUMSEL
sum sumb
REG
ck1 to Cache
9-1 Mux
2-1 Mux SUMGEN s0

+ LU s1
b
LU : Logical
Unit
1000um
Itanium has 6 integer execution units like this
4
Digital
Arithmetic Circuits
Bit-Sliced Design
Control
Bit 3
Data-Out
Multiplexer
Bit 2
Data-In
Register
Adder
Shifter
Bit 1
Bit 0
Tile identical processing elements

5
Digital
Arithmetic Circuits
Bit-Sliced Datapath
From register files / Cache / Bypass
Multiplexers
Shifter
Adder stage 1
Wiring
Loopback Bus
Loopback Bus
Loopback Bus
Adder stage 2
Wiring
Bit slice 63
Bit slice 2
Bit slice 1
Bit slice 0
Adder stage 3
Sum Select
To register files / Cache
6
Digital
Arithmetic Circuits
Itanium Integer Datapath
Fetzer, Orton, ISSCC02 7

Digital
EE141 Integrated Circuits 2nd
Arithmetic Circuits
Adders
8
Digital
Arithmetic Circuits
Full-Adder
A B
Cin Full Cout

adder
Sum
9
Digital
Arithmetic Circuits
The Binary Adder
A B
Cin Full Cout

adder
Sum
S = A B Ci
= ABC i + ABC i + ABCi + ABCi

C o = AB + BCi + ACi
10
Digital
Arithmetic Circuits
Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B

Generate (G) = AB
Propagate (P) = A B
Delete = A B
Can also derive expressions for S and Co based on D and P

Note that we will be sometimes using an alternate definition for
Propagate (P) = A + B
11
Digital
Arithmetic Circuits
Complimentary Static CMOS Full Adder
VDD
VDD
Ci A B
A B
A
B
Ci B
VDD
A
X
Ci
Ci A S
Ci
A B B VDD
A B Ci A
Co B
28 Transistors
12
Digital
Arithmetic Circuits
A Better Structure: The Mirror Adder
VDD
VDD VDD A
A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A
24 transistors
13
Digital
Arithmetic Circuits
Mirror Adder
Stick Diagram
VDD
A B Ci B A Ci Co Ci A B
Co
GND
14
Digital
Arithmetic Circuits
The Mirror Adder
The NMOS and PMOS chains are completely symmetrical.
A maximum of two series transistors can be observed in the carry-
generation circuitry.
When laying out the cell, the most critical issue is the minimization
of the capacitance at node Co. The reduction of the diffusion
capacitances is particularly important.
The capacitance at node Co is composed of four diffusion
capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell .
The transistors connected to Ci are placed closest to the output.
Only the transistors in the carry stage have to be optimized for
optimal speed. All transistors in the sum stage can be minimal
size.
15
Digital
Arithmetic Circuits
Transmission Gate Full Adder
P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci
A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P
16
Digital
Arithmetic Circuits
One-phase dynamic CMOS adder
17
Digital
Arithmetic Circuits
18
Digital
Arithmetic Circuits
19
Digital
Arithmetic Circuits
The Ripple-Carry Adder
A0 B0 A1 B1 A2 B2 A3 B3
Ci,0 Co,0 Co,1 Co,2 Co,3

FA FA FA FA
(= Ci,1)
S0 S1 S2 S3
Worst case delay linear with the number of bits

td = O(N)
tadder = (N-1)tcarry + tsum
Goal: Make the fastest possible carry path circuit
20
Digital
Arithmetic Circuits
Inversion Property
A B A B
Ci FA Co Ci FA Co
S S
21
Digital
Arithmetic Circuits
Minimize Critical Path by Reducing Inverting Stages
Even cell Odd cell
A0 B0 A1 B1 A2 B2 A3 B3
Ci,0 Co,0 Co,1 Co,2 Co,3

FA FA FA FA
S0 S1 S2 S3
Exploit Inversion Property
22
Digital
Arithmetic Circuits
Carry Look-Ahead Adders
23
Digital
Arithmetic Circuits
Carry-Lookahead Adders
24
Digital
Arithmetic Circuits
Carry-Lookahead Adders
25
Digital
Arithmetic Circuits
Look-Ahead: Topology
Expanding Lookahead equations: VDD
C o, k = Gk + Pk (Gk 1 + Pk 1 Co , k 2 ) G3
G2
G1
All the way:
G0
C o, k = Gk + Pk ( Gk 1 + P k 1( + P1 ( G0 + P0 Ci , 0 ) ) )
Ci,0
Co,3
P0
P1
P2
P3
26
Digital
Arithmetic Circuits
Manchester Carry Chain
VDD
Pi
VDD
Pi
Ci Co
Gi
Co Gi
Ci
Di
Pi
27
Digital
Arithmetic Circuits
VDD

P0 P1 P2 P3
C3
Ci,0
G0 G1 G2 G3
C0 C1 C2 C3
28
Digital
Arithmetic Circuits
Stick Diagram
Propagate/Generate Row
VDD
Pi Gi Pi + 1 Gi + 1
Ci - 1 Ci Ci + 1
GND
Inverter/Sum Row
29
Digital
Arithmetic Circuits
Carry-Bypass Adder
P0 G1 P0 G1 P2 G2 P3 G3 Also called
Carry-Skip
Ci,0 C o,0 C o,1 Co,2 Co,3
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
Multiplexer
FA FA FA FA
Co,3
Idea: If (P0 and P1 and P2 and P3 = 1)

then Co3 = C0, else kill or generate.
30
Digital
Arithmetic Circuits
Carry-Bypass Adder (cont.)
Bit 03 Bit 47 Bit 811 Bit 1215
Setup tsetup Setup Setup Setup
tbypass
Carry Carry Carry Carry

propagation propagation propagation propagation
Sum Sum Sum tsum Sum
M bits
tadder = tsetup + Mtcarry + (N/M 1)tbypass + (M 1)tcarry + tsum
31
Digital
Arithmetic Circuits
Carry Ripple versus Carry Bypass
tp
ripple adder
bypass adder
4..8 N
32
Digital
Arithmetic Circuits
Carry-Select Adder
Setup
P,G
"0" "0" Carry Propagation
"1" "1" Carry Propagation
Co,k-1 Multiplexer C o,k+ 3
Carry Vector
Sum Generation
33
Digital
Arithmetic Circuits
Carry Select Adder: Critical Path
Bit 03 Bit 47 Bit 811 Bit 1215
Setup Setup Setup Setup
0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry
1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry
Multiplexer Multiplexer Multiplexer Multiplexer

Ci,0 Co,3 Co,7 Co,11 Co,15
Sum Generation Sum Generation Sum Generation Sum Generation

S03 S47 S811 S1215
34
Digital
Arithmetic Circuits
Linear Carry Select
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
(1)
"0" Carry "0" Carry "0" Carry "0" Carry

"0" "0" "0" "0"
(1)

"1" "1" "1" "1"
(5) (5) (5) (5) (5)
(6) (7) (8)
Multiplexer Multiplexer Multiplexer Multiplexer
Ci,0
(9)
Sum Generation Sum Generation Sum Generation Sum Generation
S0-3 S 4 -7 S8-11 S 1 2-15 (10)
35
Digital
Arithmetic Circuits
Square Root Carry Select
Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19

(1)

"0" "0" "0" "0"
(1)

"1" "1" "1" "1"
(3) (3) (4) (5) (6) (7)
(4) (5) (6) (7)
Multiplexer Multiplexer Multiplexer Multiplexer Mux
Ci,0
(8)
Sum Generation Sum Generation Sum Generation Sum Generation Sum
S0-1 S2-4 S5-8 S9-13 S14-19 (9)
36
Digital
Arithmetic Circuits
Adder Delays - Comparison
50
tp (in unit delays)

40 Ripple adder
30
Linear select
20
10
Square root select
0
0 20 40 60
N
37
Digital
Arithmetic Circuits
O Operator
Definizione
38
Digital
Arithmetic Circuits
Properties of the O operator
39
Digital
Arithmetic Circuits
Properties of the O operator
40
Digital
Arithmetic Circuits
Group Generate and Propagate
41
Digital
Arithmetic Circuits
42
Digital
Arithmetic Circuits
43
Digital
Arithmetic Circuits
Look-Ahead - Basic Idea
A0, B0 A1, B1 AN-1, BN-1
Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1
S0 S1 SN-1
C o, k = f (A k, B k, Co , k 1 ) = Gk + P k Co , k 1
44
Digital
Arithmetic Circuits
Logarithmic Look-Ahead Adder
A0 F
A1 A2 A3 A4 A5 A6 A7
A0
tp N
A1
A2
A3
F
A4
A5
A6 tp log2(N)
A7
45
Digital
Arithmetic Circuits
Brent-Kung BLC adder
46
Digital
Arithmetic Circuits
Folding of the inverse tree
47
Digital
Arithmetic Circuits
Folding the inverse tree
48
Digital
Arithmetic Circuits
Dense tree with minimum fan-out
49
Digital
Arithmetic Circuits
Dense tree with simple connections
50
Digital
Arithmetic Circuits
Carry Lookahead Trees
Co , 0 = G0 + P0 Ci , 0
C o, 1 = G1 + P1 G 0 + P1 P0 Ci, 0
C o, 2 = G2 + P2 G 1 + P2 P1 G0 + P2 P1 P0 C i, 0
= ( G 2 + P2 G1) + ( P2 P1 ) ( G 0 + P0 Ci , 0 ) = G 2:1 + P2:1 C o, 0
Can continue building the tree hierarchically.
51
Digital
Arithmetic Circuits
Digital
(A0, B0) S0
(A1, B1) S1
(A2, B2) S2
(A3, B3) S3

(A4, B4) S4
Tree Adders
(A5, B5) S5
(A6, B6) S6
(A7, B7) S7
(A8, B8) S8
16-bit radix-2 Kogge-Stone tree

(A9, B9) S9
(A10, B10) S10
(A11, B11) S11
(A12, B12) S12
(A13, B13) S13
(A14, B14) S14
(A15, B15) S15

52
Arithmetic Circuits
Digital
(a 0, b 0) S0
(a 1, b 1) S1
(a 2, b 2) S2
(a 3, b 3) S3

(a 4, b 4) S4
Tree Adders
(a 5, b 5) S5
(a 6, b 6) S6
(a 7, b 7) S7
(a 8, b 8) S8
16-bit radix-4 Kogge-Stone Tree (a 9, b 9) S9
(a 10, b 10) S 10
(a 11, b 11) S 11
(a 12, b 12) S 12
(a 13, b 13) S 13
(a 14, b 14) S 14
(a 15, b 15) S 15
53
Arithmetic Circuits
Digital
(a 0, b 0) S0
(a 1, b 1) S1
(a 2, b 2) S2
(a 3, b 3) S3

(a 4, b 4) S4
(a 5, b 5) S5
Sparse Trees
(a 6, b 6) S6
(a 7, b 7) S7
(a 8, b 8) S8
(a 9, b 9) S9
(a 10, b 10) S 10
(a 11, b 11) S 11
(a 12, b 12) S 12
16-bit radix-2 sparse tree with sparseness of 2
(a 13, b 13) S 13
(a 14, b 14) S 14
(a 15, b 15) S 15
54
Arithmetic Circuits
Digital
(A0, B0) S0
(A1, B1) S1
(A2, B2) S2

(A3, B3) S3
Brent-Kung Tree
(A4, B4) S4
Tree Adders
(A5, B5) S5
(A6, B6) S6
(A7, B7) S7
(A8, B8) S8
(A9, B9) S9
(A10, B10) S10
(A11, B11) S11
(A12, B12) S12
(A13, B13) S13
(A14, B14) S14
(A15, B15) S15

55
Arithmetic Circuits
Example: Domino Adder
VDD
VDD
Clk
Gi = aibi
Clk
P i = a i + bi ai
ai bi
bi
Clk
Clk
Propagate Generate
56
Digital
Arithmetic Circuits
Example: Domino Adder
VDD
VDD
Clkk
Clkk
Pi:i-2k+1 Gi:i-2k+1
Pi:i-k+1 Pi:i-k+1
Gi:i-k+1
Pi-k:i-2k+1 Gi-k:i-2k+1
Propagate Generate
57
Digital
Arithmetic Circuits
Example: Domino Sum
VDD VDD Keeper
Clk Clkd
Sum
Gi:0
Clk Si0
Clkd
Clk
Gi:0
Si1
Clk
58
Digital
Arithmetic Circuits
Adders Summary
59
Digital
Arithmetic Circuits
Multipliers
60
Digital
Arithmetic Circuits
The Binary Multiplication
61
Digital
Arithmetic Circuits
62
Digital
Arithmetic Circuits
1 0 1 0 1 0 Multiplicand
x 1 0 1 1 Multiplier
1 0 1 0 1 0
1 0 1 0 1 0
0 0 0 0 0 0 Partial products
+ 1 0 1 0 1 0
1 1 1 0 0 1 1 1 0 Result
63
Digital
Arithmetic Circuits
The Array Multiplier
X3 X2 X1 X0 Y0
X3 X2 X1 X0 Y1 Z0
HA FA FA HA
X3 X2 X1 X0 Y2 Z1
FA FA FA HA
X3 X2 X1 X0 Y3 Z2
FA FA FA HA
Z7 Z6 Z5 Z4 Z3
64
Digital
Arithmetic Circuits
The MxN Array Multiplier
Critical Path
HA FA FA HA
FA FA FA HA Critical Path 1
Critical Path 2
Critical Path 1 & 2

FA FA FA HA
65
Digital
Arithmetic Circuits
Carry-Save Multiplier
HA HA HA HA
HA FA FA FA
HA FA FA FA
HA FA FA HA
Vector Merging Adder
66
Digital
Arithmetic Circuits
Multiplier Floorplan
X3 X2 X1 X0
Y0
Y1 HA Multiplier Cell
C S C S C S C S
Z0
FA Multiplier Cell
Y2
C S C S C S C S
Z1 Vector Merging Cell
Y3
C S C S C S C S X and Y signals are broadcasted
Z2 through the complete array.
( )
C C C C
S S S S
Z7 Z6 Z5 Z4 Z3
67
Digital
Arithmetic Circuits
Wallace-Tree Multiplier
Partial products First stage
6 5 4 3 2 1 0 6 5 4 3 2 1 0 Bit position
(a) (b)
Second stage Final adder

6 5 4 3 2 1 0 6 5 4 3 2 1 0
FA HA
(c) (d)
68
Digital
Arithmetic Circuits
x3y2 x2y2 x3y1 x1y2 x3y0 x1y1 x2y0 x0y1
Partial products x3y3 x2y3 x1y3 x0y3 x2y1 x0y2 x1y0 x0y0
First stage
HA HA
Second stage FA FA FA FA
Final adder
z7 z6 z5 z4 z3 z2 z1 z0
69
Digital
Arithmetic Circuits
y0 y1
y2
y 0 y 1 y2 y3 y4 y5
Ci-1
FA
y3
FA FA
Ci Ci Ci-1
Ci-1
FA Ci Ci-1
y4
FA
Ci Ci-1 Ci Ci-1
FA
y5
Ci FA
FA
C S
C S
70
Digital
Arithmetic Circuits
Wallace Tree Mult. Performance
71
Digital
Arithmetic Circuits
Wallace Tree Multiplier Complexity
72
Digital
Arithmetic Circuits
4:2 Adder
73
Digital
Arithmetic Circuits
Eight-input Tree
74
Digital
Arithmetic Circuits
Architectural comparison of
multiplier solutions
75
Digital
Arithmetic Circuits
SPIM Architecture
76
Digital
Arithmetic Circuits
SPIM Pipe Timing
77
Digital
Arithmetic Circuits
SPIM Microphotograph
78
Digital
Arithmetic Circuits
SPIM clock generator circuit
79
Digital
Arithmetic Circuits
Binary Tree Multiplier Performance
80
Digital
Arithmetic Circuits
Binary Tree Multiplier Complexity
81
Digital
Arithmetic Circuits
Multipliers Summary
Optimization Goals Different Vs Binary Adder
Once Again: Identify Critical Path
Other possible techniques

- Logarithmic versus Linear (Wallace Tree Mult)
- Data encoding (Booth)
- Pipelining
FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION
82
Digital
Arithmetic Circuits
Multipliers Summary
83
Digital
Arithmetic Circuits
Booth encoding
84
Digital
Arithmetic Circuits
Booth encoding
85
Digital
Arithmetic Circuits
Tree Multiplier with Booth Encoding
86
Digital
Arithmetic Circuits
The f.p. addition algorithm
Exponent comparison and swap (if

needed)
Mantissas aligment
Addition
Normalization of result
Rounding of result
87
Digital
Arithmetic Circuits
The f.p. multiplication algorithm
Mantissas multiplication
Exponent addition
Mantissa normalization and exponent
adjusting (if needed)
Rounding of result
88
Digital
Arithmetic Circuits
Dividers
89
Digital
Arithmetic Circuits
Iterative Division (Newton-Raphson)
90
Digital
Arithmetic Circuits
Iterative Division (Newton-Raphson)
91
Digital
Arithmetic Circuits
Quadratic Convergence of the Newton
Method
92
Digital
Arithmetic Circuits
Properties of the Newton Method
Asymptotically quadratic convergence

Correction of round-off errors
Final multiplication by a generates a
round-off problem incompatible with
the Standard IEEE-754
93
Digital
Arithmetic Circuits
Iterative Division (Goldschmidt)
94
Digital
Arithmetic Circuits
Iterative division (Goldschmidt)
95
Digital
Arithmetic Circuits
Iterative Division (Goldschmidt)
The sequence of xn tends to a/b

The convergence is quadratic
In its present form, this method is
affected by roud-off errors
96
Digital
Arithmetic Circuits
Modified Goldschmidt Algorithm
(correction of round-off errors)
97
Digital
Arithmetic Circuits
The Link between the Newton-Raphson
and Goldschmidt Methods
98
Digital
Arithmetic Circuits
The Link between the Newton-Raphson
and Goldschmidt Methods
99
Digital
Arithmetic Circuits
Comparison between Newton and
Goldschmidt methods
The Newton and Goldschmidt methods
are essentially equivalent;
Both methods exhibit an asymptotically
quadratic convergence;
Both methods are able to correct round-
off errors;
The Goldschmidt methods directly
computes the a/b ratio.
100
Digital
Arithmetic Circuits
Shifters
101
Digital
Arithmetic Circuits
The Binary Shifter
Right nop Left
Ai Bi
Ai-1 Bi-1
Bit-Slice i
...
102
Digital
Arithmetic Circuits
The Barrel Shifter
A3
B3
Sh1
A2
B2
Sh2 : Data Wire

A1
B1 : Control Wire
Sh3
A0
B0
Sh0 Sh1 Sh2 Sh3
Area Dominated by Wiring

103
Digital
Arithmetic Circuits
4x4 barrel shifter
A3
A2
A1
A0
Sh0 Sh 1 S h2 Sh3
B uffer
Widthbarrel ~ 2 pm M
104
Digital
Arithmetic Circuits
Logarithmic Shifter
Sh1 Sh1 Sh2 Sh2 Sh4 Sh4
A3 B3
A2 B2
A1 B1
A0 B0
105
Digital
Arithmetic Circuits
0-7 bit Logarithmic Shifter
A
3
Out3
A
2
Out2
A
1
Out1
A
0
Out0
106
Digital
Arithmetic Circuits
ALUs
107
Digital
Arithmetic Circuits
Two-bit MUX
108
Digital
Arithmetic Circuits
Two-bit MUX Truth Table
109
Digital
Arithmetic Circuits
Two-bit Selector Truth Table
110
Digital
Arithmetic Circuits
Carry-chain Truth Table
111
Digital
Arithmetic Circuits
ALU block diagram (Mead-Conway)
112
Digital
Arithmetic Circuits
ALU Operations
113
Digital
Arithmetic Circuits
ALU Operations
114
Digital
Arithmetic Circuits
ALU Operations
115
Digital
Arithmetic Circuits
ALU Operations
116
Digital
Arithmetic Circuits
ALU Operations
117
Digital
Arithmetic Circuits
MIPS-X Instruction Format
118
Digital
Arithmetic Circuits
Pipeline dependencies in MIPS-X
119
Digital
Arithmetic Circuits
Die Photo of MIPS-X
120
Digital
Arithmetic Circuits
MIPS-X Architecture
121
Digital
Arithmetic Circuits
MIPS-X Instruction Cache-miss timing
122
Digital
Arithmetic Circuits
MIPS-X Tag Memory
123
Digital
Arithmetic Circuits
MIPS-X Valid Store Array
124
Digital
Arithmetic Circuits
RAM Sense Amplifier
125
Digital
Arithmetic Circuits
CMOS Dual-port Register Cell
126
Digital
Arithmetic Circuits
Self-timed bit-line write circuit
127
Digital
Arithmetic Circuits
Register bypass logic
128
Digital
Arithmetic Circuits
Schematic of comparator circuit
129
Digital
Arithmetic Circuits
Squash FSM
130
Digital
Arithmetic Circuits
Cache-miss FSM
131
Digital
Arithmetic Circuits

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Digital Integrated

2-1 Mux SUMGEN s0

Itanium has 6 integer execution units like this

Tile identical processing elements

To register files / Cache

Fetzer, Orton, ISSCC02 7

Cin Full Cout

Cin Full Cout

= ABC i + ABC i + ABCi + ABCi

Define 3 new variable which ONLY depend on A, B

Can also derive expressions for S and Co based on D and P

Ci,0 Co,0 Co,1 Co,2 Co,3

Worst case delay linear with the number of bits

tadder = (N-1)tcarry + tsum

Goal: Make the fastest possible carry path circuit

Even cell Odd cell

Ci,0 Co,0 Co,1 Co,2 Co,3

Exploit Inversion Property

Idea: If (P0 and P1 and P2 and P3 = 1)

Carry Carry Carry Carry

Sum Sum Sum tsum Sum

tadder = tsetup + Mtcarry + (N/M 1)tbypass + (M 1)tcarry + tsum

"0" "0" Carry Propagation

"1" "1" Carry Propagation

Co,k-1 Multiplexer C o,k+ 3

0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry

Multiplexer Multiplexer Multiplexer Multiplexer

Sum Generation Sum Generation Sum Generation Sum Generation

Setup Setup Setup Setup

"0" Carry "0" Carry "0" Carry "0" Carry

"1" Carry "1" Carry "1" Carry "1" Carry

Sum Generation Sum Generation Sum Generation Sum Generation

S0-3 S 4 -7 S8-11 S 1 2-15 (10)

Setup Setup Setup Setup

"0" Carry "0" Carry "0" Carry "0" Carry

"1" Carry "1" Carry "1" Carry "1" Carry

S0-1 S2-4 S5-8 S9-13 S14-19 (9)

tp (in unit delays)

Can continue building the tree hierarchically.

EE141 Integrated Circuits2nd

16-bit radix-2 Kogge-Stone tree

(A10, B10) S10

(A11, B11) S11

(A12, B12) S12

(A13, B13) S13

(A14, B14) S14

(A15, B15) S15

EE141 Integrated Circuits2nd

16-bit radix-4 Kogge-Stone Tree (a 9, b 9) S9

EE141 Integrated Circuits2nd

EE141 Integrated Circuits2nd

(A10, B10) S10

(A11, B11) S11

(A12, B12) S12

(A13, B13) S13

(A14, B14) S14

(A15, B15) S15

Critical Path 1 & 2

Vector Merging Adder

Second stage Final adder

Optimization Goals Different Vs Binary Adder

Once Again: Identify Critical Path