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Embedded System of Automatic Level Control

Based on FPGA

Article August 2010

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Hetal Patel Dr. Pravin R. Prajapati

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Embedded System of Automatic Level Control Based on FPGA
1 2
Hetal N Patel , Pravin R Prajapati

ABSTRACT:
This paper describes the control of level in water tank and boilers in the thermal plants
for safety purpose and for domestic use. Efficient FPGA based water level controller is
described which turn on the motor pump when water in the overhead tank falls below the
lowest level and turns it off when the upper tank is full. It also turn off motor when lower
tank level is falls below the lowest level in respective of condition of upper tank level.
Moreover, if the pump is running dry due to non availability of water, it will sense dry
run condition and turn off motor automatically. For indication of motor on, motor off and
dry run conditions LEDs are connected. Manual facility to turn on and off of motor also
included. The embedded system is designed with Spartan 3 FPGA family, level sensors,
LED indicators and dry run sensors for automatic level control of water tank.

Index Terms: Field Programmable Gate Array (FPGA), Fuzzy Controller, RTL
Schematic, Dry Run, HDL code, Slices, Synthesis.

1. INTRODUCTION monitor level of upper tank water, one

Level Controller is a device used to has to climb staircase and switch off
maintain the level of any liquid to motor if level of upper tank is near to
predefined level contained within a upper level. Sometimes even though
particular boundary. This boundary can a motor cannot climb up water from lower
separate container like a steel tank or a tank to upper tank, unnecessary motor run
civil structure like centrally located water and there is wastage of electricity. Here
containing high rise overhead tanks made FPGA based water level control is
up of concrete that supply water to the discussed which solve all problems.
city. This predefined level is the user
specified level, the maintaining of which 2. FIELD PROGRAMMABLE
will further initiate/abort some process or GATE ARRAYS:
lead to proper functioning of the system
of which this container is a part by A Field Programmable Gate Arrays
fulfilling some of the system (FPGAs) is a digital integrated circuit that
requirements. Water management and can be programmed to do any type of
planning is important for saving water digital function. There are three main
and electric energy. At home, hostel or advantages of an FPGA over a
hotel if there is no any automatic control microprocessor chip for fuzzy systems:
of water level, sometimes water is wasted (1) An FPGA has the ability to be
due to overflow of upper tank. To reprogrammed on the fly.
________________________________________________________________________
Hetal N Patel and Pravin R Prajapati are Assistant Professor of Electronics and
Communication Department of A D Patel Institute of Technology, Karamsad, Gujarat-
388121
(2) The new FPGAs that are on the
market will support hardware that is
upwards of 1 million gates,
(3) An FPGA used as a fuzzy controller
will be semicustom hardware
(4) The FPGA will operate faster than a
microprocessor chip.
2.1 Steps of Programming the
FPGA:
The process of programming the FPGA
chip[2] is shown in the figure 1.
Figure 1 : Algorithm verification and
implementation design flow:
Simulation: verifying the design
specifications after design entry is
functional simulation. It saves the
time consumed for physical
prototyping.
Synthesis: Is the process of
creating a representation of a
system at a lower level of design
abstraction from a higher level
representation.
Synthesis tools provides a means
to convert schematic or HDL in
real-world hardware. The output
of synthesis is a net list.
For locking physical pins with the
designed entity user constraint file
(UCF) has to specify by the user.
Implementation: Is the process
of placing the design into the
specified target technology.
Implementation tool reads the
standard net list and fits it into the
target device.
Following steps are performed by the
implementation tool
Mapping: Tool partitions the
design into the logic blocks
available on the device. Good
partitioning results in better
performance.
Placing: After the logic is
partitioned, implementation
software searches for the best
location to place the logic block
among all of the possibilities.
Primary goal is to reduce the
amount of outing recourses
required.
Routing: Logical nets are
assigned to the physical wire
segments in the device that
interconnect logic cells.
Programming:
After the design is implemented,
software creates the bit stream
(binary programming).
The programmable device is
configured for the function by
downloading the programming
file into target.
After the device is programmed,
you are ready to test the actual
system, with real life inputs and
outputs.
2
3.0 IMPLEMENTATION OF
THE WATER LEVEL
CONTROLLER:
The device used for the implementation is
Spartan -3 1.2V FPGA family XC3S400-
4PQ208.The Spartan TM -3 family is
supported by the complete set of Xilinx
integrated Software Environment
(ISE)[1] development tools, with
additional support available from a
variety of partners. Figure 3 (Resistor Transistor Logic) RTL
schematic
The design for the water level controller The above figure 3 shows the gate level
using FPGA family XC3S400-4PQ208 is implementation design of the water level
shown below in figure 2. controller. Here in the figure 3 the inputs
are the level sensors of the upper tank and
lower tank. Another input is the output of
the wire, which indicates the presence of
water in the line. Depending on these five
inputs the digital design shown above
will make the motor on / off. Also if the
motor is on, the status of sensor for the
dry running condition is checked and if it
will give the 0 result, the motor will be
off and the LED will indicate the DRY
Figure 2 (Resistor Transistor Logic) RTL
condition. The comparison of the water
schematic
level sensors of the upper tank and the
lower tank is made by the design shown
The above figure 2 is the RTL schematic
below in figure 4.
generated after synthesis of the HDL
Code. Again the detail of the design is
generated by double clicking on the
symbol generated by the synthesis tool.
The pop up window will show the
internal detail of the block shown above
in figure 2. The detail inside the block is
shown in figure 3 below.

Figure 4 (Resistor Transistor Logic) RTL

schematic

The inputs to the design are the water

levels of the upper tank. Depending on

3
the water levels detected by the input
vector, the device is programmed to make
the motor on or off. The design is also
having the feature of stopping the motor
in dry condition. Means when motor is on
and water is not transfer because of any
reason the design will stop the motor to
protect from the dry condition. The
simulation result is shown below in figure
5:
Figure 5: Simulation Result
The above simulation result shows the
switching of motor depending on the
input vector. The summary of the devices
used for the design are listed below:
Device utilization summary:
Selected Device :3s400pq208-5
Number of Slices:
1 out 0%
of
3584
Number of 4 input 2 out 0%
LUTs: of
7168
Number of IOs: 6 operation continuously.
Number of bonded IOBs: 6 out 4%
of
141
The Delay summary Report:
The number of signals not 0
completely routed for this design is:
The average connection delay for 0.545
this design is:
The maximum pin delay is: 1.283
The average connection delay on 0.675
the 10 worst nets is:
Listing Pin Delays by value: (nsec)
d< <d< <d< <d<4.0 <d<5.0 d>=5.0
1.0 2.00 3.0
8 1 0 0 0 0
4.0 ALGORITHM
The algorithm of the water level
controller is shown below:
Step 1: Read the inputs (level sensors and
wire sensor for dry indication).
Step 2: Compare the inputs in terms of
levels, depending on the comparison
result generate the signal for motor.
Step 3: Send the appropriate ON/OFF
signal to the motor.
Step 4: During the ON condition of
motor, check the status of wire, which
indicates presence of water in the line.
Step 5: If the wire sensor will give the 0
output, make the motor OFF, else
continue the motor in ON condition.
Step 6: Go to the step 1 and do the
5.0. TESTING OF CIRCUIT
1. Immerse points R and A in water, as
would be the case when the water
level rises. Momentarily touch point
4
 B to water. LED1 goes off and the delivered from the water pipe
relay de-energies to turn the pump doesnt touch any of the
off. This would be the case when suspended water-level sensors.
water touches the overflow limit. 2. Mount the dry run sensor firmly
2. Remove points A from the water onto the water pipe such that elec-
assuming that water level goes below trodes E and F are shorted by
lower limit. Relay will be energies water flowing out of the pipe.
and motor will be on. 3. Use a properly shielded cable to
3. Similar task can be done for upper carry signals from the tank to
tank. water level controller unit.
The complete circuit diagram of the
water level controller is shown below 6. CONCLUSION
in figure 6.
The objective to use the FPGA for
+12V 12V, 100
Ohm Relay
water level control is to improve the
Upper Tank
R1
functioning of the level controller in the
4 Bypass
D R5
T1
330
ohm 1
IC
PC817
T5
Switch
230 V
Motor
industries and domestic use. The FPGA
R9
3
L AC
50Hz
N
used for the water level control is much
C

R2
2 more superior in technology, more
Sensor 3
R6
R3
efficient and effective, more precise in
Sensor 2
R10 T2 Spartan-3,
1.2V
FPGA
level control, simpler in use and more
Sensor 1
Family
XC3S400-
4PQ208
economic as compared to the
Sensor 0
R7
R4
LED for
conventional methods. The role of the
R11 Wire Dry Run
T3
indication
level indicator becomes so critical that
B
To Point A
it is malfunctioning can lead to total
R8

T4
R1-R4 =10k Ohm
disruption of the system functioning of
A R12 R5-R8 =10k Ohm
R9-R12 =100k Ohm
the level control of tank. So rust free
R

Lower Tank
T1-T5 =BC 548
and alkali free sensor should be used.

Figure 6: Circuit diagram of the FPGA 7. REFERENCES

based Water Level Controller (1) Xilinx Version ISE 9.2.
(2) FPGA Kit SPARTAN 3 Manual.
(3) J. Bhasker , VHDL Primer,
Prentice-Hall India(PHI), 3RD Edition.
(4) S.S.Limaye, VHDL A Design
Oriented Approach, Tata McGraw-
Hill Publishing Company Limited, 1st
Edition.
Figure 7: Dry Run Sensor arrangement (5) Sudhakar Yalamanchili,

5. PRECAUTIONS Introductory VHDL From

Simulation to Synthesis, Pearson
1. Make sure that water being
Education, Low Price Edition.
5

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