CHAPTER FIVE

MEMORY INTERFACE

1 Memory Addressing
The semiconductor memories are organized as two dimensional arrays of memory locations. For
example, 4K x 8 or 4K byte memory contains 4096 locations, where each location contains 8-bit
data and only one of the 4096 locations can be selected at a time. Once a location is selected all
the bits in it are accessible using a group of conductors called data bus. To address a memory
location out of N memory locations, it is required at least n bits address, i.e. n address lines where
n = log2 N . Thus if the microprocessor has n address lines, then it is able to address at most
N locations of memory, where 2n = N . However, if out of N locations only p memory locations
are to be interfaced, then the least significant p address lines out of the available n lines can be
directly connected from the microprocessor to the memory chip while the remaining (n-p) higher
order address lines may be used for address decoding.
The 8086 is a 16-bit microprocessor; it can transfer 16-bit data. So in addition to byte, word
(16-bit) has to be stored in the memory. This is stored by using two consecutive memory locations,
one for least significant byte and the other for most significant byte. The address of word is the
address of least significant byte. To implement this, the entire memory is divided into two memory
banks: bank0 and bank1. Fig. 5.1 shows the interfacing diagram to these memory banks. Bank0
is selected only when A0 is zero and Bank1 is selected only when BHE (negated) is zero. A0 is zero
for all even addresses, so that Bank0 is usually referred as even addressed memory bank. BHE
(negated) is used to access higher order memory bank, referred as odd addressed memory bank.

Figure 1: Memory interfacing

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 The 8086 microprocessor provides 20-bit memory address that allows up to 1 Mbyte main
memory. It is important in any memory interface that one block of memory must not be allowed
to overlap another memory block. So in order to attach a memory device to the microprocessor, it
is necessary to decode the address from the microprocessor to access each memory independently.

2 Address Decoding
One of the most common, although not only, integrated circuit decoders found in many micro-
processor based system is the 74LS138 3-to-8 line decoder. For any of the decoders outputs to go
low, the three enable inputs (G2A (neg.), G2B (neg.), and G1) must all be active. To be active,
the G2A (neg.) and G2B (neg.) input must both be low (logic 0), and G1 must be high (logic
1). Once the 74Sl138 is enabled, the address inputs (C, B, and A) select which output pin goes
low. Notice that the outputs of the decoder, illustrated in Figure 5.3, are connected to two 2764
EPROM and two 2764 RAM memory device.

Figure 2: Memory interfacing

Application Example: Design an 8086 based system with the following specifications.
1. 64 KByte EPROM

2. 64 KByte RAM

Draw the complete schematic of the design indicating address map

The 8086 is a 16 bit microprocessor. It can access 16 bit data simultaneously. For interfacing
memory module to 8086 CPU, it is necessary to have odd and even memory banks. This can be
achieved by using two 32 Kbyte EPROMs and two 32 Kbyte RAMs, one for odd bank another for
even bank. As 32 Kbyte RAM and EPROM need 15 address lines, A1 to A15 lines are used. A0
and BHE (neg.) are used to even and odd memory banks respectively.

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