Controller plus Datapath Model

Dr DC Hendry

April 16, 2006

1 Control and Datapath Model

Control Controller Control

Inputs (FSM) Outputs

Data Status Internal Control

Data Datapath Data

Inputs Outputs

1.1 Datapath

Data Status Internal Control

Data Datapath Data

Inputs Outputs

Data Inputs are data items (16 bit, 32 bit) bit patterns from the outside
world.
1.2 Controller Control + Data

Data Outputs are the data results from the processing of the data inputs.

Data Status are single bit signals indicating something about the data,
e.g. that an item is zero.
Internal Control are control lines to the datapath, multiplexor select
lines for example.

1.2 Controller

Control Controller Control

Inputs (FSM) Outputs

Data Status Internal Control

Control Inputs are single bit control lines from the outside world, e.g.
comms status lines.
Control Outputs are single bit control lines to the outside world.

Data Status are single bit signals indicating something about the data,
e.g. that an item is zero.
Internal Control are control lines to the datapath, multiplexor select
lines for example.

FSM View

The controller is designed as an FSM, and in general may be complex. The

inputs and outputs of that FSM are:

Inputs

Control inputs from the outside world and

Data status bits from the datapath.

Outputs

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 Control + Data

Control outputs to the outside world and

Internal control lines to the datapath.

2 Register Transfer Language

Register Transfer Language

R1 C/L R2

1. The basic operation in a register transfer language is the movement of

data through a block of combinational logic from one register to another.
2. This movement takes place during a single synchronous clock cycle.
3. R1 launches new data at the start of the clock cycle, R2 catches the
processed data at the end of the same clock cycle.

4. The propagation delay of the combinational logic determines the minimum

clock period.

Register Transfer Language ...

R1 C/L R2

1. The diagram above is described by a statement of the form:

R2 f (R1 )

where f is a function describing the combinational logic.

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 Control + Data

2. Inputs to combinational logic may come from multiple registers, for ex-
ample, an adder will have two inputs (probably) from registers and one
output to a register:
R 3 R1 + R 2

Example with an internal control line

R1

R3

R2

add/
subtract
1. R3 R1 + R2
2. In this case the ALU can either add or subtract, so the above statement
implies a value for the add/subtract input line.

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 Control + Data

3. To be complete we might write:

R3 R 1 + R2
add subtract = 0
(1)

3 Communications

Communications

1. Data must be communicated from its source (output of a register or combi-

national logic) to its intended location (input of a register or combinational
logic).
2. For short range communications, either multiplexors or buses are used.
3. For longer range communications buffer structures are needed (synthesis
tools can generate some of these as necessary).

4. For chip level communications in large designs on chip local area networks
are needed (definitely not discussed here!).

3.1 Multiplexors

Multiplexors

1. Multiplexors may be placed at the inputs of either a register or a block of

combinational logic where the inputs can come from a variety of locations.
2. The number of inputs is limited (less than 10 say).
3. The select inputs of a multiplexor are driven by the controller, so they
become the outputs of an FSM.
4. In VHDL coding simply use a single concurrent statement.
5. Easier to read if an enumerated type or constants used to define the the
select input patterns.

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3.1 Multiplexors Control + Data

Multiplexor Example

R1

R2

1. In this case the top ALU input can be either R1 or R2 .

2. A single multiplexor select line is required to be driven by the controller
(FSM).

3. The second input of the ALU, and the output not specified in this diagram.

VHDL Code

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3.2 Buses Control + Data

constant ALUIN1R1 : natural := 0;

constant ALUIN1R2 : natural := 1;
signal aluin1sel : std logic;
signal r1, r2, aluin1 :
std logic vector(15 downto 0);
.
.
aluin1mux : with aluin1sel select
aluin1 <= r1 when ALUINR1,
r2 when others; ALUINR2

3.2 Buses

Bus Structures

1. Bus structures best when a large number of sources need to drive (one at
a time) one target.
2. Each possible driver requires one output enable line.
3. Only one output enable line should be active at a time - drive these with
the FSM.

4. Any number of targets can read from the bus during the same clock cycle.
5. Long buses can suffer from high capacitance and so high power dissipation.

Typical Bus Structure

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3.2 Buses Control + Data

VHDL Coding of Buses

Type std logic includes the value Z for the high impedance value. Typical
VHDL:
signal bus1, r1, r2 : std logic vector(15 downto 0);
signal r1enable, r2enable : std logic;
.
.
r1driver : process(r1, r1enable)
begin
if (r1enable = 0) then
bus1 <= (others => Z);
else
bus1 <= r1;
end if ;
end process r1driver;

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