Anda di halaman 1dari 2

Assigned:14November2017

Homework#6
EE209:Fall2017

1. TheequivalentresistanceofaPMOSandNMOStransistorinaCMOSinverterare10Kand7K,respectively.
Theinverterdrivesaneffectivecapacitanceof10fF(femtofarads).Ignoreotherinternalcapacitances.Use
anequivalentRCmodeltocalculatethetimeconstant( ),thepropagationdelay(50%),andthetransition
time(10to90%)forboththerisingoutputcaseandfallingoutputcase.

2. Consider the pulldown network for the CMOS


compoundgateshowntotheright.
a. Drawthecomplementarypullupnetwork.
b. WritetheBooleanequationfor .
c. Annotate your completed pullup and pull
downnetworkwithwidthsforeachNMOS
andPMOStransistorsothattheworstcase
current for both rise and fall matches the
equivalent pullup and pulldown
resistance of a CMOS inverter. Assume
4where istheconductancefor

thetransistor.

3. DrawaCMOStransistorleveldiagramforthelogicfunction .Annotateyourdiagram
withtransistorwidthssothatyourimplementationmatchestheequivalentpullupandpulldownresistance
ofaCMOSinverter.Assumethemobilityratio 2andthatthetransistorsareminimumlength(i.e.
1).

4. DrawtheCMOScircuitforthelogicfunction .Youmayassumethatcomplement
valuesareavailable.SizethetransistorssuchthattheCMOScircuitistwiceasstrongasareferenceinverter
withanNMOS 1andPMOS 3.

5. TheinputofaCMOSinverterispermanentlyconnectedto 0.6 .Assume , , 0.2 .Calculate


theoperatingregionoftheNMOSandPMOStransistors.

6. SetupaKCLequationtocalculatetheoutputvoltage( )ofaCMOSinverterwithNMOS 1and


PMOS 2whereinvertertheinputispermanentlyconnectedtoahighvoltageof2.4 .Assume
3.0 , , , 0.4 ,and 2 .PuttheKCLequationinstandardquadraticform(i.e.0
).Compute .[hint:makeaneducatedguessfortheapproximate .Useyourguesstoinfer
theoperatingmodeforeachtransistor.Afteryoucalculate checkthattheoperatingmodesyouinferred
areconsistentyouranswer].
7. ListthesizeoftheROMrequiredtoimplementeachofthefollowinglogicfunctions.Drawablockdiagram
oftheROMshowingthedevicelabels: 1 to 0 andthedataoutputs: 1 to 0 .Thenadd
appropriatesystemlabelsforeachfunction.DonotwritethecontentsoftheROM;youonlyneedtowrite
thesize.[reminder:devicelabelsareinsidetheblockandsystemlabelsareoutsidetheblock].
a. Converta3bit2scomplementnumber 2: 0 totheequivalentsignedmagnitudenumber .
b. 2,5,6,7,8,10,13,15 .
c. Squarea6bit2scomplementnumber 5: 0 toproduce with inunsignedrepresentation(since
isalwayspositive).

8. Considerthefollowinglogicfunction.

1,3,4,8,9,13 6,12,15

a. Implement using a single 2x1 mux and additional basic logic gates (AND, OR, NOT, NAND, NOR) as
needed.
b. Implement using a single 4x1 mux and additional basic logic gates (AND, OR, NOT, NAND, NOR) as
needed.
c. Implement usingasingle8x1muxandinverters.Donotuseanyadditionallogicgates.

9. Implement the following logic function pair using ONLY 2x1 multiplexers and inverters. Do not use any
additionallogicgates.[hint:theminimalsolutionuses4muxes].