PHASE

LOCKED
LOOP
TEAM

ANSHU KATARIA (1613501)

JITENDER KUMAR (1613627)

RAJAT SARDANA (1613641)

SALIL BATABYAL (1613526)

SUKRITI HANS (1613447)

TANYA VERMA (1613731)

 ACKNOWLEDGEMENT

The fo|qr group acknowledges the deep sense of gratitude to all the faculty members Prof.
Amitabh Mukherjee, Prof. Vinay gupta, Prof. Nivedita Deo, Prof. K. Sreenivas and Dr. Manjula for
their spirited encouragement, healthy criticism and inspiring discussion throughout session
August 2017 to December 2017. Acknowledgements are due to Prof. Amitabh Mukherjee and
Prof. Vinay Gupta for their valuable suggestions regarding the new addition to the work
Differential Equation Solver, and Prof. Nivedita Deo for Lissajous Figure. We are also
fortunate to have a company of all the motivated students of electronics lab 2017-18, without
their help and cooperation it would have been difficult for us to enjoy the academic environment
of the lab.

At the end, the fo|qr, is also grateful to the lab staff for the constant help during the course of
work.
 Contents
2.0. INTRODUCTION ............................................................................................................................... 1
VARIATION OF FREE RUNNING FREQUENCY OF PLL WITH RT ............................................................. 10
2.1. VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH CF ...................................................... 13
2.2. VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH RT ...................................................... 19
2.3. APPLICATIONS OF PLL ................................................................................................................... 23
2.3.1. DIVIDE BY 5 NETWORK ..................................................................................................... 27
2.3.2. LOCK RANGE AND CAPTURE RANGE ................................................................................ 29

BIBLIOGRAPHY ............................................................................................................................................ 32
fo|q r INTRODUCTION

INTRODUCTION
CONCEPT OF PHASE:
The operation of a phase locked loop, PLL, is based around the idea of comparing the phase of
two signals. This information about the error in phase or the phase difference between the two
signals is then used to control the frequency of the loop.

To understand more about the concept of phase and phase difference, first visualize a radio
frequency signal in the form of a familiar x-y plot of a sine wave. As time progresses the amplitude
oscillates above and below the line, repeating itself after each cycle. The linear plot can also be
represented in the form of a circle. The beginning of the cycle can be represented as a particular
point on the circle and as a time progresses the point on the waveform moves around the circle.
Thus, a complete cycle is equivalent to 360 or 2 radians. The instantaneous position on the
circle represents the phase at that given moment relative to the beginning of the cycle.

Fig. 2.0.1

To look at the concept of phase difference, take the example of two signals. Although the two
signals have the same frequency, the peaks and troughs do not occur in the same place. There is
said to be a phase difference between the two signals. This phase difference is measured as the
angle between them. It can be seen that it is the angle between the same point on the two
waveforms. In this case a zero-crossing point has been taken, but any point will suffice provided
that it is the same on both.

When there two signals have different frequencies, it is found that the phase difference between
the two signals is always varying. The reason for this is that the time for each cycle is different
and accordingly they are moving around the circle at different rates.

1
fo|q r INTRODUCTION

Fig. 2.0.2

It can be inferred from this that the definition of two signals having exactly the same frequency
is that the phase difference between them is constant. There may be a phase difference between
the two signals. This only means that they do not reach the same point on the waveform at the
same time. If the phase difference is fixed it means that one is lagging behind or leading the other
signal by the same amount, i.e. they are on the same frequency.

PHASE LOCKED LOOP:

A phase locked is controlled loop consisting of three fundamental components. These are phase
detector, loop filter, voltage controlled oscillator (VCO).

BLOCK DIAGRAM:
The block diagram of a basic PLL is shown in the figure below. It is basically a flip flop consisting
of a phase detector, a low pass filter (LPF), and a Voltage Controlled Oscillator (VCO).

Fig. 2.0.3

2
fo|q r INTRODUCTION

The input signal Vi with an input frequency fi is passed through a phase detector. A phase detector
basically a comparator which compares the input frequency f i with the feedback frequency fo.
The phase detector provides an output error voltage Ver( ) = fi + fO, which is a DC voltage. This
DC voltage is then passed on to an LPF. The LPF removes the high frequency noise and produces
a steady DC level, Vf = fi fO. Vf also represents the dynamic characteristics of the PLL.

The DC level is then passed on to a VCO. The output frequency of the VCO (f O) is directly
proportional to the input signal. Both the input frequency and output frequency are compared
and adjusted through feedback loops until the output frequency equals the input frequency.
Thus, the PLL works in these stages free-running, capture and phase lock.

As the name suggests, the free running stage refer to the stage when there is no input voltage
applied. As soon as the input frequency is applied the VCO starts to change and begin producing
an output frequency for comparison this stage is called the capture stage. The frequency
comparison stops as soon as the output frequency is adjusted to become equal to the input
frequency. This stage is called the phase locked state.

Fig. 2.0.4

PLL is the feedback system which detects the phase error and then adjusts the output.

PARTS OF PHASE LOCKED LOOP:

Now let us study in detail about the various parts of a PLL The phase detector, Low Pass Filter
and Voltage Controlled Oscillator.

3
fo|q r INTRODUCTION

1. PHASE DETECTOR:
This comparator circuit compares the input frequency and the VCO output frequency and
produces a dc voltage that is proportional to the phase difference between the two frequencies.
The phase detector used in PLL may be of analog or digital type. Even though most of the
monolithic PLL integrated circuits use analog phase detectors, the majority of discrete phase
detectors are of the digital type. One of the most commonly used analog phase detector is the
double balanced mixer circuit. Most common digital type phase detector is:

EXCLUSIVE OR (XOR) PHASE DETECTOR:

An exclusive OR phase detector is shown below. Obeying the EX-OR concept the output becomes
HIGH only if either of the inputs fi or fo becomes HIGH. All other conditions will produce a LOW
output. Let us consider a waveform where the input frequency leads the output frequency by
degrees. That is, fi and fo has a phase difference of degrees. The dc output voltage of the
comparator will be a function of the phase difference between its two inputs.

Fig. 2.0.5

The figure shows the graph of DC output voltage as a function of the phase difference between
fi and fo. The output DC voltage is maximum when the phase detector is 180.This type of phase
detector is used when both fi and fo are square waves. (Vdc= ).

4
fo|q r INTRODUCTION

Fig. 2.0.5

2. LOW PASS FILTER:

A Low Pass Filter (LPF) is used in Phase Locked Loops (PLL) to get rid of the high frequency
components in the output of the phase detector. It also removes the high frequency noise. All
these features make the LPF a critical part in PLL and helps control the dynamic characteristics of
the whole circuit. The dynamic characteristics include capture and lock ranges, bandwidth, and
transient response. The lock range is the tracking range where the range of frequencies of the
PLL system follows the changes in the input frequency. The capture range is the range in which
the Phase Locker Loops attains the Phase Lock.

When the filter bandwidth is reduced, the response time increases. But this reduces the capture
range. But it also helps in reducing noise and in maintaining the locked loop through momentary
losses of signal. Two types of passive filter are used for the LPF circuit in a PLL. An amplifier is
used also with LPF to obtain gain. The active filter used in PLL is shown below.

3. VOLTAGE CONTROLLED OSCILLATOR (VCO):

A voltage-controlled oscillator or VCO is an electronic oscillator whose oscillation frequency is
controlled by a voltage input. The applied input voltage determines the instantaneous oscillation
frequency. The main function of the VCO is to generate an output frequency that is directly
proportional to the input voltage.

This VCO provides simultaneous square wave and triangular wave outputs as a function of the
input voltage. The frequency of oscillation is determined by the resistor R and capacitor C along
with the voltage Vc applied to the control terminal.

5
fo|q r INTRODUCTION

WORKING:
PLL goes through 3 states:

Free running
Capture
Phase lock.

When the signal frequency and VCO frequency is same the loop gets locked. The loop gets locked
by detecting the phase difference between two inputs so called Phase Locked Loop (PLL). Without
application of any external signal, VCO has some frequency called as free running frequency or
centre frequency. In this initial condition loop is not locked i.e. in open condition.

When external signal is applied its frequency is either less or greater than VCO frequency so there
is a phase difference between them. Phase detector detects the phase difference between two
inputs and generates an error voltage. This is passed through LPF. After amplification it is given
as a controlled voltage. This adjusts the frequency of VCO such that input frequency is equal to
VCO frequency and forms locked condition. This process of locking the loop is called Capture
effect.

The time required for VCO to adjust its frequency with signal frequency is called capture time. It
depends on the internal parameters of system. There is some limit for input signal for which
system can acquire a locked condition. This range of frequency between which the system can
goes into locked condition is called capture range. This range is symmetrical about center
frequency. This capture range depends upon filter and amplifier characteristics.

If system acquires a locked condition then even if the signal frequency changes the loop remains
in locked condition. The range of input frequency over which the locked condition maintained is
called locked range. This also depends on amplifier and filter characteristics. Capture range is
always less than lock range or almost equal; but capture range is never greater than locked range.

The following figure shows the PLL spectrum of the three frequencies.

Fig. 2.0.6

6
fo|q r INTRODUCTION

Fig. 2.0.7

Initially the signal frequency is gradually increased. The PLL is not locked because signal frequency
and VCO frequency is not same. At frequency f1, the PLL is locked. Thus, f1 is referred as lower
edge of the capture range. After f1 PLL remains in locking condition. At frequency f1 a sudden
negative jump of error voltage is observed to shift the output frequency f O of VCO. If signal
frequency is still increased, the loop remains in locked condition. At frequency f2 the locked
condition is lost. So, frequency f2 is called as upper edge of the lock range. After f2, lock is removed
and error voltage drops to zero and VCO frequency returns to its free running frequency. If the
signal frequency is gradually decreased, the loop is captured at frequency f 3 and removed at
frequency f4 (i.e. between f3 and f4 the locking condition is maintained). Thus, f3 is called as upper
edge of the capture range and f4 is called as upper edge of lock range. Thus, frequency range
between f3 and f1 is called capture range and frequency range between f4 and f2 is called lock
range.

If the frequency of the input signal is outside the PLL lock range than PLL will not be able to
lock. Under this condition, VCO frequency jumps to its fundamental free running frequency.

NOTE: 1. Both PLL lock range and PLL capture range are centered around the VCO free running
frequency.
2. PLL acts as a Band Pass Filter which is effective in eliminating the noise as well as
interference from the input signal if present.

PIN DIAGRAM OF IC - 565:

The PLL IC 565 is usable over the frequency range 0.1 Hz to 500 kHz. It has highly stable center
frequency and is able to achieve a very linear FM detection. The output of VCO is capable of

7
fo|q r INTRODUCTION

producing TTL compatible square wave. The dual supply is in the range of 6V to 12V. The IC
can also be operated from single supply in the range 12V to 24V.

The following figure shows the pin-out and the internal block schematic of PLL IC LM 565.

Fig. 2.0.8

The pin configuration of the IC 565 operational amplifier is shown. It comprises of fourteen pins
where the function of each pin is discussed below.

Pin-14 is operated from a dual power supply +V (at pin no. 10) and V (at pin no. 1).
Pin-2 and 3 is Signal input for phase detector.
Pin-4 is VCO output is available.
Pin-4 and 5 are shorted externally so that VCO output is applied for phase detection. In
some applications PLL loop is broken and some circuit is to be connected between pin no
4 and 5.
Pin-6 is the reference dc voltage is available.
Pin-7 is demodulated output. If input signal between pin no 2 and 3 is FM signal then at
pin no 7 we get FM demodulation output.
Pin-8 and 9 external RT and CT for VCO (determines free running frequency of VCO).

8
fo|q r INTRODUCTION

Fig. 2.0.9

FEATURES OF IC - 565:
1) Extreme stability of center frequency typically 200ppm.
2) Wide range of operating voltage 6V to 12V.
3) Very high linearity of demodulated output typically 0.2%.
4) Centre frequency of VCO is programmable by means of resistor, capacitor or voltage.
5) TTL compatible square wave output.
6) Highly linear triangular wave output available at pin no.9.
7) Loop can be broken between pin no.4 and 5 and external circuit can be added.
8) Frequency adjustable over the range 1:10 with single capacitor.

APPLICATIONS:
Frequency Modulation (FM) stereo decoders, FM Demodulation networks for FM
operation.
Frequency synthesis that provides multiple of a reference signal frequency.
Used in motor speed controls, tracking filters.
Used in frequency shift keying (FSK) decodes for demodulation carrier frequencies

9
fo|q r VARIATION OF FREE RUNNING FREQUENCY WITH R T

VARIATION OF FREE RUNNING

FREQUENCY OF PLL WITH RT
AIM:
To study the variation of free running frequency of PLL with the timing resistance RT and to
compare it with theoretical value.

APPARATUS:
IC-565; 9V Dual Power Supply; Resistors R1 = 4.7k, R2 = 4.7k (Pot.), R3 = R4 = 10k; Capacitor
CF = 0.2F, CT = 0.02F, C = 1.08F; Function Generator; CRO/DSO.

THEORY:
A PLL is basically a closed loop feedback system. The basic purpose of the PLL is to synchronize
the frequency of the voltage controlled oscillator with that of the incoming signal, it goes through
the following three stages:

I) Free running: When the control voltage given as input to the VCO Is zero, then VCO is
said to be in free running mode.
1
Free Running Frequency, = 3.7

II) Capture: When the control voltage is applied as input to VCO, which forces the VCO
to change its output frequency to move towards the frequency of the incoming signal
until the two frequencies become equal is called capturing.
1 2
Capture Frequency, = 2

Where RF = 3.6k (From Internal Circuitry of IC 565)

III) Locked: when two frequencies (Input & Output) are equal, then circuit is said to be
locked. The total time taken by PLL to establish lock is called as pull in time.
8
Locked Frequency, =

Where = + ( )

10
fo|q r VARIATION OF FREE RUNNING FREQUENCY WITH R T

CIRCUIT DIAGRAM:

Fig. 2.1.1

PROCEDURE:
1. This circuit shown in Fig. 2.1.1 is connected on a breadboard/chassis.
2. Initially no input is applied for free running mode.
3. Output is recorded by changing the values of RT.
4. Frequency, fO of output (square wave) is noted.

NOTE: Instead of using a potentiometer, use fixed resistors.

11
fo|q r VARIATION OF FREE RUNNING FREQUENCY WITH R T

OBSERVATIONS:
1
=
3.7

Where CT = 0.016F

RT = R1 + R2 (k) Observed frequency,

(kHz) Calculated frequency, (kHz)
4.63 3.008 3.65
5.63 2.478 3.00
6.63 2.101 2.55
7.63 1.800 2.21
9.30 1.475 1.82
10.30 1.370 1.64
11.30 1.240 1.50
12.63 1.110 1.34
Table 2.1.1

CALCULATIONS:
3.008+1.110
Mid Frequency, = ( ) kHz = 2.059kHz
2

Corresponding to this frequency, = 8.20k

To a good approximation, fmid is close to 2.101kHz (from observations) obtained with RT = 6.63k.

RESULT:
Free running mode of VCO has been observed and mid frequency has been calculated.

12
fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH C F

VARIATION OF LOCK RANGE AND

CAPTURE RANGE WITH CF
AIM:
Study the variation of lock range and capture range with the filter capacitor CF, while keeping that
value of RT which corresponds to mid frequency of the output frequency band of observation
Table 2.1.1.

APPARATUS:
IC-565; 9V Dual Power Supply; Resistors R1 = 4.7k, R2 = 4.7k (Pot.), R3 = R4 = 10k, RT = 6.63k;
Capacitor CF = Two 0.20F, CT = 0.02F, C = 1.08F; Function Generator; CRO/DSO.

PROCEDURE:
1. The value of RT (=6.63k) set to mid frequency of the range of output frequency of Table
2.1.1.
2. To the circuit made in experiment 2.1 (Fig. 2.1.1), connect frequency generator to pin 2
through a capacitor.
3. The Fin was initially kept at some low value and was a square wave.
4. The frequency Fin was then increased and the output at C was noted.
5. The frequency was increased until the PLL ran out of lock after remaining in lock over a
range of frequency (i.e. output frequency is equal to the input frequency).
6. Now the frequency was slowly decreased and again the output frequency was noted.
7. The frequency was decreased beyond a point where PLL ran out of lock after remaining
so, for some range of frequency.
8. Using data from increasing input frequency and decreasing input frequency, graph
between output frequency and input frequency was plotted and then using the definition
of capture range and lock range, resp. bandwidths were obtained.
9. Thereafter the value of CF was changed to 0.4 F and steps (2) to (8) were repeated. Again,
the value of CF was changed to 0.1 F and steps (2) to (8) were repeated.

13
fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH C F

OBSERVATIONS:
i) CF = 0.20F

INCREASING INPUT FREQUENCY DECREASING INPUT FREQUENCY

FIN (kHz) FOUT (kHz) FIN (kHz) FOUT (kHz)
0.500 2.138 3.000 2.112
0.700 2.120 2.846 2.251
0.925 1.983 2.688 2.272
1.200 1.839 2.604 2.185
1.500 1.839 2.577 2.577
1.634 1.634 2.500 2.500
1.724 1.720 2.400 2.400
1.880 1.880 2.273 2.273
2.000 2.000 2.137 2.137
2.100 2.100 2.033 2.033
2.250 2.250 1.880 1.880
2.358 2.358 1.786 1.786
2.500 2.500 1.689 1.689
2.600 2.600 1.656 1.656
2.632 2.358 1.623 1.623
2.860 2.175 1.603 2.314
3.000 2.112 1.282 1.954
Table 2.2.1

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fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH C F

ii) CF = 0.40F

INCREASING INPUT FREQUENCY DECREASING INPUT FREQUENCY

FIN (kHz) FOUT (kHz) FIN (kHz) FOUT (kHz)
0.504 2.085 3.000 2.138
0.827 2.059 2.800 2.252
1.238 2.136 2.721 2.342
1.603 2.000 2.632 2.632
1.623 1.623 2.577 2.577
1.724 1.724 2.336 2.336
1.838 1.838 2.155 2.155
2.000 2.000 2.066 2.066
2.232 2.232 1.909 1.909
2.336 2.336 1.724 1.724
2.432 2.432 1.667 1.667
2.500 2.500 1.634 2.000
2.604 2.604 1.584 1.786
2.655 2.230 1.481 1.661
2.841 2.000 1.250 1.650
3.000 1.924 1.019 1.433
Table 2.2.2

15
fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH C F

iii) CF = 0.10F

INCREASING INPUT FREQUENCY DECREASING INPUT FREQUENCY

FIN (kHz) FOUT (kHz) FIN (kHz) FOUT (kHz)
0.347 2.320 2.941 2.001
0.748 2.313 2.884 2.131
0.822 2.083 2.874 2.874
1.259 2.470 2.731 2.731
1.515 2.063 2.655 2.655
1.623 1.894 2.601 2.601
1.656 1.736 2.523 2.523
1.736 1.736 2.446 2.446
1.854 1.854 2.381 2.381
2.022 2.022 2.293 2.293
2.174 2.174 2.179 2.179
2.255 2.255 2.054 2.054
2.380 2.380 1.932 1.932
2.520 2.520 1.782 1.782
2.683 2.683 1.656 1.656
2.841 2.841 1.521 2.433
2.860 2.532 1.359 2.125
2.992 2.778 1.018 1.972
Table 2.2.3

16
fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH C F

CALCULATIONS:
i) CF = 0.20F

From Graph:

= 2.600kHz = 1.623kHz

= = (2.600 1.623)kHz = 0.977kHz

8 16(2.101kHz)
= 2| | = 2 | |= = 1.868kHz
9 (9)

1 = 1.634kHz 2 = 2.577kHz

= 2 1 = (2.577 1.634)kHz = 0.943kHz

1 2 2(0.934kHz)
= 2| | = 2 | |= = 0.908kHz
2 (3.6k)(0.20F)

ii) CF = 0.40F

From Graph:

= 2.632kHz = 1.623kHz

= = (2.632 1.623)kHz = 1.009kHz

8 16(2.059kHz)
= 2| | = 2 | |= = 1.868kHz
9 (9)

1 = 1.667kHz 2 = 2.604kHz

= 2 1 = (2.604 1.667)kHz = 0.937kHz

1 2 2(1.868kHz)
= 2| | = 2 | |= = 0.643kHz
2 (3.6k)(0.40F)

iii) CF = 0.10F

From Graph:

= 2.874kHz = 1.656kHz

= = (2.874 1.656)kHz = 1.218kHz

17
fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH C F

8 16(2.059kHz)
= 2| | = 2 | |= = 1.868kHz
9 (9)

1 = 1.736kHz 2 = 2.841kHz

= 2 1 = (2.841 1.736)kHz = 1.105kHz

1 2 2(1.868kHz)
= 2| | = 2 | |= = 1.285kHz
2 (3.6k)(0.10F)

RESULT:
Lock Range, BL (kHz) Capture Range, BC (kHz)
CF (F)
Observed Calculated Observed Calculated
0.20 0.977 1.868 0.943 1.285
0.40 1.009 1.868 0.643 0.909
0.10 1.218 1.868 1.105 1.818

18
fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH R T

VARIATION OF LOCK RANGE AND

CAPTURE RANGE WITH RT
AIM:
Study the variation of lock range and capture range with timing resistor RT.

APPARATUS:
IC-565; 9V Dual Power Supply; Resistors R1 = 4.7k, R2 = 4.7k (Pot.), R3 = R4 = 10k; Capacitor
CF = 0.40F, CT = 0.02F, C = 1.08F; Function Generator; CRO/DSO.

PROCEDURE:
10. Make the circuit as in experiment 2.1 (Fig. 2.1.1), connect frequency generator to pin 2
through a capacitor.
11. The Fin was initially kept at some low value and was a square wave.
12. The frequency Fin was then increased and the output at C was noted.
13. For a particular RT, lower lock point frequency ( ), upper lock point frequency ( ), lower
capture point frequency ( ), upper capture point frequency ( ) was noted.
14. Free running frequency was also noted by switching off the frequency generator (a
key can be used for convenience).
15. Repeat the experiment for several different values of RT.

OBSERVATIONS:
=
=

RT (k)
(kHz) (kHz)
(kHz) (kHz)
18.30 1.163 0.561 1.235 0.462
15.41 1.333 0.699 1.493 0.546
14.93 1.370 0.719 1.538 0.606
13.12 1.539 0.819 1.724 0.613
11.38 1.724 0.990 1.963 0.704
9.80 1.923 1.162 2.272 0.828
Table 2.3.1

19
fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH R T

CALCULATIONS:
CT = 0.02F, CF = 0.36F

1. RT = 18.30k
1 1
= = = 0.738kHz
3.7 3.7(18.30 103 )(0.02 106 )

= = (1.235 0.462)kHz = 0.773kHz

8 16(0.738kHz)
= 2| | = 2 | |= = 0.656kHz
9 (9)

= = (1.163 0.561)kHz = 0.602kHz

1 2 2(0.328kHz)
= 2| | = 2 | |= = 0.401kHz
2 (3.6k)(0.36F)

2. RT = 15.41k
1 1
= = = 0.877kHz
3.7 3.7(15.41 103 )(0.02 106 )

= = (1.493 0.546)kHz = 0.947kHz

8 16(0.877kHz)
= 2| | = 2 | |= = 0.780kHz
9 (9)

= = (1.333 0.699)kHz = 0.634kHz

1 2 2(0.317kHz)
= 2| | = 2 | |= = 0.395kHz
2 (3.6k)(0.36F)

3. RT = 14.93k
1 1
= = = 0.905kHz
3.7 3.7(14.93 103 )(0.02 106 )
= = (1.538 0.606)kHz = 0.932kHz
8 16(0.905kHz)
= 2| | = 2 | |= = 0.804kHz
9 (9)
= = (1.370 0.719)kHz = 0.615kHz

20
fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH R T

1 2 2(0.402kHz)
= 2| | = 2 | |= = 0.444kHz
2 (3.6k)(0.36F)

4. RT = 13.12k
1 1
= = = 1.029kHz
3.7 3.7(13.12 103 )(0.02 106 )

= = (1.724 0.613)kHz = 1.111kHz

8 16(0.877kHz)
= 2| | = 2 | |= = 0.916kHz
9 (9)

= = (1.539 0.819)kHz = 0.720kHz

1 2 2(0.458kHz)
= 2| | = 2 | |= = 0.474kHz
2 (3.6k)(0.36F)

5. RT = 11.38k
1 1
= = = 1.188kHz
3.7 3.7(11.38 103 )(0.02 106 )

= = (1.963 0.704)kHz = 1.259kHz

8 16(0.877kHz)
= 2| | = 2 | |= = 1.056kHz
9 (9)

= = (1.724 0.990)kHz = 0.734kHz

1 2 2(0.528kHz)
= 2| | = 2 | |= = 0.509kHz
2 3.6k)(0.36F)
(

6. RT = 9.80k
1 1
= = = 1.379kHz
3.7 3.7(9.80 103 )(0.02 106 )

= = (2.272 0.828)kHz = 1.444kHz

8 16(1.379kHz)
= 2| | = 2 | |= = 1.225kH
9 (9)

21
fo|q r VARIATION OF LOCK RANGE AND CAPTURE RANGE WITH R T

= = (1.923 1.162)kHz = 0.761kHz

1 2 2(0.614kHz)
= 2| | = 2 | |= = 0.549kHz
2 (3.6k)(0.36F)

RT (k)
(kHz) (kHz)
(kHz) (kHz)
(kHz)
18.30 0.738 0.773 0.656 0.602 0.401
15.41 0.877 0.947 0.780 0.634 0.395
14.93 0.905 0.932 0.804 0.615 0.444
13.12 1.029 1.111 0.916 0.720 0.474
11.38 1.188 1.259 1.056 0.734 0.509
9.80 1.379 1.444 1.225 0.761 0.549
Table 2.3.2

RESULT:
From Table 2.3.2 following results were derived:

1. With increase in RT, free running frequency decreases.

2. The experimental values and calculated values of lock range are in conformity.
3. For lower RT, we have broader lock range.
4. The experimental values and calculated values of capture range BC are in good conformity.

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fo|q r APPLICATIONS OF PLL

APPLICATIONS OF PLL
The output from a PLL system can be obtained either as the voltage signal VC(t) corresponding to
the error voltage in the feedback loop, or as a frequency signal at VCO output terminal. The
voltage output is used in frequency discriminator applications whereas the frequency output is
used in signal conditioning, frequency synthesis or clock recovery applications.

Consider the case of voltage output. When PLL is locked to an input frequency, the error voltage
VC(t) is proportional to (fS - fO). If the input frequency is varied as in the case of FM signal, V C will
also vary to maintain the lock. Thus, the voltage output serves as a frequency discriminator which
converts the input frequency changes to voltage changes.

In the case of frequency output, if the input signal is comprised of many frequency components
corrupted with noise and other disturbances, the PLL can be made to lock, selectively on one
particular frequency component at the input. The output of VCO would then regenerate that
particular frequency (because of LPF which gives output for beat frequency) and attenuate
heavily other frequencies. VCO output thus can be used for regenerating or reconditioning a
desired frequency signal (which is weak and buried in noise) out of many undesirable frequency
signals.

Some of the typical applications of PLL are discussed below.

FREQUENCY MULTIPLIER:
Out of huge number of exciting and interesting uses of PLL frequency multiplier is one in
operations where a fixed input is fed and a fixed output is obtained whose frequency is a whole
number multiple of input frequency hence it is called as Frequency multiplier.

The multiplication of frequency can also be observed when the input frequency is varying within
a given range. In this case the output frequency also varies in tune with the variation in input
frequency. However, the range of variation in output frequencies is also the same time integral
multiple of the input range as the multiplication factor for the multiplier is designed. Thus, in this
case the device shifts the input frequency spectrum to a higher frequency spectrum as
determined by the multiplication factor, and also broadens the input spectrum range by the same
factor. Thus, in this mode of operation it would be right to call the circuit Spectrum filter that
can be understood from the following:

23
fo|q r APPLICATIONS OF PLL

Fout output spectrum width

= ,
Fin input spectrum width
Fout
or =N;
Fin

In this application, the loop is broken and a frequency divider network is inserted between VCO
and phase detector as shown in figure below. This is used in locked range because during the lock
the phase detector locks the divider output to the input frequency therefore input frequencies is
same as divider output to the input frequency and so it will be N times the input frequency.

Fig. 2.4.1

Since the output of frequency divider is locked to input frequency fin, the VCO is actually running
at a multiple of the input frequency. The desired amount of multiplication can be obtained by
selecting a proper N network.

Fout
Input to phase detector, Fin = ,
N
Fout =N Fin

First adjust the Fin range and then adjust the free running frequency Fout of the VCO by means of
R1 and C1.

Fig. 2.4.2

24
fo|q r APPLICATIONS OF PLL

In the following spectrum we are going to demonstrate a 5 times multiplier circuit and so need
a binary counter which are used to perfect the job of frequency divider. One such counter is 7940
which is a 4-bit counter. Between pin no.4 and 5 the loop is broken i.e. N network is inserted. In
this case we have connected IC 7490 as 5 network.

IC 7490:
The 7490 is a TTL MSI decode counter which can be configured to operate as a divider range
divide by 2 to divide by 10. We use it as a divide by 5 network.

Fig. 2.4.3

Now in order to make a divide by 5 network all we need to do is ground pin 2,3,6,7 and 10.
Provide +Vcc to pin 5 which is +5V. Provide input into pin 1 and draw the output from pin 11.

The output of VCO at pin no. 4 is not sufficient to drive IC so a transistor is used in-between to
increase the drive. Transistor is in CE configuration so there is current gain at collector to drive
IC.

Also, very important to note is that to be able to observe the multiplier operation it is necessary
the VCO frequency spectrum width should be greater than or equal to 5 times the spectrum width
of input frequency. Also 5 times of mid frequency of input range should correspond of the VCO.
Thus, in order to ascertain adjust the values of timing capacitor CT and RT accordingly.

25
fo|q r APPLICATIONS OF PLL

Now we proceed to demonstrate the working of the multiplier circuit. We will perform 2 stages
of experiment. Relating to the same. In the first stage we will verify the working of divide by 5
networks by connecting it to the output of freely running PLL and then taking the reading of
various values of RT. Thereafter in second stage we will provide input frequency to the phase
detector of PLL and run a complete cycle a frequency to obtain to see whether during the lock
the VCO output is or not 5 times of input frequency.

26
fo|q r DIVIDE BY 5 NETWORK

DIVIDE BY 5 NETWORK
AIM:
To verify the working of divide by 5 network using the free running output of PLL for different
values of RT.

APPARATUS:
IC-565, IC-7940, Resistors R1 = 4.7k, R2 = 4.7k (Pot.), R3 = R4 = 1k, Capacitor CF = 0.40F, CT =
0.02F, 9V Dual power supply, 5V DC power supply, CRO/DSO.

CIRCUIT DIAGRAM:

Fig. 2.4.1.1

27
fo|q r DIVIDE BY 5 NETWORK

PROCEDURE:
1. This circuit shown in Fig. 2.4.1.1 is connected on a breadboard/chassis.
2. Initially no input is applied for free running mode.
3. Record the frequency at pin 4 of IC-565 and pin 11 of IC-7490 for various (increasing)
values of RT.

OBSERVATIONS:
RT = R 1 + R 2



= =
(k) . Observed Observed
Calculated (kHz) Calculated (Hz)
(kHz) (Hz)
5.30 2.550 2.977 595.4 588.2
6.71 2.013 2.314 462.8 469.0
7.30 1.851 2.083 416.6 412.5
7.95 1.700 1.984 396.8 387.6
8.13 1.662 1.950 390.0 382.8
8.82 1.532 1.196 239.2 231.0
9.35 1.445 1.724 344.8 342.9
9.88 1.368 1.479 295.8 299.8
11.99 1.127 1.252 256.4 263.1
12.35 1.078 1.220 244.0 248.8
Table 2.4.1.1

CALCULATIONS:
2.977+1.220
Mid Frequency, = ( ) kHz = 2.099kHz
2

Corresponding to this frequency, = 8.05k

To a good approximation, fmid is close to 2.083kHz (from observations) obtained with RT = 7.30k.

RESULT:
1. The calculated and observed values of fVCO for various RT matches to good extent.
2. Also, the experiment observations at divider output matches with expected to good degree.

28
fo|q r LOCK RANGE AND CAPTURE RANGE

LOCK RANGE AND CAPTURE RANGE

AIM:
To observe and analyse lock range and capture range.

APPARATUS:
IC-565, IC-7940, Resistors R1 = 4.7k, R2 = 4.7k (Pot.), R3 = R4 = 1k, Capacitor CF = 0.40F, CT =
0.02F, 9V Dual power supply, 5V DC power supply, Function generator, CRO/DSO.

PROCEDURE:
16. Following modifications were made to the circuit made in experiment 2.4.1 (Fig. 2.4.1.1)
i) Frequency generator is connected to Pin 2 of IC 565 through a capacitor
ii) CH1 of oscilloscope is connected across the input frequency
iii) RT = 6.71k is used.
17. Starting from very low frequency we started taking observations of input frequency and
the divide by 5 network output frequency.
18. The frequency was increased slowly and the output was noted until the two frequencies
came out of lock after remaining in lock over a range of frequency.
19. Now the input frequency was gradually decreased and the output was noted until the two
frequencies came out of lock after remaining in lock over a range of frequency.

OBSERVATIONS:
INCREASING INPUT FREQUENCY DECREASING INPUT FREQUENCY
Input frequency, 5 output frequency, Input frequency, 5 output frequency,
FIN (Hz) FDIV (Hz) FIN (Hz) FDIV (Hz)
283.3 414.9 700.2 482.1
292.4 520.8 656.2 497.2
307.7 507.7 602.4 521.6
312.5 366.3 564.3 543.5
321.5 369.0 547.0 547.0
332.2 362.2 515.5 515.5
341.3 341.3 482.2 482.2
393.7 393.7 454.5 454.5
473.9 473.9 398.8 398.8
482.6 482.6 372.1 372.1
521.9 521.9 350.1 350.1
543.4 543.4 343.4 405.2

29
fo|q r LOCK RANGE AND CAPTURE RANGE

547.0 547.0 318.1 389.1

548.2 548.2 301.9 322.1
550.7 548.2 288.8 251.6
561.3 525.7 276.1 242.4
639.2 529.4
684.0 464.2
Table 2.4.2.1

CALCULATIONS:
From Graph:

= 548.2Hz = 341.3Hz

= = (548.2 341.3)Hz = 206.9Hz

8 16(2.314kHz)
= 2| | = 2 | |= = 2.057kHz
9 (9)

1 = 350.1Hz 2 = 570.0Hz

= 2 1 = (570.0 350.1)Hz = 219.9Hz

30
fo|q r LOCK RANGE AND CAPTURE RANGE

1 2 2(1.028kHz)
= 2| | = 2 | |= = 0.711kHz
2 (3.6k)(0.36F)

RESULT:
Now according to the theory of multiplier, the range of frequencies available at the 5 network
output should be a band of frequencies 1/5th of the VCO output.
2.057kHz
Therefore, = = 411.4Hz
5

Moreover, we dont expect the capture range depends only on the cutoff frequency of the low
pass filter which has not been changed.

Thus, the capture range remains what it initially was i.e. Hz which becomes more the lock range
at 5 output. But as per the theory developed for the PLL, capture range must be less than lock
range and therefore in such a case we expect that the capture range becomes redundant and
basically merges with the lock range.

Now unlike, what was expected by the modified lock range, its value does not become 1/5 th of
the VCO range in fact, it has become 1/10th of that.

So, the discrepancy in the observed value of modified range can be explained by the fact that
since the LPF band width has remained the same and also the random fluctuation in the input
frequency do not decrease proportionally with the input frequency, so in the present mode of
operation a good amount of fluctuation in the input is there which even gets passed through the
LPF. Now the fluctuation gets aggravated by the same factor. This causes instability at the edge
frequency of the otherwise valid range and hence the stable range which is the observed range,
becomes significantly less than the expected.

31
fo|q r BIBLIOGRAPHY

BIBLIOGRAPHY

REFERENCE BOOKS:
1. Operational Amplifier and linear Integrated Circuits, Ramakant A. Gaykward.

INTERNET SOURCES:
1. https://en.wikipedia.org
2. http://www.circuitstoday.com
3. www.electronics-notes.com
4. http://www.radio-electronics.com

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