Quartus Schematic

Quartus II Schematics Tutorial
by Gregory L. Moss
UNIT 5 – SCHEMATIC CAPTURE OF COMBINATIONAL
LOGIC CIRCUITS WITH QUARTUS II
Example 5-1
Create a multiplier circuit that will output the product of any 3-bit input number (0 through 7) multiplied
by the constant 3. The truth table is shown in Table 5-1. The schematic is given in Fig. 5-2.
A B C P4 P3 P2 P1 P0
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 1
0 1 0 0 0 1 1 0
0 1 1 0 1 0 0 1
1 0 0 0 1 1 0 0
1 0 1 0 1 1 1 1
1 1 0 1 0 0 1 0
1 1 1 1 0 1 0 1
Table 5-1 Truth table for example 5-1
A B C
P4
P3
P2
P1
P0
Fig. 5-2 Logic circuit for example 5-1
Copyright © 2007 by Pearson Education 1

Schematic Capture of Combinational Logic Circuits with Quartus II
Quartus II procedures for Example 5-1
Start a New Design Project
1. Start Quartus II. The main screen, shown below, will open.

2. Select the File menu and choose “New Project Wizard.” The Introduction window will open. A
new folder (directory) should be created for each separate design project. There will be
many files associated with a project and they should all be placed in the same folder. Do not
duplicate design file names for a project. The New Project Wizard will guide you in setting up
the design project. Click the Next button.

3. The Directory, Name, Top-Level Entity dialog box opens. Type the working directory as shown
below or use the working directory specified by your lab instructor. The project name and top-
level design entity name should be typed as shown in the dialog box. Click the Next button.

4. You will be asked if the directory should be created. Click the Yes button and the Add Files
dialog box will open. We do not have any additional design files to add to the project, so click
the Next button.

5. The Family & Device Settings dialog box opens. Check with your instructor on the specific
hardware that you will be using in lab. Select the Family in the drop-down box. Specify a
Specific device and select the target device from the list of Available devices. Click Next. The
MAX7000S family and EPM7128SLC84-7 device were selected in the dialog box below.

6. The EDA Tool Settings dialog box opens. There are no additional tools to use, so click Next.

7. The Summary window opens. Click Finish. This is the final screen to set up the information for
a new project. Project settings may be changed in the Settings dialog box, which can be opened
from the Assignments menu.

Create a Block Diagram File
8. Open a New File using either the File menu or the toolbar button. Select “Block
Diagram/Schematic File” in the dialog box for “Device Design Files” and then click OK.

9. A blank worksheet on which we will draw our schematic appears. Open the File menu and
choose “Save As.” The Save As dialog box opens. The file name should be mult_by_3.bdf and
the folder to save it in should be example5_1 as shown below. Schematic files have a .bdf file
extension. Make sure the “Add file to current project” is checked and click Save.

10. The Quartus II Block Editor will be used to draw the schematic for our project. Click the Symbol
Tool button (gate symbol) on the left side of the Block Editor window (or double-click the left
mouse button anywhere in the drawing area or right-click the mouse, choose “Insert” and then
“Symbol”) and the Symbol dialog box will appear. Open the set of folders for Libraries,
Primitives, and Logic and select and2. Check “Repeat-insert mode” because we will need to
place five copies of a 2-input AND gate in our schematic (see Fig. 5-2). Click OK. A 2-input
AND should appear next to the drawing cursor in the Block Editor window.

11. Each time the left mouse button is clicked, another 2-input AND will be placed on the worksheet
at the position of the drawing cursor. Place five 2-input AND gates on the drawing sheet. When
finished, click the right mouse button and select Cancel. To move any of the AND gates, point
the cursor at the symbol, press and hold the left mouse button down, drag the symbol to the
desired position on the drawing sheet, and release the button. To delete a symbol, select the
symbol by pointing the cursor at it and clicking the left mouse button and then pressing the Delete
key on the keyboard (or opening the Edit menu and choosing “Delete”).
12. Open the Symbol dialog box (by clicking the Symbol Tool button). Choose the and3 gate and
place two copies in the Block Editor window. The last symbol used will always be inserted in the
Symbol Name box. You will save some time if you place all duplicate symbols before changing
to a different symbol. You can also select (highlight) existing components and use the Copy and
Paste buttons on the toolbar. A single click of the left mouse button will identify the insertion
point for the Paste operation. Place the remaining components (or2, or3, & not) for this project
(see Fig. 5-2).
13. Remember the standard operating procedure when using computers is to periodically save your
work, just in case!

14. Place inputs and outputs in the schematic. Open the Symbol dialog box, close the logic library,
open the pin library, and select input. Place three input symbols on the worksheet, then right-
click the mouse an select Cancel when finished. Repeat to place five output symbols.

15. Neatly arrange the components in the Block Editor window (see below). Label the input and
output node names by double-clicking on the default pin name “PIN_NAME” with the left mouse
button and then typing the new text. Press Enter when completed with each label.
16. Draw the wires to make the necessary circuit connections. Point the mouse cursor at a device
connection (pointer will turn into a cross-hair), hold down the left mouse button, move the cursor
towards the desired connection point, and release the mouse button. If you need more than one
right-angle turn in the wire, you will need to end the wire (by releasing the button) and then
continue drawing the wire from that point. When you create a T intersection, connection dots are
automatically inserted. Components or wires can be moved by selecting them (point and click on
it once with the left mouse button) and dragging them to the desired location. To delete any part
of the drawing, select and press the delete key. Save the file.
a INPUT
VCC AND2
OUTPUT p4
NOT inst
b INPUT
VCC AND3
inst10
OR2
OUTPUT p3
inst8
c INPUT
VCC AND2 inst5
NOT
inst1
inst13
AND2 OR3
OUTPUT p2
inst2 inst7
AND3
inst9
AND2
OR2
inst3 OUTPUT p1
AND2
inst6
NOT
inst4
inst14
OUTPUT p0

Check for Errors
17. When you are finished with the wiring, click on the Analysis and Synthesis button (or choose
“Analyze Current File” in the Processing menu). Quartus II will check for errors (such as opens
and shorts) in the design file and report the results.
18. The message box will indicate if the “Analysis & Synthesis was successful” or if there are errors
(see step 19). Click OK.

19. If you have errors, click OK to “Analysis & Synthesis was NOT successful” message, then point
the cursor to the red error message in the message window at the bottom of the screen and open
the message menu by clicking the right mouse button. Context-sensitive help is available if you
choose Help from the menu. If you choose Locate in the message menu and then Locate in
Design File (or double-click the left mouse button on the error message), the location of the error
in the design file will be highlighted. Make the necessary corrections to the schematic. Ask your
lab instructor to check your schematic. Repeat the design Analysis and Synthesis to make sure
there are no more errors.

20. If you did not have any errors in the file, create some or have your lab instructor insert errors so
that you can observe how to handle them. Return to the design file by clicking the
mult_by_3.bdf tab or using the Window menu or double-clicking the left mouse button on
mult_by_3 in the Project Navigator. Create an error in the design file by shorting two outputs
together or leaving an input unconnected. Repeat the design Analysis and Synthesis. When
finished exploring, correct any errors as outlined in step 19.

Compile the Project
21. Click the Start Compilation button (or open the Processing menu and choose “Start
Compilation”). The design will be compiled from the top-level of the project as defined by the
current project name. The current project name is always given in the banner at the top of the
screen. There is only one design file for this project since it is a “flat design.”

22. If the compilation was successful, click OK. If errors are reported, consult your lab instructor.

23. Expand the Fitter report and select Pin-Out File. This file is a listing of the current pin
assignments made by Quartus for this design. This information will be needed to wire the PLD to
switches and lights for testing. Pin assignments may change if the design is recompiled (see the
Back-Annotating the Project section after this example). Pin assignments may also entered by the
designer instead of being determined by Quartus, but the project must then be recompiled. Select
the Resource Section of the Fitter report. Determine the percentage usage of various resources
within the chip. Input and Output pin numbers are also available in the Resource Section.

Simulate the Design
24. Simulation inputs are drawn in a Vector Waveform File (.vwf). Create an input file for the
simulator by clicking the New file button on the toolbar or choosing “New” in the File menu.
Select “Vector Waveform File” listed under the “Other Files” tab in the New dialog box and click
OK.

25. Click the Save button on the toolbar (or in the File menu). The Save As dialog box should
indicate that File name mult_by_3.vwf is to be added to the current project in the Example5_1
folder. Click Save.

26. Specify an end time of 8 μs for the simulation file. Open the Edit menu and choose “End Time.”
Enter 8 and select μs in the End Time dialog box and click OK.
27. Specify a grid size of 1 μs for the simulation file. Open the Edit menu again and choose “Grid
Size.” Enter 1 and select μs in the Grid Size dialog box for Time period and click OK.

28. Open the View menu and choose “Fit in Window.”

29. Select inputs and outputs for the project simulation using the Node Finder. Open the View menu
and choose “Node Finder” under “Utility Windows.”

30. Click the List button in the Node Finder window. Select the desired input and output node
Names with the left mouse button, holding the Shift key (for groups of nodes) or the CTRL key
(to add individual nodes). Point to a selected Node handle (located at the left in the Node Finder
window under Name and labeled with I or O) in the Node Finder window, hold down the left
mouse button, and drag the highlighted nodes to the Name field in the Vector Waveform window.
The selected nodes will be added to the Vector Waveform File. Close the Node Finder window
by clicking the 7 close window button.

31. Create the desired input waveforms for the project simulation. We will be applying all eight
possible combinations for the circuit inputs a b c using a binary count sequence as shown below.
Edit the waveforms by selecting a time segment of an input waveform to be changed (point the
mouse cursor at the beginning of a time segment to be changed, hold down the left mouse button,
and drag to the end of the desired time). The time segment selected will be highlighted.
Additional time segments can be selected by holding down the CTRL key while dragging through
a time segment with the left mouse button pressed. Clicking the editing buttons on the left of the
Simulation Waveforms window can change the logic levels for the selected time segments.
Create the high pulses for the desired vector waveform by clicking on the 1 (Forcing High)
button.
32. Save the mult_by_3.vwf file.
33. Simulate the project by clicking the Start Simulation button in the toolbar or opening the
Processing menu and choosing “Start Simulation.”

34. Click OK when the “Simulator was successful” message appears. The simulation results can be
seen in the Simulation Waveforms window. If necessary, open the View menu and choose “Fit in
Window” to see the entire simulation results. You may also wish to toggle the Full Screen button
(or open the View menu and choose “Full Screen”) to maximize the Simulation Waveforms
window. Another click of Full Screen will return to the standard multi-window display. Check
the simulated design output to determine if it matches the theoretical results given in Table 5-1.
If your results are incorrect, you have an error in the design and it will be necessary to correct the
schematic (mult_by_3.gdf) and recompile.

Manually assigning pin numbers
35. After determining that the project simulation is correct, you may find it necessary to change some
of the pin numbers. To manually assign pin numbers, open the Assignments menu and choose
“Pins.” The Assignment Editor will open.

36. Double-click the highlighted field under the To column. The input and output signal names will
appear in a drop-down list. Point the cursor to the desired signal and click the left mouse button.
The selected signal will be placed in the field. Press Enter and the highlighted field will move
down to the next row. Double-click the new field to select the next signal. Repeat until all
desired signals have been entered in the To column.
37. When all signals have been entered, double-click the field in the first row under the Location
column. The pin numbers for our selected device (specified in the New Project Wizard) will
appear in a drop-down list. Scroll down to pin 34 and click the left mouse button. Note: Your
instructor may specify different pin numbers due to the hardware used in your lab. Press Enter.

38. Repeat this procedure to complete the pin assignments shown below for this design.
39. Save the pin assignments when finished. Open the mult_by_3.bdf window (by clicking on the
labeled tab) and display the pin assignments on the schematic by enabling Show Pin and Location
Assignments in the View menu.
40. Recompile the project to replace the original pin assignments made by Quartus. Click Yes if
asked to Save changes to mult_by_3.bdf. Click OK for the “Full Compilation was successful”
message. Verify the new pin assignments by checking the Pin-Out File in the Fitter report.

Program a PLD
41. Open the Programmer window by clicking on the Programmer button (or choose “Programmer”
from the Tools menu). If this is the first time for programming a PLD on this computer, the
programmer window will report No Hardware and it will be necessary to setup the hardware for
programming. Skip step 41 if ByteBlaster hardware has already been set up on this computer.

42. If the programmer window reports No Hardware, click the Hardware Setup button – otherwise,
proceed to step 43. Click the Add Hardware button on the Hardware Setup dialog box. Select
“ByteBlasterMV or ByteBlaster II” in the drop-down box for Hardware type and “LPT1” for
Port. Click OK and return to the Hardware Setup dialog box. Select ByteBlaster in the
“Currently selected hardware” drop-down box. Click Close.
43. Attach the PLD trainer board to the PC’s parallel (printer) port and power the board. Make sure
to use the correct power supply voltage. Check with your lab instructor for instructions on
your specific brand and model of PLD trainer. Altera boards use an interface cable called a
ByteBlaster. To prevent damaging the PLD, make sure that output pins have not been connected
to input sources (such as logic switches).

44. Select Program/Configure and Verify functions for the programmer by clicking the appropriate
boxes. A function will be selected if a check mark is in the box. The PLD will be programmed
and then it will be checked to verify that it has stored the correct programming information.
Click the Start button in the Programmer window. When the Progress bar shows 100%, the
programming is complete and the PLD is ready for testing.
45. Read this step carefully and completely BEFORE wiring the chip.
Check with your lab instructor for instructions on your specific brand and model of PLD
trainer. Turn off the power to the board (the EPM7128S is “non-volatile” and will retain the
programmed design when the power is turned off). Connect the chip’s inputs to logic switches
and outputs to lamp monitors according to the pin assignments listed in the Pin-Out File. Most
PLD trainers have pin 83 connected to a crystal oscillator (which is not being used in this
project). The compiler has no way of knowing that pin 83 might already be connected to a signal
source! Do not short the oscillator’s output to ground! Power supply connections (VCC and
GND) to the chip typically are already provided by the trainer’s printed circuit board. Since the
dedicated input pins 1, 2, and 84 are not used in this project, they should also be connected to
GND as noted in the Pin-Out file. Connect the inputs to appropriate logic switches and the
outputs to logic display lamps. Ask your lab instructor to check your wiring before continuing
to the final step.
46. After consulting with the lab instructor, turn the power back on and test your design. Compare
your circuit’s operation with the theoretical truth table (Table 5-1). Does it match? If your circuit
works correctly, demo your project to the lab instructor. If it is necessary to modify (correct?) the
design, you may wish to lock the input and output pin assignments by “back-annotating” the
project (see Quartus Notes) before recompiling. If you have already manually assigned the pins,
it will not be necessary to back-annotate.

Example 5-2
Create a 1-out-of-4 data selector circuit using a circuit design for a 1-out-of-2 data selector. A data
selector uses a control input to select a single data input (from several choices) to be routed to the output
of the circuit. See Fig. 5-3 and Table 5-2. If the control SEL is low, then output Y = D0; otherwise Y =
D1. A data selector is also called a multiplexer.
SEL
D0
Y
D1
Fig. 5-3 1-out-of-2 data selector circuit for example 5-2
SEL Y
0 D0
1 D1
Table 5-2 Truth table for 1-out-of-2 data selector circuit
A 1-out-of-4 data selector can be constructed by combining two levels of the 1-out-of-2 data selector
circuit design (see Fig. 5-4). This design can be easily implemented in a hierarchical fashion.
S1
S0
SEL
D0 D0 data_sel2 Y
D1 D1 SEL
D0 data_sel2 Y Y
D1
SEL
D2 D0 data_sel2 Y
D3 D1
Fig. 5-4 Block diagram for 1-out-of-4 data selector circuit

Quartus II procedures for Example 5-2
Start a New Design Project
1. Start Quartus II. The main screen, shown below, will open.

2. Select the File menu and click New Project Wizard. The Introduction window will open.
A new folder (directory) should be created for each separate design project. There
will be many files associated with a project and they should all be placed in the same
folder. Do not duplicate design file names for a project. The New Project Wizard will
guide you in setting up the design project. Click the Next button.

3. The Directory, Name, Top-Level Entity dialog box opens. Type the working directory as
shown below or use the working directory specified by your lab instructor. The project
name and top-level design entity name should be typed as shown in the dialog box. Click
the Next button.

4. You will be asked if the directory should be created. Click the Yes button and the Add
Files dialog box will open. We do not have any additional design files to add to the
project, so click the Next button.

5. The Family & Device Settings dialog box opens. Check with your instructor on the
specific hardware that you will be using in lab. Select the Family in the drop-down box.
Specify a Specific device and select the target device from the list of Available devices.
Click Next. The MAX7000S family and EPM7128SLC84-7 device were selected in the
dialog box below.

6. The EDA Tool Settings dialog box opens. There are no additional tools to use, so click
Next.

7. The Summary window opens. Click Finish. This is the final screen to set up the
information for a new project. Project settings may be changed in the Settings dialog
box, which can be opened from the Assignments menu.

Create a Block Diagram File
8. Open a New File using either the File menu or the toolbar button. Select “Block

9. A blank worksheet on which we will draw our schematic appears. Open the File menu
and select Save As. The Save As dialog box opens. The file name should be
data_sel2.bdf and the folder to save it in should be example5_2 as shown below.
Schematic files have a .bdf file extension. Make sure the Add file to current project is
checked and click Save.

10. The Quartus II Block Editor will be used to draw the schematic for our project. Click the
Symbol Tool button (gate symbol) on the left side of the Block Editor window (or
double-click the left mouse button anywhere in the drawing area or right-click the mouse,
choose Insert and then Symbol) and the Symbol dialog box will appear. Open the set of
folders for Libraries, Primitives, and Logic and select and2. Check “Repeat-insert
mode” because we will need to place two copies of a 2-input AND gate in our schematic
(see Fig. 5-3). Click OK. A 2-input AND should appear next to the drawing cursor in
the Block Editor window.

11. Each time the left mouse button is clicked, another 2-input AND will be placed on the
worksheet at the position of the drawing cursor. Place two 2-input AND gates on the
drawing sheet. When finished, click the right mouse button and select Cancel. To move
any of the AND gates, point the cursor at the symbol, press and hold the left mouse
button down, drag the symbol to the desired position on the drawing sheet, and release
the button. To delete a symbol, select the symbol by pointing the cursor at it and clicking
the left mouse button and then pressing the Delete key on the keyboard (or opening the
Edit menu and selecting Delete).
12. Open the Symbol dialog box (by clicking the Symbol Tool button). Choose the or2 gate
and place it in the Block Editor window. The last symbol used will always be inserted in
the Symbol Name box. Also place the not gate for this project (see Fig. 5-3).
13. Remember to periodically save your work!

14. Place inputs and outputs in the schematic. Open the Symbol dialog box, close the Logic
library, open the Pin library, and select input. Place three input symbols on the
worksheet, then right-click the mouse and select Cancel when finished. Repeat to place
one output symbol.

15. Neatly arrange the components in the Block Editor window (see below). Label the input
and output node names by double-clicking on the default pin name “PIN_NAME” with
the left mouse button and then typing the new text. Press Enter when completed with
each label.
16. Draw the wires to make the necessary circuit connections. Point the mouse cursor at a
device connection (pointer will turn into a cross-hair), hold down the left mouse button,
move the cursor towards the desired connection point, and release the mouse button. If
you need more than one right-angle turn in the wire, end the wire by releasing the button
and then continue drawing the wire from that point. Connection dots are automatically
inserted at T intersections. Components or wires can be moved by selecting them (point
and click on it once with the left mouse button) and dragging them to the desired
location. To delete any part of the drawing, select and press the delete key.
NOT
sel INPUT
VCC AND2
inst3
d0 INPUT
VCC OR2
inst
OUTPUT y
AND2
inst2
d1 INPUT
VCC
inst1

Check for Errors
17. When you are finished with the wiring, click on the Analysis and Synthesis button (or
choose “Analyze Current File” in the Processing menu). Quartus II will check for errors
(such as opens and shorts) in the design file and report the results.

18. The message box will indicate if the “Analysis & Synthesis was successful” or if there
are errors (see step 20). Click OK.

19. If you have errors, click OK to “Analysis & Synthesis was NOT successful” message,
then point the cursor to the red error message in the message window at the bottom of the
screen and open the message menu by clicking the right mouse button. Context-sensitive
help is available if you choose Help from the menu. If you choose Locate in the message
menu and then Locate in Design File (or double-click the left mouse button on the error
message), the location of the error in the design file will be highlighted. Make the
necessary corrections to the schematic. Ask your lab instructor to check your schematic.
Repeat the design Analysis and Synthesis to make sure there are no more errors.

20. It is important to note that the analysis performed by the compiler does not verify that the
design is logically correct, only that it is wired correctly. Appropriate simulation and
bench testing of a prototype design are needed to verify that the circuit has been correctly
designed. Since this is an example of a hierarchical design project, the design block that
we have just created will actually become a lower-level block in the overall design. We
have a decision to make at this point in our design flow. If we wish to verify this design
block, it must be compiled before it can be simulated. Simulating lower-level design
blocks is actually an excellent design strategy for complex designs. We can work our
way up to the complete system, simulating individual blocks along the way and making
any necessary design corrections before we get to the more complex top-level of the
system. In a hierarchical design, compiling from the top-level of a design will compile
all lower-level blocks in the system. Likewise, simulations of the top-level of a design
will include all blocks within the system. Since this is a fairly simple design block, we
will choose to forego simulation at this lower-level and will, instead, continue by entering
the top-level of the overall design.

Create the Top-Level Design File
21. To be able to use a lower-level design block in a higher-level file, it is necessary to create
a symbol for the block. Open the data_sel2.bdf schematic (block design file) by
clicking the left mouse button on the appropriate main window tab (or opening the
Window menu or double-clicking the file in the Entity window).

22. Open the File menu and choose “Create/Update” and then “Create Symbol Files for
Current File.” Click OK to “Created Block Symbol File data_sel2” message.

23. Open the New Project Wizard in the File menu. Click Next on the Introduction screen.
Enter data_sel4 as the project name (and name of the top-level entity for this project).
Click the Next button and a warning message will appear. Click No since we want to use
the data_sel2 project in the new project data_sel4. We do not want to select a different
project directory.

24. Click the Add All button. Click Next.
25. We will be using the same Family and device. Click Next.
26. No other EDA tools will be used. Click Next.
27. Check the Summary and, if it is correct, click Finish.

28. Open a New File using either the File menu or the toolbar button. Choose “Block
29. A blank worksheet on which we will draw our top-level block diagram appears. Open
the File menu and choose “Save As.” The Save As dialog box should indicate that the
file named data_sel4 will be saved in the folder example5_2 as shown below. The
“Add file to current project” should be checked. Click Save.

30. Click the Symbol Tool button (gate symbol) on the left side of the Block Editor window
(or double-click the left mouse button anywhere in the drawing area or right-click the
mouse, choose “Insert” and then “Symbol”) and the Symbol dialog box will appear.
Open the Project folder and select data_sel2. Check “Repeat-insert mode” because we
will need three copies of the lower-level block for the top-level file (see Fig. 5-4). Click
OK. The symbol for data_sel2 should appear next to the drawing cursor in the Block
Editor window.

31. Each time the left mouse button is clicked, another data_sel2 symbol will be placed on
the worksheet at the position of the drawing cursor. Place three data_sel2 symbols on
the drawing sheet. When finished, click the right mouse button and select Cancel. To
move any of the symbols, point the cursor at the symbol, press and hold the left mouse
button down, drag the symbol to the desired position on the drawing sheet, and release
the button. To delete a symbol, select the symbol by pointing the cursor at it and clicking
the left mouse button and then pressing the Delete key on the keyboard (or opening the
Edit menu and selecting Delete).

32. Place inputs and outputs in the schematic. Open the Symbol dialog box, open the set of
folders for Libraries, Primitives, and Pin, and select input. Place six input symbols on
the worksheet, then right-click the mouse and select Cancel when finished. Repeat to
place one output symbol. Neatly arrange the components in the Block Editor window.
Label the input and output node names by double-clicking on the default pin name
“PIN_NAME” with the left mouse button and then typing the new text. Press Enter when
completed with each label.

33. Draw the wires to make the necessary circuit connections. Point the mouse cursor at a
device connection (pointer will turn into a cross-hair), hold down the left mouse button,
move the cursor towards the desired connection point, and release the mouse button. If
you need more than one right-angle turn in the wire, end the wire by releasing the button
and then continue drawing the wire from that point. Connection dots are automatically
inserted at T intersections. Components or wires can be moved by dragging them to the
desired location. To delete any part of the drawing, select and press the delete key.
34. Save the data_sel4.bdf file.
35. Double-click the left mouse button while pointing to one of the data_sel2 symbols in the
top-level file. This will allow you to “dive down” one layer in the design hierarchy and
bring the underlying data_sel2 design to the foreground. Return to the higher-level
design file by closing the lower-level window or clicking the tab for the higher-level
window. Note: You may edit the design of this lower layer but if you change any of the
input or output ports, you must edit and save the new symbol (right-click mouse and
choose “Open Symbol File”) and also update the symbols in the higher-level design file
(right-click mouse and choose “Update Symbol or Block”). Any changes to the logic
circuit will not be effective until the top-level design file is compiled (again).
36. Check for wiring errors. Click the Analysis and Synthesis button (or choose “Analyze
Current File” in the Processing menu). Click OK. Correct any reported errors and re-
check the design.

Compile the Project
37. Compile the top-level design. Click the Start Compilation button (or open the Processing
menu and choose “Start Compilation”). The design will be compiled from the top-level
of the project that is named in the banner at the top of the screen. This will automatically
include any lower- level blocks. Click OK. Report any errors to your lab instructor.

Simulate the Design
38. Create a Vector Waveform File (.vwf) to use in simulating the project. Click the New
file button on the toolbar (or choose “New” in the File menu). Select “Vector Waveform
File” under the “Other Files” tab in the New dialog box and click OK.

39. Specify an end time of 12.0ms and a grid size of 1.0ms for the simulation file. Open the
Edit menu and choose “End Time.” Enter 12.0 and select ms in the End Time dialog box
and click OK. Open the Edit menu again and choose “Grid Size.” Enter 1.0 and select
ms in the Grid Size dialog box for Time period and click OK.
40. Fit the Vector Waveform File in the window. Open the View menu and choose “Fit in
Window.”
41. Select inputs and outputs for the project simulation using Node Finder. Open the View
menu and choose “Node Finder” under “Utility Windows.”

42. Click the List button in the Node Finder window. Select the desired input and output
node Names with the left mouse button, holding the Shift key (for groups of nodes) or the
CTRL key (to add individual nodes). Point to a selected Node handle (located at the left
in the Node Finder window under Name and labeled with I or O) in the Node Finder
window, hold down the left mouse button, and drag the highlighted nodes to the Name
field in the Vector Waveform window. The selected nodes will be added to the Vector
Waveform File. Close the Node Finder window by clicking the 7 close window button.

43. Create a 0 through 3 count sequence for the two inputs s1 and s0 (assuming s0 is the
least significant bit). Select the desired grid time segments (drag the mouse cursor
through the time segment while holding down the left mouse button) and overwrite the
selected time segment with a Forcing High using the editing buttons on the left side of the
window. If you need to change a high back to a low, select the desired grid section and
click the Forcing Low button. When one cycle of the count sequence is complete, select
the portion of the two waveforms with the count pattern and click the Copy button in the
toolbar. Open the Edit menu and choose “Repeat Paste.” Enter 3 for the Number of
Copies in the Repeat Paste dialog box and click OK. The count pattern will be repeated
three times and will now extend to the file’s end time at 12ms.

44. Also edit the inputs for d3 d2 d1 d0 to provide three different bit patterns, one for each
count cycle of s1 s0. The waveforms can be rearranged (note that the signal order
shown below has been reversed) by selecting the waveform to be moved (point to the
waveform’s handle and click the left mouse button) and then dragging (press and hold the
left mouse button while pointing to the handle and dragging up or down to reposition,
release) it to the desired new location. Save the data_sel4.vwf file (5 “Add to current
project”) when finished.
45. Simulate the project by clicking the Start Simulation button in the toolbar (or opening the
Processing menu and choosing “Start Simulation”). Click OK for “Simulator was
successful” message. Open the View menu and choose “Fit in window.” Toggle the Full
Screen button (or open the View menu and choose “Full Screen”). Check your
simulation results to determine if the circuit is operating correctly. Show the simulation
results to your lab instructor.

Manually assigning pin numbers
46. After determining that the functional simulation is correct, you may be required to change
some of the pin numbers due to your specific brand/model of PLD trainer (check with
your lab instructor for details). To manually assign pin numbers, open the Assignments
menu and choose “Pins.” In the Assignment Editor window, double-click the highlighted
To field. Select the desired signal from the drop-down window (point cursor and click
the left mouse button) and press Enter to place the signal in the To field. Repeat until all
desired signals have been entered in the To column. Then double-click the first field in
the Location column. Scroll down the pin number list for our selected device to the
desired number for that signal and select by clicking the left mouse button. Press Enter.
Repeat for all pin assignments. Save the pin assignments when finished. Recompile the
design for the new pin assignments to take effect. Verify the pin assignments by
checking the Pin-Out File in the Fitter report.

Program a PLD
47. Open the Programmer window by clicking on the Programmer button (or choose
“Programmer” from the Tools menu). If the Programmer window indicates No
Hardware: cClick the Hardware Setup button, dClick the Add Hardware button,
eSelect “ByteBlaster…” for Hardware type and “LPT1” for Port, fclick OK, gSelect
ByteBlaster in the “Currently selected hardware” drop-down box, and hClick Close.
Continue.
48. Attach the PLD trainer board to the PC’s parallel (printer) port and power the board.
Make sure to use the correct power supply voltage. Check with your lab instructor for
instructions on your specific brand and model of PLD trainer. To prevent damaging
the PLD, make sure that output pins have not been connected to input sources (such as
logic switches).
49. Select Program/Configure and Verify functions for the programmer (5 boxes). The
PLD will be programmed and then it will be checked to verify that it has stored the
correct programming information. Click the Start button in the Programmer window.
When the Progress bar shows 100%, the programming is complete and the PLD is ready
for testing.

50. Read this step carefully and completely BEFORE wiring the chip.
Check with your lab instructor for instructions on your specific brand and model of
CPLD trainer. Turn off the power to the board (the EPM7128S is “non-volatile” and
will retain the programmed design when the power is turned off). Connect the chip’s
inputs to logic switches and outputs to lamp monitors according to the pin assignments
shown in the Pin-Out File. Most PLD trainers have pin 83 connected to a crystal
oscillator (which is not being used in this project). The compiler has no way of knowing
that pin 83 might already be connected to a signal source! Do not short the oscillator’s
output to ground! Power supply connections (VCC and GND) to the chip typically are
already provided by the trainer’s printed circuit board. Since the dedicated input pins 1,
2, and 84 are not used in this project, they should also be connected to GND as noted in
the Pin-Out File. Connect the inputs to appropriate logic switches and the outputs to
logic display lamps. Ask your lab instructor to check your wiring before continuing to
the final step.
51. After consulting with the lab instructor, turn the power back on and test your design.
Compare your circuit’s operation with this description: “The two select inputs s1 s0
should control which of the four data inputs (d0 d1 d2 d3) is routed to the output y.”
Does it match? If your circuit works correctly, demo your project to the lab instructor. If
it is necessary to modify (correct?) the design, you may wish to lock the input and output
pin assignments by “back-annotating” the project (see Quartus Notes) before
recompiling. If you have already manually assigned the pins, it will not be necessary to
back-annotate.

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Quartus II Schematics Tutorial

Table 5-1 Truth table for example 5-1

Fig. 5-2 Logic circuit for example 5-1

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Quartus II procedures for Example 5-1

Start a New Design Project

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Create a Block Diagram File

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Check for Errors

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Compile the Project

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Simulate the Design

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28. Open the View menu and choose “Fit in Window.”

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32. Save the mult_by_3.vwf file.

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Manually assigning pin numbers

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Fig. 5-3 1-out-of-2 data selector circuit for example 5-2

Table 5-2 Truth table for 1-out-of-2 data selector circuit

Fig. 5-4 Block diagram for 1-out-of-4 data selector circuit

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Quartus II procedures for Example 5-2

Start a New Design Project

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Create a Block Diagram File

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13. Remember to periodically save your work!