Chap 10

Switched-Capacitor Circuits
David Johns and Ken Martin

University of Toronto
(johns@eecg.toronto.edu)
(martin@eecg.toronto.edu)
University of Toronto 1 of 60
© D. Johns, K. Martin, 1997

Basic Building Blocks
Opamps
• Ideal opamps usually assumed.
• Important non-idealities
— dc gain: sets the accuracy of charge transfer,
hence, transfer-function accuracy.
— unity-gain freq, phase margin & slew-rate: sets
the max clocking frequency. A general rule is that
unity-gain freq should be 5 times (or more) higher
than the clock-freq.
— dc offset: Can create dc offset at output. Circuit
techniques to combat this which also reduce 1/f
noise.

Double-Poly Capacitors
metal
C1 metal
poly1
C p1 thin oxide
bottom plate C1
poly2 C p2 thick oxide
C p1 C p2
(substrate - ac ground)
cross-section view equivalent circuit
• Substantial parasitics with large bottom plate

capacitance (20 percent of C 1 )
• Also, metal-metal capacitors are used but have even
larger parasitic capacitances.

Switches
φ φ
Symbol n-channel
v1 v2 v1 v2
φ transmission
φ φ gate
v1 v2
p-channel v1 v2
φ
• Mosfet switches are good switches.
— off-resistance near GΩ range
— on-resistance in 100Ω to 5kΩ range (depends on
transistor sizing)
• However, have non-linear parasitic capacitances.

Non-Overlapping Clocks
φ1 T
V on φ φ1
V off
n–2 n–1 n n+1 t⁄T delay
1
φ2 f s ≡ --- delay
V on T
V off φ2
n – 3 ⁄ 2n – 1 ⁄ 2 n + 1 ⁄ 2 t⁄T
• Non-overlapping clocks — both clocks are never on
at same time
• Needed to ensure charge is not inadvertently lost.
• Integer values occur at end of φ 1 .
• End of φ 2 is 1/2 off integer value.

Switched-Capacitor Resistor Equivalent
φ1 φ2 R eq
V1 V2 V1 V2
C1
T
∆Q = C 1 ( V 1 – V 2 ) every clock period R eq = ------
C1
Qx = C xV x (1)
• C 1 charged to V 1 and then V 2 during each clk period.
∆Q 1 = C 1 ( V 1 – V 2 ) (2)
• Find equivalent average current
C1(V 1 – V 2)
I avg = ------------------------------- (3)
T
where T is the clk period.

Switched-Capacitor Resistor Equivalent
• For equivalent resistor circuit
V1 – V2
I eq = ------------------- (4)
R eq
• Equating two, we have
T 1
R eq = ------ = ------------ (5)
C1 C1 f s
• This equivalence is useful when looking at low-freq

portion of a SC-circuit.
• For higher frequencies, discrete-time analysis is
used.

Resistor Equivalence Example
• What is the equivalent resistance of a 5 pF
capacitance sampled at a clock frequency of 100kHz .
• Using (5), we have
1
R eq = --------------------------------------------------------- = 2MΩ
– 12 3
( 5 × 10 ) ( 100 × 10 )
• Note that a very large equivalent resistance of 2MΩ
can be realized.
• Requires only 2 transistors, a clock and a relatively
small capacitance.
• In a typical CMOS process, such a large resistor
would normally require a huge amount of silicon
area.

Parasitic-Sensitive Integrator
v c2(nT )
φ1 φ2
v cx(t) C2 φ1
v ci(t) v co(t)
v c1(t) C1
v i(n) = v ci(nT ) v o(n) = v co(nT )
• Start by looking at an integrator which IS affected by

parasitic capacitances
• Want to find output voltage at end of φ 1 in relation to
input sampled at end of φ 1 .

C2 C2
v ci(nT – T ) v ci(nT – T ⁄ 2)
C1 v co(nT – T ) C1
v co(nT – T ⁄ 2)
φ 1 on φ 2 on
• At end of φ 2
C 2 v co(nT – T ⁄ 2) = C 2 v co(nT – T ) – C 1 v ci(nT – T ) (6)
• But would like to know the output at end of φ 1
C 2 v co(nT ) = C 2 v co(nT – T ⁄ 2) (7)
• leading to
C 2 v co(nT ) = C 2 v co(nT – T ) – C 1 v ci(nT – T ) (8)

• Modify above to write
C1
v o(n) = v o(n – 1) – ------ v i(n – 1) (9)
C2
and taking z-transform and re-arranging, leads to
V o(z) C 1 1
H (z) ≡ ------------- = –  ------  ----------- (10)
V i(z) C 2 z – 1
• Note that gain-coefficient is determined by a ratio of
two capacitance values.
• Ratios of capacitors can be set VERY accurately on
an integrated circuit (within 0.1 percent)
• Leads to very accurate transfer-functions.

Typical Waveforms
φ1
φ2 t
t
v ci(t)
v cx(t)
v co(t)

Low Frequency Behavior
• Equation (10) can be re-written as
C 1  z –1 / 2
H (z) = –  ------  ---------------------------- (11)
C 2  z 1 / 2 – z –1 / 2
• To find freq response, recall
z = e jωT = cos ( ωT ) + j sin ( ωT ) (12)
ωT ωT
z 1 / 2 = cos  --------  + j sin  --------  (13)
 2   2 
ωT ωT
z – 1 / 2 = cos  --------  – j sin  --------  (14)
 2   2 
ωT ωT
cos  --------  – j sin  -------- 
jωT C 1  2   2 
H (e ) = –  ------  ---------------------------------------------------- (15)
C 2  ωT 
j2 sin --------
 2 

Low Frequency Behavior
• Above is exact but when ωT « 1 (i.e., at low freq)
jωT C 1 1
H (e ) ≅ –  ------  ----------- (16)
 C 2  jωT
• Thus, the transfer function is same as a continuous-

time integrator having a gain constant of
C1 1
K I ≅ ------ --- (17)
C2 T
which is a function of the integrator capacitor ratio

and clock frequency only.

Parasitic Capacitance Effects
C p3 C p4
C2
φ1 φ2
φ1
v i(n)
v o(n)
C p1 C1
C p2
• Accounting for parasitic capacitances, we have

 C 1 + C p1  1
H (z) = –  -----------------------  ----------- (18)
 C2  z – 1
• Thus, gain coefficient is not well controlled and

partially non-linear (due to C p1 being non-linear).

Parasitic-Insensitive Integrators
C2
φ1 φ2
C1
φ1
v ci(t) v co(t)
φ2 φ1
v i(n) = v ci(nT ) v o(n) = v co(nT )
• By using 2 extra switches, integrator can be made

insensitive to parasitic capacitances
— more accurate transfer-functions
— better linearity (since non-linear capacitances
unimportant)

C2 C2
v ci(nT – T ) v ci(nT – T ⁄ 2)
+ -
C1 C1
- v co(nT – T ) + v co(nT – T ⁄ 2)
φ 1 on φ 2 on
• Same analysis as before except that C 1 is switched

in polarity before discharging into C 2 .
V o(z) C 1 1
H (z) ≡ ------------- =  ------  ----------- (19)
V i(z) C 2 z – 1
• A positive integrator (rather than negative as before)

C p3 C p4
C2
φ1 φ2
C1 φ1
v i(n)
v o(n)
φ2 φ1
C p1 C p2
• C p3 has little effect since it is connected to virtual gnd
• C p4 has little effect since it is driven by output
• C p2 has little effect since it is either connected to

virtual gnd or physical gnd.

• C p1 is continuously being charged to v i(n) and
discharged to ground.
• φ 1 on — the fact that C p1 is also charged to v i(n – 1)
does not affect C 1 charge.
• φ 2 on — C p1 is discharged through the φ 2 switch
attached to its node and does not affect the charge
accumulating on C 2 .
• While the parasitic capacitances may slow down
settling time behavior, they do not affect the discrete-
time difference equation

Parasitic-Insensitive Inverting Integrator
C2
φ1 φ1
C1
φ1
v i(n)
v o(n)
V i(z) φ2 φ2
V o(z)
C 2 v co(nT – T ⁄ 2) = C 2 v co(nT – T ) (20)

C 2 v co(nT ) = C 2 v co(nT – T ⁄ 2) – C 1 v ci(nT ) (21)
• Present output depends on present input(delay-free)
V o(z) C 1 z
H (z) ≡ ------------- = –  ------  ----------- (22)
V i(z) C 2 z – 1
• Delay-free integrator has negative gain while
delaying integrator has positive gain.

Signal-Flow-Graph Analysis
C1
V 1(z)
φ1 φ2
C2 CA
V 2(z)
φ2 φ1 φ1
φ1 φ1 V o(z)
C3
V 3(z)
φ2 φ2
–C 1 ( 1 – z –1 )
V 1(z)
C 2 z –1
V 2(z)  ------
1  1
- ---------------- V o(z)
 C A  1 – z –1
–C 3
V 3(z)

First-Order Filter
V in(s) V out(s)
• Start with an active-RC structure and replace

resistors with SC equivalents.
• Analyze using discrete-time analysis.

First-Order Filter
φ1 φ1 φ1 φ1
C2 C3
φ2 φ2 φ2 φ2
CA
C1 φ1
V i(z)
V o(z)
–C 3
–C 2
V i(z)  ------
1  1
- ---------------- V o(z)
 C A  1 – z –1
–C 1 ( 1 – z –1 )

First-Order Filter
C A ( 1 – z – 1 )V o(z) = – C 3 V o(z) – C 2 V i(z) – C 1 ( 1 – z – 1 )V i(z) (23)
 C1   C2 
 -------  ( 1 – z ) +  ------- 
– 1
C A C A
V o(z) – -----------------------------------------------------
C3
H (z) ≡ ------------- = –
1 – z + -------1 (24)
V i(z) CA
C 1 + C 2 C1
 --------------------  z – -------
 CA  CA
= – -----------------------------------------
 C3 
1 + -------  z – 1
 C A

First-Order Filter
• The pole of (24) is found by equating the
denominator to zero
CA
z p = -------------------- (25)
C A + C3
• For positive capacitance values, this pole is

restricted to the real axis between 0 and 1
— circuit is always stable.
• The zero of (24) is found to be given by
C1
z z = -------------------- (26)
C1 + C2
• Also restricted to real axis between 0 and 1.

First-Order Filter
The dc gain is found by setting z = 1 which results in
–C 2
H (1) = ---------- (27)
C3
• Note that in a fully-differential implementation,
effective negative capacitances for C 1 , C 2 and C 3 can
be achieved by simply interchanging the input wires.
• In this way, a zero at z = – 1 could be realized by
setting
C 1 = – 0.5C 2 (28)

First-Order Example
• Find the capacitance values needed for a first-order
SC-circuit such that its 3dB point is at 10kHz when a
clock frequency of 100kHz is used.
• It is also desired that the filter have zero gain at
50kHz (i.e. z = – 1 ) and the dc gain be unity.
• Assume C A = 10 pF.
Solution
• Making use of the bilinear transform
p = ( z – 1 ) ⁄ ( z + 1 ) the zero at – 1 is mapped to Ω = ∞ .
• The frequency warping maps the -3dB frequency of
10kHz (or 0.2π rad/sample ) to

First-Order Example
 0.2π 
Ω = tan ----------- = 0.3249 (29)
 2 
• in the continuous-time domain leading to the
continuous-time pole, p p, required being
p p = – 0.3249 (30)
• This pole is mapped back to z p given by
1 + pp
z p = --------------- = 0.5095 (31)
1 – pp
• Therefore, H (z) is given by

k(z + 1)
H (z) = ------------------------ (32)
z – 0.5095

First-Order Example
• where k is determined by setting the dc gain to one
(i.e. H (1) = 1 ) resulting
0.24525 ( z + 1 )
H (z) = ------------------------------------ (33)
z – 0.5095
• or equivalently,
0.4814z + 0.4814
H (z) = ------------------------------------------ (34)
1.9627z – 1
• Equating these coefficients with those of (24) (and
assuming C A = 10 pF) results in
C 1 = 4.814 pF (35)
C 2 = – 9.628 pF (36)
C 3 = 9.628 pF (37)

Switch Sharing
φ1
C3
φ2
C1
CA
φ1 φ1
C2
)
V o(z)
φ2 φ2
• Share switches that are always connected to the

same potentials.

Fully-Differential Filters
• Most modern SC filters are fully-differential
• Difference between two voltages represents signal
(also balanced around a common-mode voltage).
• Common-mode noise is rejected.
• Even order distortion terms cancel
2 3 4
v p1 = k 1 v 1 + k 2 v1 + k 3 v1 + k 4 v1 +…
nonlinear
v1 element
3 5
+ v diff = 2k 1 v 1 + 2k 3 v 1 + 2k 5 v 1 + …
-
–v1 nonlinear
element
2 3 4
v n1 = – k 1 v 1 + k 2 v1 – k 3 v1 + k 4 v1 +…

C1
C3 φ1
φ2 φ2 C A φ2
+ C2
φ1 φ1 +
V i(z) φ1
V (z)
φ1 - o
- C2
φ2 φ2 CAφ
2
C3 φ1
C1

• Negative continuous-time input
— equivalent to a negative C 1
C1
C3 φ1
φ2 φ2 C A φ2
+ C2
φ1 φ1 +
V i(z) φ1
V (z)
φ1 - o
- C2
φ2 φ2 CAφ
2
C3 φ1
C1

• Note that fully-differential version is essentially two
copies of single-ended version, however ... area
penalty not twice.
• Only one opamp needed (though common-mode
circuit also needed)
• Input and output signal swings have been doubled so
that same dynamic range can be achieved with half
capacitor sizes (from kT ⁄ C analysis)
• Switches can be reduced in size since small caps
used.
• However, there is more wiring in fully-differ version
but better noise and distortion performance.

Low-Q Biquad Filter
2
V out(s) k2s + k1s + ko
H a(s) ≡ ----------------- = – --------------------------------------- (38)
V in(s) 2 ωo 2
s + ------ s + ωo
Q
1 ⁄ ωo
Q ⁄ ωo
C A = 1 V c1(s)
CB = 1
ωo ⁄ k o –1 ⁄ ωo
V in(s)
V out(s)
1 ⁄ k1
k2

Low-Q Biquad Filter
φ1 K C φ1
4 1
φ2 φ2 φ1 K C φ1
6 2
φ2 φ2
C1
V 1(z) C2
φ1 K C φ1
V i(z) 1 1 φ1 K C φ2 φ1
5 2 V o(z)
φ2 φ2
φ2 φ1
φ1 K C φ1
2 2
φ2 φ2
K 3C2

Low-Q Biquad Filter
–K 4
–K 6
V 1(z)
–K 1 1 K 5 z –1 1
V i(z) ---------------- ---------------- V o(z)
1 – z –1 1 – z –1
–K 2
–K 3 ( 1 – z –1 )
2
V o(z) ( K 2 + K 3 )z + ( K 1 K 5 – K 2 – 2K 3 )z + K 3
H (z) ≡ ------------- = – ----------------------------------------------------------------------------------------------------- (39)
V i(z) 2
( 1 + K )z + ( K K – K – 2 )z + 1
6 4 5 6

Low-Q Biquad Filter Design
2
a2 z + a1 z + a0
H (z) = – -------------------------------------
2
(40)
b2 z + b1 z + 1
• we can equate the individual coefficients of “z” in
(39) and (40), resulting in:
K 3 = a0 (41)
K 2 = a2 – a0 (42)
K 1 K 5 = a0 + a1 + a2 (43)
K 6 = b2 – 1 (44)
K 4 K 5 = b1 + b2 + 1 (45)
• A degree of freedom is available here in setting
internal V 1(z) output

Low-Q Biquad Filter Design
• Can do proper dynamic range scaling
• Or let the time-constants of 2 integrators be equal by
K4 = K5 = b1 + b2 + 1 (46)
Low-Q Biquad Capacitance Ratio
• Comparing resistor circuit to SC circuit, we have
K 4 ≈ K 5 ≈ ωo T (47)
ωo T
K 6 ≈ ---------- (48)
Q
• However, the sampling-rate, 1 ⁄ T , is typically much
larger that the approximated pole-frequency, ω o ,
ωo T « 1 (49)

Low-Q Biquad Capacitance Ratio
• Thus, the largest capacitors determining pole
positions are the integrating capacitors, C 1 and C 2 .
• If Q < 1 , the smallest capacitors are K 4 C 1 and K 5 C 2
resulting in an approximate capacitance spread of
1 ⁄ ( ωo T ) .
• If Q > 1 , then from (48) the smallest capacitor would

be K 6 C 2 resulting in an approximate capacitance
spread of Q ⁄ ( ω o T ) — can be quite large for Q » 1

High-Q Biquad Filter
• Use a high-Q biquad filter circuit when Q » 1
• Q-damping done with a cap around both integrators
• Active-RC prototype filter
1 ⁄ ωo
1⁄Q
C1 = 1 C2 = 1
ωo ⁄ k o –1 ⁄ ωo
V in(s)
k 1 ⁄ ωo V out(s)
k2

φ1 K C φ1
4 1
φ2 φ2
K 6C1
C1
V 1( z ) C2
φ1 K C φ1
1 1 φ1 K C φ2 φ1
V i(z) 5 2 V o(z)
φ2 φ2
φ2 φ1
K 2C1
K 3C2
• Q-damping now performed by K 6 C 1

• Input K 1 C 1 : major path for lowpass
• Input K 2 C 1 : major path for band-pass filters
• Input K 3 C 2 : major path for high-pass filters
• General transfer-function is:
2
V o(z) K 3 z + ( K 1 K 5 + K 2 K 5 – 2K 3 )z + ( K 3 – K 2 K 5 )
H (z) ≡ ------------- = – -------------------------------------------------------------------------------------------------------------------(50)
-
V i(z) 2
z + ( K K + K K – 2 )z + ( 1 – K K )
4 5 5 6 5 6
• If matched to the following general form

2
a2 z + a1 z + a0
H (z) = – -------------------------------------
2
(51)
z + b1 z + b0

K 1 K 5 = a0 + a1 + a2 (52)
K 2 K 5 = a2 – a0 (53)
K 3 = a2 (54)
K 4 K 5 = 1 + b0 + b1 (55)
K 5 K 6 = 1 – b0 (56)
• And, as in lowpass case, can set
K4 = K5 = 1 + b0 + b1 (57)
• As before, K 4 and K 5 approx ω o T « 1 but K 6 ≅ 1 ⁄ Q

Charge Injection
• To reduce charge injection (thereby improving
distortion) , turn off certain switches first.
φ1
C3 Q6
Q5 φ2
C1
CA
φ1 φ 1a
C2
φ1
V i(z)
Q1 Q4 V o(z)
φ2 Q 2Q 3 φ 2a
• Advance φ 1a and φ 2a so that only their charge

injection affect circuit (result is a dc offset)

Charge Injection
• Note: φ 2a connected to ground while φ 1a connected
to virtual ground, therefore ...
— can use single n-channel transistors
— charge injection NOT signal dependent
Q CH = – W LC ox V eff = – W LC ox ( V GS – V t ) (58)
• Charge related to V GS and V t and V t related to
substrate-source voltage.
• Source of Q 3 and Q 4 remains at 0 volts — amount of
charge injected by Q 3, Q 4 is not signal dependent
and can be considered as a dc offset.

Charge Injection Example
• Estimate dc offset due to channel-charge injection
when C 1 = 0 and C 2 = C A = 10C 3 = 10 pF.
• Assume switches Q 3, Q 4 have V tn = 0.8V , W = 30µm ,
–3 2
L = 0.8µm , C ox = 1.9 × 10 pF ⁄ µm , and power
supplies are ± 2.5V .
• Channel-charge of Q 3, Q 4 (when on) is
Q CH 3 = Q CH 4 = – ( 30 ) ( 0.8 ) ( 0.0019 ) ( 2.5 – 0.8 ) (59)

–3
= – 77.5 × 10 pC
• dc feedback keeps virtual opamp input at zero volts.

Charge Injection Example
• Charge transfer into C 3 given by
Q C = – C 3 v out (60)
3
• We estimate half channel-charges of Q 3 , Q 4 are

injected to the virtual ground leading to
1
--- ( Q CH 3 + Q CH 4 ) = Q C (61)
2 3
which leads to
–3
77.5 × 10 pC
v out = -------------------------------------- = 78 mV (62)
1 pF
• dc offset affected by the capacitor sizes, switch sizes
and power supply voltage.

SC Gain Circuits — Parallel RC
R2
R2 ⁄ K C1
KC 1
v in v out(t) = – K v in(t)
φ1
C2
φ1 φ1
KC 2 φ2
φ2 φ2
C1
KC 1
v in(n)
v out(n) = – K v in(n)

SC Gain Circuits — Resettable Gain
C2 φ2
φ2
φ1
φ1
C1
v in(n) C 1
v out(n) = –  ------  v in(n)
φ2
C 2
v out
V off
time
φ2 φ1 φ2 φ1 …

SC Gain Circuits
Parallel RC Gain Circuit
• circuit amplifies 1/f noise as well as opamp offset
voltage
Resettable Gain Circuit
• performs offset cancellation
• also highpass filters 1/f noise of opamp
• However, requires a high slew-rate from opamp
V off
+ - VC
C2 - 2+
VC C2 v out(n)
V off v in(n) + -1
- + C1 +
C1 + V off C 1
V off
V off - = –  ------  v in(n)
- C 2

SC Gain Circuits — Capacitive-Reset
• Eliminate slew problem and still cancel offset by
coupling opamp’s output to invertering input
φ1
C3
φ2
φ2
C2
φ 1( φ 2 ) φ1
C1
v in(n) C 1
φ2 v out(n) = –  ------  v in(n)
( φ1 ) C 2
C4
• C 4 is optional de-glitching capacitor

SC Gain Circuits — Capacitive-Reset
V off
+ -
C2
v out(n – 1)
- +
C3
V off
- +
v out(n – 1) + V off
C1
+
V off
- during reset
C2
during valid output
C1
v in(n)
v out(n)
+  C 1
V off = – ------ v in(n)
C3 C 2
-

SC Gain Circuits — Differential Cap-Reset
φ 1a
C3
φ2
φ 2a
C2
φ1
φ1 C1
+
v in C 1 + -
v out =  ------  ( v in – v in )
φ2 C 2
φ2
- C1 C2 φ1
v in
φ1 φ 2a C3 φ2
φ 1a
• Accepts differential inputs and partially cancels

switch clock-feedthrough

Correlated Double-Sampling (CDS)
• Preceeding SC gain amp is an example of CDS
• Minimizes errors due to opamp offset and 1/f noise
• When CDS used, opamps should have low thermal
noise (often use n-channel input transistors)
• Often use CDS in only a few stages
— input stage for oversampling converter
— some stages in a filter (where low-freq gain high)
• Basic approach:
— Calibration phase: store input offset voltage
— Operation phase: error subtracted from signal

Better High-Freq CDS Amplifier
φ1
C2
φ1 φ2
C1 φ1
v in v out
φ2
φ2 φ2 φ2
C′1 C′2
φ1 φ1 φ1
• φ 2 — C 1', C 2' used but include errors

• φ 1 — C 1, C 2 used but here no offset errors

CDS Integrator
C2
φ2 ( φ1 ) φ2 φ1
C1 φ1
v in
v out
φ1 ( φ2 ) φ1 C′2
• φ 1 — sample opamp offset on C 2'

• φ 2 — C 2' placed in series with opamp to reduce error
• Offset errors reduced by opamp gain
• Can also apply this technique to gain amps

SC Amplitude Modulator
• Square wave modulate by ± 1 (i.e. V out = ± V in)
φ1
C3
φ2
φ2 φ1
φB
φA C2
φ1
φ2
C1
v in
φB
v out φA
φ A = ( φ 2 ⋅ φ ca ) + ( φ 1 ⋅ φ ca ) φ ca
φ B = ( φ 1 ⋅ φ ca ) + ( φ 2 ⋅ φ ca )
• Makes use of cap-reset gain circuit.

• φ ca is the modulating signal

SC Full-Wave Rectifier
v in Square Wave v out

Modulator
φ ca
• Use square wave modulator and comparator to make

• For proper operation, comparator output should
changes synchronously with the sampling instances.

SC Peak Detector
φ V DD
v in
comp
Q2
opamp
v out
v in v out
Q1 CH CH
• Left circuit can be fast but less accurate

• Right circuit is more accurate due to feedback but
slower due to need for compensation (circuit might
also slew so opamp’s output should be clamped)

Chap 10

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Switched-Capacitor Circuits

David Johns and Ken Martin

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

cross-section view equivalent circuit

• Substantial parasitics with large bottom plate

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

• This equivalence is useful when looking at low-freq

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

• Start by looking at an integrator which IS affected by

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

• Thus, the transfer function is same as a continuous-

which is a function of the integrator capacitor ratio

© D. Johns, K. Martin, 1997

• Accounting for parasitic capacitances, we have

• Thus, gain coefficient is not well controlled and

© D. Johns, K. Martin, 1997

• By using 2 extra switches, integrator can be made

© D. Johns, K. Martin, 1997

• Same analysis as before except that C 1 is switched

• A positive integrator (rather than negative as before)

© D. Johns, K. Martin, 1997

• C p3 has little effect since it is connected to virtual gnd

• C p4 has little effect since it is driven by output

• C p2 has little effect since it is either connected to

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

C 2 v co(nT – T ⁄ 2) = C 2 v co(nT – T ) (20)

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

• Start with an active-RC structure and replace

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

• For positive capacitance values, this pole is

• Also restricted to real axis between 0 and 1.

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

• Therefore, H (z) is given by

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

• Share switches that are always connected to the

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

© D. Johns, K. Martin, 1997

• If Q > 1 , then from (48) the smallest capacitor would

© D. Johns, K. Martin, 1997