Session-04-Current Mirror and Single Stage Amplifier

PEMP VSD 528
Session - 04
Current Mirrors and Single Stage Amplifiers
Session Speaker
Chandramohan P
©M S Ramaiah School of Advanced Studies - Bangalore 1

PEMP VSD 528
Session Objectives
• To understand and design sub blocks of analog circuits

design
• To understand the concept of current mirrors and current
sources/sinks
• To design current mirrors and current sources/sinks
• To model and simulate subcircuits using spice
• To understand the single stage amplifiers

PEMP VSD 528
Session Topics
• Current mirrors
– Simple current mirror
– Wilson current mirror
– Cascode current mirror
• Single stage amplifiers
– Common source amplifier
– Common drain amplifier
– Common gate amplifier
– Differential amplifier and design

PEMP VSD 528
Mixed Signal Sub circuits
Each consists of one or more transistors.

They are not used by themselves.
PEMP VSD 528
Current sources / sinks
V
Current
I source
Current I
sink
V
I
V
Non-ideal current sources / sinks PEMP VSD 528

PEMP VSD 528
Current Mirrors/Current Amplifiers

PEMP VSD 528
Simple MOS Current Mirror

PEMP VSD 528
Simple CMOS Current Mirror

Current Mirror Design Example PEMP VSD 528

PEMP VSD 528

PEMP VSD 528
Cascoding
M1 and M2 are the mirror

pair that determines io.
VDS1 and VDS2 matched
go is small

PEMP VSD 528
Cascode Current Mirror

PEMP VSD 528
Small signal model

PEMP VSD 528

PEMP VSD 528
Wilson Current Mirror
go is small
VDS1 and VDS2

not matched

Small signal circuit PEMP VSD 528

PEMP VSD 528
Computation of rout

Characteristics PEMP VSD 528

PEMP VSD 528
Improved Wilson Current Mirror

SPICE simulation PEMP VSD 528

PEMP VSD 528
Applications of current mirrors
Common source amplifier: Load for C.S. Amp

Common drain amplifier (source follower) PEMP VSD 528

Differential input single-ended output gain stage PEMP VSD 528

PEMP VSD 528
Simple Current Mirror Design
• Design a NMOS based current mirror which can sink/mirror a current of
30µA. Estimate the output resistance. Also find the device dimensions in
order to mirror 30µA of current.
Solution:
Assume VGS= 0.7V
VDD
The value of R, can be found by assuming
ID1= ID2 = 30µA, is determined by solving
IRef
the equation below ID2= Iout
VDD −VDS M1
+
M2
ID1 = VGS
R –
VDD − VDS 1.8 − 0.7

⇒R= = = 36.66 KΩ
I D1 30μ

PEMP VSD 528
Solving for the width of the transistors, since the transistors
operate in saturation region
Kn W
ID2 = 30μA = (VGS −VTH)2
2 L
W
30μA =165.5× ×(0.7 −0.379924
)2
L
W
= 1.769
L
Let L1 = L2= 0.36µm, then W2=0.636µm, which gives W1=0.636µm
The small signal output resistance of the current source is given by

1 1
ro = = = 0.37 MΩ
λI o 0.09 × 30μA
PEMP VSD 528
• SPICE code
NMOS Current Souce / Current Mirror
.include "C:\synopsys\FT07Analog\modelfile018.txt"
R1 Vdd P1 32.5K
M1 P1 P1 gnd gnd CMOSN L=0.36U W=0.7U
M2 P2 P1 gnd gnd CMOSN L=0.36U W=0.7U
Vdd Vdd gnd dc 1.8

V2 P2 gnd dc 0
.dc V2 0 1.8 0.01
.op
.print dc i(M1) i(M2) v(P2) i(R1)
.end

PEMP VSD 528
• Simulation Results

PEMP VSD 528
• Design a cascode current source with a DC output current
of 50µA and a small signal output resistance of 100MΩ.
Solution
Begin the design by setting the gate

voltage of M1 and M3 to ensure that M2
and M4 are operating in their constant
current region with VD4=0.5V
Let VGS of M1, M2, M3 and M4 be 0.8V,

the gate voltage on M4 will be 1.6V
With VGS4=0.8V, it implies that the

source of M4, which is the drain of M2
will be at 0.8V
PEMP VSD 528
Since VDS2 = 0.8V,

Recalling that VGS2 – VTn = 0.8 – 0.379924 = 0.420076V, => VDS2 > VDS(SAT)2
Note that VDS(Sat)4 = 0.8V the source of M4 is at 0.8V, the drain voltage must
be greater than 0.5V to ensure operation in the constant current region.
Setting the W/L ratio of M1and M3 to yield VGS = 0.8V with Iref = 50µA
I REF
VGS = VTn + 50
W μnCox 0.8 = 0.379924 +
W
× 165.5
L 2 L
W W1 W3
= 1.712 ∴ = = 1.712
L L1 L3

PEMP VSD 528
We can match the (W/L) of M2 and M4 with M1 and M3, respectively, since
we want IREF = IOUT
W2 W4
∴ = = 1.712
L2 L4
To calculate the small signal output resistance
RS = (gm4 ⋅ ro4)ro2
1 1
ro 4 = ro 2 = ro 4 = ro 2 = = 0.22 MΩ
λn I D 0.09 × 50μ
W
gm4 = 2 μ nCox I REF = 4 ×1.712 ×165.5 × 50 = 238.04
L
RS = ( g m 4 ⋅ ro 4 )ro 2 = 238.04 × 0.22 × 0.22 = 11.52 MΩ

PEMP VSD 528
• SPICE code
M1 P3 P3 Gnd Gnd CMOSN L=0.7U W=1.2U

M2 P4 P3 Gnd Gnd CMOSN L=0.7U W=1.2U
M3 P1 P1 P3 Gnd CMOSN L=0.7U W=1.2U
M4 P2 P1 P4 Gnd CMOSN L=0.7U W=1.2U
I1 Vdd P1 dc 50u
Vdd Vdd Gnd dc 1.8V
V1 P2 gnd dc 0.5V
.dc V1 0 1.8 0.01

.Print dc i(M1) i(M2) i(M3) i(M4)
.end

PEMP VSD 528

PEMP VSD 528
Common-Source Amplifier

PEMP VSD 528
Common Drain amplifier

PEMP VSD 528
Common Gate Amplifier

PEMP VSD 528
Common Source Amplifier with a Current Mirror Active Load

Consider a common source amplifier with a current mirror active load as shown in the figure.
Assume all transistors have W/L = 100μm/1.6μm , and that μnCox=90μA/V2, μpCox=90μA/V2,
Ibias = 100μA, rds-n(Ω) = 8,000L(μm)/ID(mA), and rds-p(Ω) = 12,000L(μm)/ID(mA). What is the
gain of the stage?
Solution:
We have g m1 = 2 μ nCox (W / L)1 I bias = 1.06mA / V
Also 8,000 × 1.6 μm

rds1 = = 128kΩ
0.1mA
and
12,000 × 1.6 μm
rds 2 = = 192 kΩ
0.1mA
AV = − g m1 (rds1 || rds 2 ) = −1.06(128 || 192) = −81.4

Therefore

PEMP VSD 528
Common Source Amplifier with a Current Mirror Active Load

SPICE CODE PEMP VSD 528
Vdd 1 0 dc 5
Ibias 2 0 dc 100u
M3 2 2 1 1 pmos W=200u L=2.6u
M2 3 2 1 1 pmos W=200u L=2.6u
M1 3 4 0 0 nmos W=200u L=2.6u
Vin 4 0 dc 0.849 ac 1
.op
.ac dec 10 1k 10000Meg
.plot ac vdb(3)
.lib C:\Documents and Settings\Desktop\SPICE\CMOS 2U.lib

.end

PEMP VSD 528
Frequency Plot for the Common Source Amplifier
The gain is 36dB, which

corresponds to 63V/V

Common Source Amplifier PEMP VSD 528
Use the parameters as in example1 along with the following : Rin=180 KΩ, CL=
0.3pF, Cgs1= 0.2pF, Cgd1= 0.015pF, Cdb1= 20fF, and Cdb2= 36fF.Estimate the –3dB
frequency of the common-source amplifier shown in the figure.
Solution:
We have R2 = rds1 || rds 2 = 77 kΩ
And C2 = C L + Cdb1 + Cdb 2 = 0.36 pF
Therefore the time constant due to Rin, namely, Rin[Cgs1+ Cgd1(1+A)]=0.26μs.

The time constant due to R2, namely, R2[Cgd1+ C2]=0.03μs.
The –3-dB frequency (in hertz) is equal to
[ [ ]
f −3dB = ⎢ ⎥ Rin C gs1 + C gd 1 (1 + g m1 R2 ) + R2 (C gd 1 + C2 )
⎡ 1 ⎤
]−1
⎣ 2π ⎦
= 550kHz.

Common Source Amplifier PEMP VSD 528

Vdd 1 0 dc 5
Ibias 2 0 dc 100u
M3 2 2 1 1 pmos W=400u L=2u
M2 3 2 1 1 pmos W=400u L=2u
M1 3 4 0 0 nmos W=150u L=2u
Rin 5 4 180k
Vin 5 0 dc 0.849 ac 1
Cl 3 0 0.3p
.op
.plot ac vdb(3)
.lib C:\Documents and Settings\Desktop\SPICE\CMOS 2U.lib

.end
PEMP VSD 528
Frequency Response for a Common Source Amplifier
The -36dB frequency

occurs around 460kHz

PEMP VSD 528
Source Follower Stage with a Current Mirror used to supply bias current
Consider the source follower in the figure where all transistors have W/L = 100μm/1.6μm,
μnCox=90μA/V2, μpCox=30μA/V2, Ibias = 100μA, γn= 0.5V1/2 rds-n(Ω) = 8,000L(μm)/ID(mA).
What is the gain of the stage?
Solution:
We have g m1 = 2 μ nCox (W / L)1 I bias = 1.06mA / V
Also 8,000 × 1.6 μm

rds1 = rds 2 = = 128kΩ
0.1mA
Taking body effect into consideration
γg m
g s1 =
2 VSB + | 2φ F |
Consider VSB ≈ 2V ∴ g = 0.5 × g m = 0.15 g = 0.16mA / V

s1
2 2 + 0.7
m
We have 1.06
AV = = 0.86V / V
1.06 + 0.16 + 1 / 128 + 1 / 128

PEMP VSD 528
Source Follower Stage with a Current Mirror

used to supply bias current

Vdd 1 0 dc 5
Ibias 1 2 dc 100u
M3 2 2 0 0 nmos W=80u L=2u
M2 3 2 0 0 nmos W=80u L=2u
M1 1 4 3 0 nmos W=80u L=2u
Vin 4 0 dc 2 ac 1
.op
.plot ac vdb(3)
.lib C:\Documents and Settings\Desktop\SPICE\CMOS CN20.lib

.end

PEMP VSD 528
Frequency Plot for the Source-Follower
The gain is –1.36dB, which

corresponds to 0.86V/V

Step Response of Source Follower PEMP VSD 528
Using the parameters in example2 and assume Rin=180 KΩ, CL= 10pF, Cgs1=
0.2pF, Cgd1= 15pF, Csb1= 40fF, and Cin= 30fF.Find ω0, Q, and the frequency of
the zero for the source follower.
Solution:
From example2 we have gm1=1.06mA/V, rds1= 128KΩ, rds2=128kΩ

and gs1=0.16mA/V
Thus Cin' = Cin + C gd 1 = 45 fF

Gs1 = g s1 + g ds1 + g ds 2 = 0.176mA / V
C s = C L + C sb1 = 10.04 pF
And so we can find ω0 as ω 0 = G in ( g m 1 + G s 1 )

C gs 1 C s + C in' ( C gs 1 + C s )
= 5.24 × 10 7 rad / s = 2π × 8.34 MHz

PEMP VSD 528
Gin ( g m1 + Gs1 )[C gs1Cs + Cin' (C gs1 + C s ) ]

Q=
Gin C s + Cin' ( g m1 + Gs1 ) + C gs1Gs1
= 0.8
This results in an overshoot for a step input given by
−π / 4 Q 2 −1
%overshoot = 100e = 8%
− g m1
Zero frequency ωz = = 844 MHz , and thus it can be ignored.
C gs1

Step Response of Source Follower PEMP VSD 528

Vdd 1 0 dc 5
Vss 2 0 dc -5
Ibias 3 2 dc 100u
Rin 4 0 180k
Cin 4 0 30f
Cl 3 0 5p
M1 1 4 3 2 nmos W=150u L=2u
Iin 4 0 pulse(0 -5u 10n 0 0)
.op
.tran 0.5n 300n
.plot v(3)
.lib C:\Documents and Settings\Desktop\SPICE\CMOS 1.2UL3.lib

.end
PEMP VSD 528
Step Response of a Source Follower
The overshoot here

is about approx. 10%

Source Follower with Compensation Network PEMP VSD 528
Using the parameters as in example above find the compensation network and the resulting first
order and second order poles of the source follower
Solution: g m1C gs1C s

C1 ≅ = 0.170 pF
( g m1 + Gs1 )(C gs1 + C s )
and
(C gs1 + C s ) 2
R1 ≅ ≅ 49 .3kΩ
C gs1C s g m1
The capacitor is a reasonable value to be realized on chip. The resistor can be realized by a MOS
transistor biased in the triode(ie., linear) region. Assuming the compensation network is used, the
poles of the transfer function then become
Gin
p1 ≅ = 2π × 3.61MHz
C gs1 + Cin
'
And
g m 1 + G s1
p2 = = 2π × 19 .3 MHz
C gs + C L
The speed penalty paid for using the compensation network is quite high, because the pole frequency
without compensation was around 8 MHz whereas here the dominant pole is at 3.6 MHz.

Source Follower with Compensation Network PEMP VSD 528

Vdd 1 0 dc 5
Vss 2 0 dc -5
Ibias 3 2 dc 100u
Rin 4 0 180k
Cin 4 0 30f
Cl 3 0 10p
M1 1 4 3 2 nmos W=200u L=2u
Iin 4 0 dc 0 ac 1
C1 4 5 0.17p
R1 5 0 49.3k
.op
.print vdb(3)
.lib C:\Documents and Settings\Desktop\SPICE\CMOS 1.2UL3.lib
.end
PEMP VSD 528
The Bode Plot of a Source Follower with compensation network
-20dB/decade
-40dB/decade

PEMP VSD 528
CMOS Differential Amplifier
• Design the currents and W/L values of the current mirror
load MOS differential amplifier to satisfy the following
specifications:
VDD = -VSS = 1.8V

SR ≥ 10V/μs (CL=5pF),
f-3dB ≥ 100kHz (CL=5pF),
small signal gain of 100V/V,
-1V ≤ ICMR ≤ 1.5V
Pdiss ≤ 1mW.

PEMP VSD 528
Design of a CMOS Differential Amplifier with a Current Mirror Load
Design Considerations:
Constraints Specifications
Power supply Small-signal gain
Technology Frequency response (CL)
Temperature ICMR
Slew rate (CL)
Power dissipation

PEMP VSD 528
• Procedure:
– Pick ISS to satisfy the slew rate
knowing CL or the power
dissipation
– Check to see if Rout will satisfy
the frequency response, if not
change ISS or modify circuit
– Design W3/L3 (W4/L4) to satisfy
the upper ICMR
– Design W1/L1 (W2/L2) to satisfy
the gain
– Design W5/L5 to satisfy the
lower ICMR
– Iterate where necessary

PEMP VSD 528
Solution Step1:- To meet the slew rate, and maximum Power Dissipation
I5 = SR ⋅ CL = (10V / μs) × 5 pF = 50μA

⇒ I 5 ≥ 50μA LL (1)
Pdiss = (VDD + VSS )⋅ I5

1mW
I5 = = 277.7μA
(1.8 + 1.8)
⇒ I 5 ≤ 277.7μA LL (2)
Step2:- To meet the frequency requirement
1
ω3dB =
Rout ⋅ C L
1 1
2π ⋅100k = ⇒ Rout = = 318471.33Ω
Rout ⋅ 5 pF 2π ⋅100k ⋅ 5 pF
PEMP VSD 528
2
Rout is given by Rout =
(λN +λP )⋅ I5
2
I5 = = 34 .888 μA
(0.09 + 0.09 ) ⋅ 318471 .33
⇒ I 5 ≥ 35μA LL (3)
From Eqns. (1), (2) and (3) We can pick the I5 as approx. 100µA
Step3:- The maximum input common mode voltage gives
VGS3 = VDD – VIC(max) + VTN1 = 1.8 – 1.5 + 0.379924 = 0.6799V ≈ 0.7V
Therefore, we can write

2 ⋅ I DS
VSG 3 = + VTP
⎛ W3 ⎞
μ P C ox ⎜⎜ ⎟⎟
⎝ L3 ⎠
PEMP VSD 528
Solving for W1/L1 gives

⎛W ⎞
50 μA ⇒ ⎜⎜ 3 ⎟⎟ = 15.839 ≈ 16
0 .7 = + 0.4038864 ⎝ L3 ⎠
2 ⎛ W3 ⎞
36 μA / V ⎜⎜ ⎟⎟ W3 W4
∴ = = 16
⎝ L3 ⎠ L3 L4
Step4:- Using the small signal gain specification gives

⎛ W1 ⎞
2 I ds 2 ⋅ ⎜⎜ ⎟⎟
gm1 ⎝ L1 ⎠
AV = gm1 ⋅ Rout = ⇒ AV =
gds2 + gds4 (λ N + λ P ) I 3
Solving for W1/L1 gives
⎛W ⎞
2 ×165.5 × ⎜⎜ 1 ⎟⎟ ⎛ W1 ⎞
⎝ L1 ⎠ ⎜⎜ ⎟⎟ = 48.9425 ≅ 49
100 =
1.8 × 50 ⎝ L1 ⎠
PEMP VSD 528
W2 W1
∴ = = 49
L2 L1
Step5:- Using the minimum input common mode voltage gives

VDS5(sat) =VIC(min)−VSS −VGS1
2 I D1
VDS 5( sat ) = VIC (min) − VSS − + VTN
W1
μ nCox
L1
50
VDS 5( sat ) = −1 + 1.8 − + 0.379924 = 0.3415
165.5 × 49
This value of VDS5(sat) gives a W5/L5 of
W5 I 100
= ' 25 = = 5.18
L5 K nVDS 5( sat ) 165.5 × (0.3415) 2

PEMP VSD 528
W2 W1
∴ = = 49
L2 L1
W3 W4
∴ = =16
L3 L4
W5
=5
L5
W6
=5
L6

PEMP VSD 528
• SPICE code
CMOS Differential Amplifier with PMOS Current Mirror
M3 P1 P1 Vdd Vdd CMOSP L=1U W=16U

M4 Vout P1 Vdd Vdd CMOSP L=1U W=16U
M1 P1 Vin+ P2 gnd CMOSN L=1U W= 49U
M2 Vout Vin- P2 gnd CMOSN L=1U W=49U
M5 P2 P3 Vss Vss CMOSN L=1U W=5U
M6 P3 P3 Vss Vss CMOSN L=1U W=5U
Cload vout gnd 5pF
Ibias Vdd P3 100U
Vdd Vdd Gnd DC 1.8
Vin1 Vin+ Gnd DC 0.5 ac 1
Vin2 Vin- Gnd DC 0.5
Vss Vss gnd dc -1.8
.AC DEC 25 1 10Meg

.print ac vm(Vout) vdb(vout)
.end
PEMP VSD 528

PEMP VSD 528
Summary
• Current mirrors are used as current references and as load
circuits
• Single stage amplifiers forms the basic building block of
analog circuit design
• Single stage amplifiers can be designed carefully taking
care of loading conditions and active loads for better gain
• Differential amplifiers form the basic building block of
operational amplifiers

Session-04-Current Mirror and Single Stage Amplifier

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Session-04-Current Mirror and Single Stage Amplifier

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PEMP VSD 528

Current Mirrors and Single Stage Amplifiers

©M S Ramaiah School of Advanced Studies - Bangalore 1

• To understand and design sub blocks of analog circuits

©M S Ramaiah School of Advanced Studies - Bangalore 2

©M S Ramaiah School of Advanced Studies - Bangalore 3

Each consists of one or more transistors.

©M S Ramaiah School of Advanced Studies - Bangalore 6

©M S Ramaiah School of Advanced Studies - Bangalore 7

©M S Ramaiah School of Advanced Studies - Bangalore 8

©M S Ramaiah School of Advanced Studies - Bangalore 9

©M S Ramaiah School of Advanced Studies - Bangalore 10

©M S Ramaiah School of Advanced Studies - Bangalore 11

M1 and M2 are the mirror

VDS1 and VDS2 matched

©M S Ramaiah School of Advanced Studies - Bangalore 12

©M S Ramaiah School of Advanced Studies - Bangalore 13

©M S Ramaiah School of Advanced Studies - Bangalore 14

©M S Ramaiah School of Advanced Studies - Bangalore 15

VDS1 and VDS2

©M S Ramaiah School of Advanced Studies - Bangalore 16

©M S Ramaiah School of Advanced Studies - Bangalore 17

©M S Ramaiah School of Advanced Studies - Bangalore 18

©M S Ramaiah School of Advanced Studies - Bangalore 19

©M S Ramaiah School of Advanced Studies - Bangalore 20

©M S Ramaiah School of Advanced Studies - Bangalore 21

Common source amplifier: Load for C.S. Amp

©M S Ramaiah School of Advanced Studies - Bangalore 22

©M S Ramaiah School of Advanced Studies - Bangalore 23

©M S Ramaiah School of Advanced Studies - Bangalore 24

VDD − VDS 1.8 − 0.7

©M S Ramaiah School of Advanced Studies - Bangalore 25

The small signal output resistance of the current source is given by

NMOS Current Souce / Current Mirror

Vdd Vdd gnd dc 1.8

©M S Ramaiah School of Advanced Studies - Bangalore 27

©M S Ramaiah School of Advanced Studies - Bangalore 28

Begin the design by setting the gate

Let VGS of M1, M2, M3 and M4 be 0.8V,

With VGS4=0.8V, it implies that the

Since VDS2 = 0.8V,

©M S Ramaiah School of Advanced Studies - Bangalore 30

RS = ( g m 4 ⋅ ro 4 )ro 2 = 238.04 × 0.22 × 0.22 = 11.52 MΩ

Cascode Current Mirror

M1 P3 P3 Gnd Gnd CMOSN L=0.7U W=1.2U

.dc V1 0 1.8 0.01

©M S Ramaiah School of Advanced Studies - Bangalore 32

©M S Ramaiah School of Advanced Studies - Bangalore 33

©M S Ramaiah School of Advanced Studies - Bangalore 34

©M S Ramaiah School of Advanced Studies - Bangalore 35

©M S Ramaiah School of Advanced Studies - Bangalore 36

Common Source Amplifier with a Current Mirror Active Load

Also 8,000 × 1.6 μm

AV = − g m1 (rds1 || rds 2 ) = −1.06(128 || 192) = −81.4

©M S Ramaiah School of Advanced Studies - Bangalore 37

Common Source Amplifier with a Current Mirror Active Load

©M S Ramaiah School of Advanced Studies - Bangalore 38

.lib C:\Documents and Settings\Desktop\SPICE\CMOS 2U.lib

©M S Ramaiah School of Advanced Studies - Bangalore 39

The gain is 36dB, which

©M S Ramaiah School of Advanced Studies - Bangalore 40

We have R2 = rds1 || rds 2 = 77 kΩ

And C2 = C L + Cdb1 + Cdb 2 = 0.36 pF