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Hall Ticket No Question Paper Code: AEC002

INSTITUTE OF AERONAUTICAL ENGINEERING


(Autonomous)
MODEL QUESTION PAPER −II

Four Year B.Tech III Semester End Examinations, November - 2017


Regulation: R16
DIGITAL SYSTEM DESIGN
Time: 3 Hours Max Marks: 70

Answer any ONE question from each Unit


All questions carry equal marks
All parts of the question must be answered in one place only

UNIT - I
1 a) Perform the BCD addition. [7M]
i) i)275+493
ii)
ii) 204.6+185.47
b) Perform the following Subtraction using 1’s complement. [7M]
i) i) 586-256 ii) 425-137
2 a) The message below coded in the seven bit hamming code is transmitted through a noisy [7M]
channel. Decode the message assuming the at most a single error occurred in each code
word.
1001011,0111001,1110110
b) Express the following excess – 3 numbers as decimals [7M]
i)1010 1100 0110 ii)0111 0100 1011.1000
UNIT - II
3 a) Simplify the followings expression and implement them with NAND gate circuits [7M]
i) F=AB'+ABD+ABD'+A'C'D'+A'BC'
ii) G=BD+BCD'+AB'C'D'
b) Reduce the expression f = πM(0,1,2,3,4,7) using mapping and implement it in AOI logic [7M]
as well as in NOR logic.
4 a) Implement the function F with the NAND –AND & AND-NOR logic [7M]
F(A,B,C,D) = ∑m(0,2,3,4,7,9,15)+d(6,8,11)
b) Convert the following to max terms [7M]
i) (A+B')(A'+D) ii) A(B+C')
UNIT – III
5 a) Implement a combinational circuit to add 1 bit information and produce output using [7M]
Logic gates and also constructs using universal gates.
b) Design a combinational circuit to produce the 2’s compliment of 4bit binary number using [7M]
logic gates.
6 a) Design a circuit to detect the decimal numbers 0, 1, 4, 6, 7&8 in a 4 bit excess -3code [7M]
input.
b) Design a minimal circuit to produce an output of 1, when its input is a 2421 code [7M]
representing an even decimal number less than 10.
UNIT – IV
7 a) Design a 2- input 2-output synchronous sequential circuit which produces an output z=1, [7M]
when ever any of the following input sequences 1101,1011 or 1001 occurs. The circuit
resets to the initial state after a 1 output is generated?
b)
Design A Jk counter that goes through states 2,4,5,7,2,4… is a counter self starting ? Modify the [7M]
circuit such that whenever it goes to any invalid states it comes back to state 2?
8 a) Design d-counter that goes through states 0,2,4,6,0…the undesired states must always go to [7M]
a zero on next clock pulse?
b) Explain the operation of Johnson counter using jk flip-flop, T flip-flop and draw the timing [7M]
diagram with positive going clock pulse?
UNIT – V
9 a) Find the equivalence partition and a corresponding reducing machine in standard form for [7M]
the machine given in table1.
NS
PS
X=0 X=1
A E,0 D,1
B F,0 D,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0
Table -1
b) Define the state equivalence and machine equivalence with reference to sequential [7M]
machines.

10 a) Obtain minimal state table using partition technique for the state table show in table -2. [7M]
NS, Z
PS
X=0 X=1
Q1 Q2,0 Q8,1
Q2 Q6,0 Q4,1
Q3 Q4,1 Q5,0
Q4 Q3,1 Q6,0
Q5 Q4,0 Q5,1
Q6 Q3,0 Q5,1
Q7 Q3,0 Q4,1
Q8 Q3,1 Q1,0
Table-2
b) Find the minimal length sequence that distinguishes state Q1 from state Q2 for a given [7M]
table2.
DIGITAL SYSTEM DESIGN

III Semester: ECE

Course Code Category Hours / Week Credits Maximum Marks


L T P C CIA SEE Total
AEC002 Foundation
3 1 - 4 30 70 100
Contact Classes: 45 Tutorial Classes: 15 Practical Classes: Nil Total Classes: 60
OBJECTIVES:
The course should enable the students to:
I. Formulate and solve problems involving number systems and operations related to them and
generate different digital codes.
II. Describe and analyze functions of logic gates and optimize the logic functions using K -map and
Quine - McClusky methods.
III. Demonstrate knowledge of combinational and sequential logic circuits elements like Adders,
Multipliers, flip-flops and use them in the design of latches, counters, sequence detectors, and similar
circuits.
IV. Design a simple finite state machine from a specification and be able to implement this in gates and
edge triggered flip-flops.

UNIT-I FUNDAMENTALS OF DIGITAL TECHNIQUES Classes:08


Review of number systems: Decimal, binary, octal and hexa decimal, base conversion methods,
complements of numbers; binary codes: Binary coded decimal, excess-3, gray codes, error detecting and
error correcting codes.
UNIT-II BOOLEAN ALGEBRA AND THEOREMS Classes:10
Boolean algebra: Postulates and theorems; Logic gates and truth tables, representation of switching
functions, sum of products and product of sums forms, karnaugh map representation, minimization using
karnaugh map Quine - McClusky method of minimization.
UNIT-III DESIGN OF COMBINATIONAL CIRCUITS Classes: 08
Design of combinational circuits using conventional AND, OR, NOT, NAND, NOR and EX-OR gates;
Adders and subtractors: Half adder, full adder, half subtractor, full subtractor.
Parallel adder, serial adder, carry look ahead adder, binary coded decimal adder, 1’s complement subtractor,
2‘s complement subtractor.

UNIT-IV SEQUENTIAL CIRCUITS Classes: 10

Flip Flops: SR flip flop, JK flip flop, D flip flop, T flip flop, excitation tables, race around condition,
master slave flip flop; Counters: Design of synchronous and asynchronous counters; Shift registers:
Modes of operation, bidirectional shift registers, ring counters, Johnson counters.
CAPABILITIES AND MINIMIZATION OF SEQUENTIAL
UNIT-V Classes: 09
MACHINES
Synchronous sequential circuits: State table, state diagram, state assignment, state minimization;
Sequential circuits example: Sequence detectors, binary counters; Mealy and Moore machines:
Capabilities and limitations of finite state machine, state equivalence and machine minimization of
completely specified or incompletely specified machines, partition method, Merger table and graph
method.
Text Books:

1. M. Morris Mano, Michael D. Ciletti, ―Digital Design‖, Pearson Education/PHI, 3rd Edition, 2008.
2. Zvi. Kohavi, ―Switching and Finite Automata Theory‖, Tata McGraw Hill, 3rd Edition, 2004.
3. John M. Yarbrough, ―Digital logic applications and design‖, Thomson publications, 2nd Edition, 2006.

Reference Books:

1. Roth, ―Fundamentals of Logic Design‖, Cengage learning, 5th Edition, 2004.


2. A. Anand Kumar, ―Switching Theory and Logic Design‖, Prentice Hall of India, 1st Edition, 2014.

Web References:

1. mcsbzu.blogspot.com
2. http://books.askvenkat.com
3. http://worldclassprogramme.com
4. http://www.daenotes.com
5. http://nptel.ac.in/courses/117106086/1

E-Text Books:

1. https://books.google.co.in/books/about/Switching_Theory_and_Logic_Design
2. https://www.smartzworld.com/notes/switching-theory-and-logic-design-stld
3. https://www.researchgate.net/.../295616521_Switching_Theory_and_Logic_Design
4. https://books.askvenkat.com/switching-theory-and-logic-design-textbook-by-anand-kumar/
5. http://www.springer.com/in/book/9780387285931

I. COURSE OUTCOMES

After completing this course the student must demonstrate the knowledge and ability to:
1. Understand number systems, binary addition and subtraction, 2’s complement representation and
operations with this representation and understand the different binary codes.
2. Explain switching algebra theorems and apply them for logic functions.

3. Identify the importance of SOP and POS canonical forms in the minimization or other optimization
of Boolean formulas in general and digital circuits.

4. Discuss about digital logic gates and their properties.

5. Evaluate functions using various types of minimizing algorithms like Boolean algebra.

6. Evaluate functions using various types of minimizing algorithms like Karnaugh map or tabulation
method

7. Design Gate level minimization using K-Maps.

8. Analyze the design procedures of Combinational logic circuits.

9. Understand bi-stable elements and different types of latches and flip-flops.

10. Analyze the design procedures of small sequential circuits.


11. Understand the concept of Shift Registers.

12. Analyze the design procedures of Synchronous Counters.

13. Analyze the design procedures of Asynchronous Counters.

14. Understand and analyze the design a finite state machine.

15. Understand and analyze the merger gaphs.

16.

INSTITUTE OF AERONAUTICAL ENGINEERING


(Autonomous)

Dundigal, Hyderabad - 500 043

ELECTRONICS AND COMMUNICATION ENGINEERING

Proficiency
Program Outcomes Level
assessed by
Engineering knowledge: Apply the knowledge of mathematics, H Lectures,
PO1 science, engineering fundamentals, and an engineering Assignments,
specialization to the solution of complex engineering problems. Exercises.
Problem analysis: Identify, formulate, review research literature, S Hands on Practice
PO2 and analyze complex engineering problems reaching substantiated Sessions.
conclusions using first principles of mathematics, natural sciences,
and engineering sciences.
Design/development of solutions: Design solutions for complex N --
engineering problems and design system components or processes
PO3 that meet the specified needs with appropriate consideration for the
public health and safety, and the cultural, societal, and
environmental considerations.
Conduct investigations of complex problems: Use research-based S Lab sessions,
PO4 knowledge and research methods including design of experiments, Exams
analysis and interpretation of data, and synthesis of the information
to provide valid conclusions.
Modern tool usage: Create, select, and apply appropriate H Design Exercises.
PO5 techniques, resources, and modern engineering and IT tools
including prediction and modeling to complex engineering activities
with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the N --
PO6 contextual knowledge to assess societal, health, safety, legal and
cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
Environment and sustainability: Understand the impact of the S Oral discussions
PO7 professional engineering solutions in societal and environmental
contexts, and demonstrate the knowledge of, and need for
Ethics: Apply ethical principles and commit to professional ethics N --
PO8
and responsibilities and norms of the engineering practice.
Individual and team work: Function effectively as an individual, H Seminars
PO9
and as a member or leader in diverse teams, and in Discussions
Communication: Communicate effectively on complex S Seminars, Paper
engineering activities with the engineering community and with Presentations
PO10 society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
Project management and finance: Demonstrate knowledge and S Discussions,
PO11 understanding of the engineering and management principles and Exams
apply these to one’s own work, as a member and leader in a team,
to manage projects and in multidisciplinary environments.
Life-long learning: Recognize the need for, and have the S Development of
PO12 preparation and ability to engage in independent and life-long Mini Projects
learning in the broadest context of technological change.

Program Specific Outcomes Proficiency


Level
Assessed by
Professional Skills: The ability to research, understand and H Lectures and
PSO1 implement computer programs in the areas related to algorithms, Assignments
system software, multimedia, web design, big data analytics, and
networking for efficient analysis and design of computer-based
systems of varying Skills:
Problem-Solving complexity.
The ability to apply standard practices S Tutorials
PSO2 and strategies in software project development using open-ended
programming environments to deliver a quality product for business
success.
Successful Career and Entrepreneurship: The ability to employ S Seminars and
PSO3 modern computer languages, environments, and platforms in Projects
creating innovative career paths, to be an entrepreneur, and a zest
for higher studies.

MAPPING COURSE OUTCOMES LEADING TO THE ACHIEVEMENT OF


THE PROGRAM OUTCOMES

Program
Course Program
Specific
Outcomes Outcomes
Outcomes
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO PSO3
S S S 2
1 H H S S
2 S S S S S S S S S S
3 H H S S S S S
4 H H H S S S S S S
5 H H S H S S S H
6 H H H S H S S S H S S S
7 S S H S S S S S S H S S
8 S S H S S S S S S S S S
9 H H S S S H H S S
10 S S S S S S S S S S
11 H H S S S S S
12 S S H S S S S S S H S S
13 S S H S S S S S S S S S
14 H H S S S H H S S
15 H H H S H S S S H S S S

MAPPING OF MODEL QUESTION PAPER QUESTIONS TO THE


ACHIEVEMENT OF COURSE OUTCOMES

Question Course Outcomes


Number CO1 CO2 CO3 CO4 CO5 CO6 CO7 CO8 CO9 CO10 CO11 CO12 CO13 CO14 CO15
1(a) H
1(b) H
2(a) H
2(b) H
3(a) H
3(b) H
4(a) S H H H
4(b) H H H
5(a) H S S S H H
5(b) H S S H H
6(a) H S S H H
6(b) H S S H H
7(a) H S H H H S S H
7(b) H S H H H S S H S
8(a) H H S S H S
8(b) H H S S H
9(a) H H S S H H H
9(b) H H S S H H H
10(a) H H S S H H H
10(b) H H H S H H H

Signature of Course Coordinator HOD