Ch13 - Wafers and Chips PDF

Wafers and Chips
FIGURE 13.1 (a) A 300-mm (11.8 in.) wafer with

a large number of dies fabricated onto its
surface. (b) Detail view of an Intel 45-nm chip
including a 153 Mbit SRAM (static random
access memory) and logic test circuits. (c) Image
of the Intel® Itanium®2 processor; (d) Pentium®
processor motherboard. Source: Courtesy of
Intel Corporation.
(a) (b)
(c) (d)
Manufacturing Processes for Engineering Materials, 5th ed.

Kalpakjian • Schmid
© 2008, Pearson Education
ISBN No. 0-13-227271-7
Basic Fabrication Approach
Boron p+ Polysilicon p+
SiO2
Cross-section implant
Silicon nitride SiO2 SiO2
p-type silicon p p
(a) (b) (c)
CVD
Phosphorus or arsenic Source Al Gate Drain
SiO2
SiO2 SiO2 SiO2 SiO2 SiO2 SiO2
p p p
n+ n+ p+ n+ n+ p+ n+ n+ p+
(d) (e) (f)
FIGURE 13.2 Cross-sectional views of the fabrication of a metal oxide semiconductor (MOS) transistor. Source: After R.C. Jaeger.

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(a) Single-crystal growing
IC Fabrication Internal diameter

saw
Sequence (b) Wafer preparation
Silicon
Silicon
wafer
ingot
1 Prepared
Silicon- Photoresist silicon wafer
dioxide layer
Silicon Projected
nitride layer light
Silicon
substrate Reticle
(or mask)
Similar cycle is repeated

(c) Lithography/ 6 to lay down metal links 2 Lens
Doping/Etching cycle between transistors
Patterns are projected
Metal repeatedly onto wafer
New photoresist is spun
connector
on wafer, and steps 2 to 4
are repeated
5
All photoresist
3
is removed
Doped 4 Exposed
region photoresist
is removed
Areas unprotected
by photoresist are
etched by gases or
doped with ions
(d) Bonding
FIGURE 13.3 General fabrication sequences for integrated circuits.

(e) Packaging
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(f) Testing
Clean Rooms
100,000
(3500)
10,000
Total number of particles/ft3 equal to

or larger than stated particle size
(350) Cl
as
1000 s
Cl 10
(35) as 0,
Cl s 00
as 10 0
100 Cl s ,0 (3
as 10 00 50
(3.5) 0 (3 0)
s 0 5
Cl 1 00 ( 35 0)
10 Cl as (3 )
(.35) as s .5
s 1 0 )
1 (
(0 0.
1 .0 35
35 )
)
0.1
0.01
0.05 0.1 0.5 1.0 5 10 100
Particle diameter (µm)
FIGURE 13.4 Allowable particle size concentrations for different clean-room classes.

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Silicon Crystallographic Structure
(a) (b)
(111)
[001] (110) [001] [001]
[111]
[100] [100] [100]

[010] [010] [010]
[110]
(100)
(c)
FIGURE 13.5 Crystallographic structure and Miller indices for silicon. (a) Construction of a diamond-type
lattice from interpenetrating face-centered cubic cells (one of eight penetrating cells shown). (b) The diamond-
type lattice of silicon. The interior atoms have been shaded darker than the surface atoms. (c) Miller indices for
a cubic lattice.

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Finishing Operations on Silicon Ingot
Silicon Pulley
ingot Silicon ingot
Diamond–metal bonded wheel

Electroplated band saw
(a) (b)
Internal
Diamond–metal diameter saw
bonded wheel
Silicon
wafer
Silicon ingot Silicon

ingot
(c) (d)
FIGURE 13.6 Finishing operations on a silicon ingot

to produce wafers. (a) and (b) Grinding of the end
Polishing pad
and cylindrical surfaces of a silicon ingot; (c)
machining of a notch or flat; (d) slicing of wafers; (e)
Silicon wafer
end grinding of wafers; and (f) chemical-mechanical Diamond
polishing of wafers. edging wheel
Slurry
(e) (f)

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Wafer Identification
Primary Primary
45° flat flat
Secondary
flat
{111} n -type {111} p-type
180°
Secondary Primary Primary
flat flat flat
90°
Secondary
flat
{100} n-type {100} p-type
(a)
{110} plane {100} planes {100} plane

Secondary
FIGURE 13.7 Identification of single-crystal wafers of flat
silicon. This identification scheme is common for 150 45
mm (6 in.) diameter wafers, but notches are more Primary

flat
common for larger wafers.
(b)

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CVD and Oxide Growth
N2 Gas N2 Pressure
Wafers
sensor FIGURE 13.8 Schematic diagrams
3-zone furnace of a (a) continuous, atmospheric-
pressure CVD reactor and (b)
Pump
Heater low-pressure CVD reactor. Source:
After S.M. Sze.
Conveyor Load Gas
Exhaust belt door inlet Wafers
(a) (b)
SiO2 surface
Original
Si interface
SiO2
Silicon substrate
FIGURE 13.9 Growth of silicon dioxide, showing consumption of silicon.

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Lithography
Visible photons Electrons
Air Vacuum
Techniques
e- e-
0.5 mm
Contact mask Direct write
Resist Resist
Substrate Substrate
Photolithography Electron-beam lithography

line-widths of 2–3 µm line-widths of 0.1 µm
(a) (b)
FIGURE 13.10 Comparison of four different lithography
X-rays Ions
techniques: (a) Photolithography, (b) electron-beam
lithography, (c) X-ray lithography, and (d) ion-beam
Air
lithography.
Proximity mask
Air Vacuum
Resist Resist Direct write
Substrate Substrate
X-ray lithography Ion-beam lithography

line-widths of 0.2 µm line-widths of 0.1 µm
(c) (d)
Method Wavelength (nm) Finest feature size (nm)

Ultraviolet (Photolithography) 365 350
Deep UV 193 190
Extreme UV 10-20 30-100
X-ray 0.01-1 20-100
Electron beam - 80
Source: After P.K. Wright.
TABLE 13.1 General characteristics of lithography techniques.

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Spinning of Organic Coating
Application
Skin
Photoresist
Liquid resist
Substrate
Chuck
1. Dispense 2. Spread cycle
Liquid resist
Evaporation
spun out from
of solvent
beneath skin
3. Ramp-up 4. Final spin speed
FIGURE 13.11 Spinning of an organic coating on a wafer. (a) Liquid dispensed; (b) liquid is spread
over the wafer surface by spinning at low speed; (c) speed is increased, developing a uniform
coating thickness and expelling excess liquid; (d) evaporation of solvent at final spin speed to
obtain organic coating.

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Wafer Stepping and Step-and-Scan
Light source
exposes entire Light source
reticle exposes line in
reticle
Reticle with pattern Reticle with pattern
Reticle motion
Stepper
Step-and-scan optics
Wafer Wafer
Exposed image Exposed image
Wafer motion
(a) (b)
FIGURE 13.12 Schematic illustration of (a) wafer stepper technique for pattern transfer
and (b) step-and-scan technique.

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Lithography
UV radiation UV radiation
Photoresist Negative
SiO2 reticle
UV radiation Positive
reticle
1 2 3
SiO2 etched Developed image

Photoresist removed
6 5 4
FIGURE 13.13 Pattern transfer by lithography. Note that the mask in Step 3 can be
either a positive or a negative image of the pattern. Source: After W.C. Till and J.T.
Luxon.

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SCALPAL
Electron beam
Interferometer
Mask stage x,y mask

Scan
Step
x,y wafer
Lens
Aperture Interferometer
Stitching
deflector
Wafer stage Scan
Step
FIGURE 13.14 Schematic illustration of the SCALPEL process.

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PDMS Stamp Production
PDMS
Developed photoresist
Cured PDMS stamp
Silicon
substrate
(a) (b) (c)
FIGURE 13.15 Production of a polydimethylsiloxane (PDMS) mold for soft lithography. (a) A developed
photoresist is produced through standard lithography (see Fig. 13.13). (b) A PDMS stamp is cast over the
photoresist. (c) The PDMS stamp is peeled off the substrate to produce a stamp. The stamp shown has
been rotated to emphasize replication of surface features; the master pattern can be used several times.
Source: After Y. Xia and G.M. Whitesides.

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Soft Lithography
1. Prepare PDMS stamp 1. Prepare PDMS stamp
Liquid polymer
Stamp droplet
Substrate
2. Fill cavities with polymer precursor 2. Press stamp against surface; apply drop
of liquid polymer to end of stamp.
3. Press stamp against surface; allow 3. Remove excess liquid; allow polymer
precursor to cure to cure
FIGURE 13.16 Soft lithography techniques. (a) Micro-

transfer molding (µTM), and (b) micromolding in
capillaries (MIMIC). Source: After Y. Xia and G.M.
Whitesides.
4. Peel off stamp 4. Peel off stamp
(a) (b)

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Etch Rates
Etch rate (nm/min)a
Phospho- Photo-
Poly- Poly- silicate resist
Target silicon silicon, glass, Alum- Tita- (OCG-
Etchant material n+ undoped SiO2 SiN annealed inum nium 820PR)
Wet etchants
Concentrated HF (49%) Silicon oxides 0 – 2300 14 3600 4.2 > 1000 0
25:1 HF:H2 O Silicon oxides 0 0 9.7 0.6 150 – – 0
5:1 BHFb Silicon oxides 9 2 100 0.9 440 140 > 1000 0
Silicon etchant Silicon 310 100 9 0.2 170 400 300 0
(126 HNO3 :60H2 O:5NH4 F)
Aluminum etchant Aluminum <1 <1 0 0 <1 660 0 0
(16H3 PO4 :1HNO3 :1HAc:2H−2O)
Titanium etchant Titanium 1.2 – 12 0.8 210 > 10 880 0
(20 H2 O:1 H2 O2 :1HF)
Piranha Cleaning off 0 0 0 0 0 180 240 > 10
(50 H2 SO4 :1H2 O2 ) metals and
organics
Acetone (CH3 COOH) Photoresist 0 0 0 0 0 0 0 > 4000
Dry etchants
CF4 +CHF3 +He, 450W Silicon oxides 190 210 470 180 620 – > 1000 220
SF6 +He, 100W Silicon nitride 73 67 31 82 61*– > 1000 69
SF6 m 125 W Thin silicon 170 280 110 280 140 – > 1000 310
nitrides
O2 , 400W Ashing 0 0 0 0 0 0 0 340
photoresist
Notes:
a
Results are for fresh solutions at room temperature unless otherwise noted. Actual etch rates will vary with temperature
and prior use of solution, area of exposure of film, other materials present, and film impurities and microstructure.
b
Buffered hydrofluoric acid, 33% NH4F and 8.3% HF by weight.
TABLE 13.2 Comparison of etch rates.

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Etching Operations
Nitride etch SiO2 etch

Temperature Etch rate {111}/{100} rate rate p++
(◦ C) (µm/min) selectivity (nm/min) nm/min) etch stop
Wet etching
HF:HNO3 :CH3 COOH 25 1-20 – Low 10-30 No
KOH 70-90 0.5-2 100:1 <1 10 Yes
Ethylene-diamine 115 0.75 35:1 0.1 0.2 Yes
pyrochatechol (EDP)
N(CH3 )4 OH (TMAH) 90 0.5-1.5 50:1 < 0.1 < 0.1 Yes
Dry (plasma) etching
SF6 0-100 0.1-0.5 – 200 10 No
SF6 /C4 F8 (DRIE) 20-80 1-3 – 200 10 No
Source: Adapted from N. Maluf, An Introduction to Microelectromechanical Systems Engineering, Artech House,
2000.
TABLE 13.2 General characteristics of silicon etching operations.

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Etching Directionality
Undercut Mask layer {111} face
54.7°
Etch material
(e.g. silicon)
Etch front Etch front Final shape Etch front

(a) (b) (c)
FIGURE 13.17 Etching directionality. (a)

Isotropic etching: etch proceeds vertically and Temperature (°C)
horizontally at approximately the same rate; note 102
120 100 80 60 40
the significant mask undercut. (b) Orientation-
dependent etching (ODE): etch proceeds
vertically, terminating on {111} crystal planes, 101 <110>
Etch rate (µm/hour)

with little mask undercut. (c) Vertical etching:
<100>
etch proceeds vertically, with little mask 100
undercut. Source: Courtesy of K.R. Williams.
10-1
FIGURE 13.18 Etch rates of silicon at different crystallographic
<111>
orientations, using ethylene-diamine/pyrocatechol-in-water as
10-2
the solution. Source: After H. Seidel, et al., J. Electrochemical 2.5 2.7 2.9 3.1 3.3
Society, 1990, pp. 3612-3626. 1/T (3 10-3 K-1)

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Boron Etch Stop
SiO2
p+
SiO2
Si Si Si
SiO2 SiO2
1. Oxidation 2. Lithography and 3. Boron diffusion
development
Membrane
Si Si
SiO2
Orifice Orifice
4. Anisotropic etching 5. Stripping and reoxidation
FIGURE 13.19 Application of a boron etch stop and back etching to form a
membrane and orifice. Source: After I. Brodie and J.J. Murray.

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Processing Cross section Description
step
1. n Silicon Sample of n-type silicon

Processing Doped
Silicon
Oxide
Grow silicon dioxide
2.
n by oxidation
Photo-
resist
3. Apply photoresist
n
UV light
Mask Expose photoresist

4. using appropriate
lithographic mask
5. Develop photoresist
n
6. Etch silicon dioxide

n
7. Remove photoresist
n
8. p Implant boron
n
p FIGURE 13.20 Sequence in processing of a p-type

9.
n
Remove silicon dioxide
region in n-type silicon.

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Dry Etching
Neutral Volatile product
Ion
(a) (b)
Neutral Ion Volatile product Neutral Ion Volatile product
Inhibitor
(c) (d)
FIGURE 13.21 Machining profiles associated with different dry-etching techniques: (a)
sputtering, (b) chemical, (c) ion-enhanced energetic, and (d) ion-enhanced inhibitor. Source:
After M. Madou.

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Reactive Plasma Etching
1. Generation of
etchant species
6. Diffusion
2. Diffusion into bulk gas
to surface
4. Reaction
3. Adsorption 5. Desorption
Film
FIGURE 13.22 (a) Schematic
(a) (b)
illustration of reactive plasma
etching. Source: After M. Madou. (b)
Example of deep reactive ion etched
trench; note the periodic undercuts,
or scalloping. (c) Near vertical
sidewalls produced through DRIE
with an anisotropic etching process.
(d) An example of cryogenic dry
etching, showing a 145 µm deep
structure etched into Si using a 2.0
µm thick oxide masking layer. The
substrate temperature was -140°C
during etching. Source: for (b) to (d):
(c) (d)
R. Kassing and I.W. Rangelow,
University of Kassel, Germany.
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Hole Profiles
Scalloping
(a) (b) (c) (d) (e) (f)
FIGURE 13.23 Various types of holes generated from a square mask in (a) isotropic (wet)
etching, (b) orientation-dependent etching (ODE), (c) ODE with a larger hole, (d) ODE of a
rectangular hole, (e) deep reactive ion etching, and (f) vertical etching. Source: After M.
Madou.

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IC Connections
Level 0—Interconnects
Level 1—DIP
leads
Level 2—Printed
circuit board
Level 3—Busses Level 4—Cable

harness
Level Element Interconnection

example method
Level 0 Transistor within an IC IC metallization
ICs, other discrete Package leads or

Level 1
components module interconnections
Level 2 IC packages Printed circuit board
Level 3 Printed circuit boards Connectors (busses)
Level 4 Chassis or box

Connectors/cable FIGURE 13.24 Connections between
harnesses
elements in the hierarchy for integrated
Level 5 System, e.g., computer circuits.

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Interconnects & Inspection
FIGURE 13.25 (a) Scanning electron
Via Second-level microscope photograph of a two-level metal
metal
interconnect; note the varying surface
Interlevel dielectric topography. (b) Cross-section of a two-level
n+ metal interconnect structure. Source: After R.C.
SiO2
Contact First-level SiO2
Si
Jaeger.
metal
(a) (b)
FIGURE 13.26 A probe (top center) checking for

defects in a wafer; an ink mark is placed on each
defective die. Source: Intel Corp.

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Wire Bonds
(a) (b) (c)
FIGURE 13.27 (a) SEM photograph of wire bonds connecting package leads (left-hand side) to die
bonding pads. (b) and (c) Detailed views of (a). Source: Courtesy of Micron Technology, Inc.

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Thermosonic Ball-and-Stitch Process
Gold wire
Wire clamp Force
Gold wire
Bonding tip
Arc
generator Bond pad
Die Die Package lead

1. Arcing forms gold ball 2. Ball bonds while 3. Position tip over
applying heat and/or package lead
ultrasonic vibration
Wire loop Force Wire loop
Die Package lead Die Package lead

4. Stitch bond on lead 5. Break wire
FIGURE 13.28 Schematic illustration of the thermosonic ball and stitch process. Source: After N. Maluf.

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Summary of Packages
Pins
Package Abbreviation min. max. Description
Through-hole mount
Dual in-line DIP 8 64 Two in-line rows of leads.
Single in-line SIP 11 40 One in-line row of leads.
Zigzag in-line ZIP 16 40 Two rows with staggered leads.
Quad in-line package QUIP 16 64 Four in-line rows of staggered leads.
Surface mount
Small-outline IC SOIC 8 28 Small package with leads on two sides.
Thin small-outline package TSOP 26 70 Thin version of SOIC.
Small-outline J-lead SOJ 24 32 Same as SOIC, with leads in a J-shape.
Plastic leaded chip carrier PLCC 18 84 J-shaped leads on four sides.
Thin quad flat pack TQFP 32 256 Wide but thin package with leads on four sides.
TABLE 13.4 Summary of molded-plastic IC packages.

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IC Packages
Ceramic cover
Molding
compound
Monolithic circuit die

Bond wires
Eutectic Bonding pad
preform (typical 10 places)
5
Glass seal 43
2
(typical for 1
Spot plate
10 leads)
Lead frame Die Die-support Bonding wire
paddle Ceramic
6 package base
78
9
10
(a) (b)
Solder Signal/ Wire Mold Die Plated copper

ground via bond compound pad conductor
Through hole Butt joint
Solder BT epoxy IC Thermal/ Solder

Crow!s foot Gull wing mask PCB ground via bump
(c) (d)
FIGURE 13.29 Schematic illustration of various IC packages: (a) dual in-line (DIP), (b) ceramic flat pack, (c)
common surface-mount configurations, and (d) ball-grid array (BGA). Source: After R.C. Jaeger, A.B. Glaser,
and G.E. Subak-Sharpe.

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Flip Chips
IC
(a) (b)
(c) (d)
FIGURE 13.30 Illustration of flip-chip technology. (a) Flip-chip package with solder-plated metal balls
and pads on the printed circuit board, (b) flux application and placement, (c) reflow soldering, and (d)
encapsulation. Source: After P.K. Wright.

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Printed Circuit Boards
Surface signal
track
DIP package Insertion hole Buried
via hole
Internal signal track

Solder
Insulation layers
Lead
Partially buried Surface mount

via hole land
Internal
Gull wing signal track
surface mount lead
removed for clarity
Via hole
FIGURE 13.31 Printed circuit board structures and design features.

ISBN No. 0-13-227271-7
Example: Accelerometer
Stationary
polysilicon fingers
Spring (beam)
Suspended inertial mass
Direction of acceleration
C1
C2
Anchor to
substrate
FIGURE 13.32 The Analog Devices ADXL-50 accelerometer. This MEMS-based product contains a
surface-micromachined sensor, on-chip excitation, self-test, and signal-controlling circuitry. The
schematic illustration shows the structure of the suspended mass. The entire chip measures 0.500 mm
x 0.625 mm. Source: Courtesy of Analog Devices, Inc.

ISBN No. 0-13-227271-7
Bulk and Surface Micromachining
Substrate Diffused layer Non-etching mask Free-standing (111) planes
FIGURE 13.33 Schematic
(e.g. n-type Si) (e.g. p-type Si) (e.g. silicon nitride) cantilever illustration of the steps in bulk
micromachining. (1) Diffuse
dopant in desired pattern, (2)
deposit and pattern masking
film, and (3) orientation-
dependent etch, leaving behind a
1. 2. 3. freestanding structure. Source:
After K.R. Williams.
Phosphosilicate glass
(spacer layer) Polysilicon
FIGURE 13.34 Schematic illustration of the

Silicon
steps in surface micromachining. (1) deposition
of a phosphosilicate glass (PSG) spacer layer, (2) (a) Step 1 (b) Step 2 (c) Step 3
etching of spacer layer, (3) deposition of
polysilicon, (4) etching of polysilicon, and (5)
selective wet etching of PSG, leaving the silicon Suspended
cantilever
substrate and the deposited polysilicon
unaffected.

(d) Step 4 (e) Step 5
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Bulk & Surface Micromachining Example
Film 2 mm thick
Cavity 0.1 mm across
FIGURE 13.35 A microlamp produced by a combination of bulk and surface

micromachining processes. Source: K.R. Williams, Agilent Technologies.

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Stiction after Wet Etching
Polysilicon beam Spacer oxide Rinse water
Substrate
1. 2.
3.
FIGURE 13.36 Stiction after wet etching. (1) Unreleased beam, (2) released beam before drying, and (3)
released beam pulled to the surface by capillary forces during drying. Once contact is made, adhesive
forces prevent the beam from returning to its original shape. Source: After B. Bhushan.

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Fabrication of Micromirror
FIGURE 13.37 (a) SEM image of a

deployed micromirror and (b) detail of
the micromirror hinge. Source: Sandia
National Laboratories.
(a) (b)
Spacer layer 1 Poly1 Spacer layer 2
FIGURE 13.38 Schematic illustration of the steps

in manufacturing a hinge. (1) Deposition of a
phosphosilicate glass (PSG) spacer layer and
polysilicon layer (see Fig. 13.34), (2) deposition of Silicon
a second spacer layer, (3) selective etching of the (a) Step 1 (b) Step 2 (c) Step 3
PSG, (4) deposition of polysilicon to form a staple
Poly2
for the hinge, and (5) after selective wet etching
of the PSG, the hinge can rotate.

(d) Step 4 (e) Step 5
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SCREAM Process
Photoresist Oxide
Silicon
1. Deposit oxide and 2. Lithography and 3. Silicon etching

photoresist oxide etching
Suspended Sharp
beam tip
4. Coat sidewalls with 5. Remove oxide at bottom 6. Plasma etching in SF6

PECVD oxide and etch silicon to release structures
FIGURE 13.39 Steps involved in the SCREAM process. Source: After N. Maluf.

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SIMPLE
Photoresist Oxide Suspended feature
p- p- n+
n+
p- Silicon p-
1. Deposit oxide and 2. Lithography and 3. Plasma etching 4. Isotropic etching of

photoresist on oxide etching p+ doped silicon n- doped silicon
layered substrate
FIGURE 13.40 Schematic illustration of silicon micromachining by the single-step plasma etching (SIMPLE) process.

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Glass reticle
Mask
Oxide Silicon
Silicon Fusion
Resist
Oxide
Silicon
Silicon
Silicon
Bonding &
1. Expose resist 2. Etch cavity
Embedded cavity
3. Silicon-diffusion bonding DRIE
Resist
Suspended beam
CMOS circuits
4. Fabricate CMOS 5. Expose resist 6. Etch (DRIE) beam

(a)
FIGURE 13.41 (a) Schematic illustration of silicon fusion bonding

combined with deep reactive ion etching to produce large
suspended cantilevers. Source: After N. Maluf. (b) A micro-fluid-flow
device manufactured by applying the DRIE process to two separate
wafers and then aligning and silicon fusion bonding them together.
Afterward, a Pyrex layer (not shown) is anodically bonded over the
top to provide a window for observing fluid flow. Source: After
K.R. Williams.
100 µm
(b)

ISBN No. 0-13-227271-7
Example: Inkjet Printer
FIGURE 13.42 Sequence of operations of a thermal ink-jet printer.
Ink Bubble
(1) Resistive heating element is turned on, rapidly vaporizing the
ink and forming a bubble. (2) Within five microseconds, the bubble
has expanded and displaced liquid ink from the nozzle. (3) Surface
Heating element
tension breaks the ink stream into a bubble, which is discharged at
1. Actuation 2. Droplet formation high velocity. The heating element is turned off at this time, so that
the bubble collapses as heat is transferred to the surrounding ink.
Satellite droplets
(4) Within 24 microseconds, an ink droplet (and undesirable
satellite droplets) are ejected, and surface tension of the ink draws
3. Droplet ejection 4. Liquid refills
more liquid from the reservoir. Source: From F.G. Tseng,
“Microdroplet Generators,” in M. Gad-el-hak (ed.), The MEMS
Handbook, CRC Press, 2002.
Phosphosilicate Silicon
glass nitride
Silicon
Silicon dioxide
FIGURE 13.43 The manufacturing sequence for 1. Silicon nitride deposition 2. Wet etch manifold, 3. Wet etch, enlarge
producing thermal ink-jet printer heads. Source: remove PSG chamber
From F.G. Tseng, “Microdroplet Generators,'” in

Tantalum Aluminum
M. Gad-el-hak (ed.), The MEMS Handbook, CRC heater interconnect
Press, 2002.
4. Heater and interconnection 5. Laser nozzle

Manufacturing Processes for Engineering Materials, 5th ed. formulation
ISBN No. 0-13-227271-7
Synchrotron radiation
Mold cavity
LIGA
Mask membrane
Absorber structure
1. Mold insert (from LIGA)
PMMA Resist
Substrate
1. Irradiation Plastic
Electrically
conductive
substrate
PMMA Structure
2. Mold filling
2. Developing
Plastic structure
as mold or final
product
Metal
PMMA Resist
3. Mold removal
Metal from FIGURE 13.44 The LIGA (lithography,

electroforming or
ceramic from slip
electrodeposition, and molding) technique. (a)
3. Electroforming
casting Primary production of a metal product or
4. Second electroforming mold insert. (b) Use of the primary part for
secondary operations, or replication. Source:
Courtesy of IMM Institute für Mikrotechnik.
Metal or ceramic
structure
Final product Mold insert
4. Resist removal 5. Final product
(a) (b)

ISBN No. 0-13-227271-7
Electroforming & Mold Production
500 µm 100 µm
FIGURE 13.45 (a) Electroformed nickel

structures. (b) Detail of nickel lines and
spaces. Source: After T. Christenson, The
MEMS Handbook, CRC Press, 2002.
(a) (b)
Production technique
LIGA Laser machining EDM
Aspect ratio 10-50 10 up to 100
Surface roughness < 50 nm 100 nm 0.3-1 µm
Accuracy < 1 µm 1-3 µm 1-5 µm
Mask Required? Yes No No
Maximum height 1-500 µm 200-500 µm µm to mm
TABLE 13.5 Comparison of micromold Source: L. Weber, W. Ehrfeld, H. Freimuth, M. Lacher, M. Lehr,
and P. Pech, SPIE Micromachining and Microfabrication Process
manufacturing techniques.
Technology II, Austin, TX, 1996.

ISBN No. 0-13-227271-7
Rare-Earth Magnet
10 ksi
Rare-earth powder
Production
and binder
PMMA mold
Sacrificial layer
(copper) Substrate (alumina)
1. Press 2. Lap
35 kOe
3. Magnetize 4. Release
(a) (b)
FIGURE 13.46 Fabrication process used in producing FIGURE 13.47 SEM images of Nd2Fe{14}B
rare-earth magnets for microsensors. Source: After T. permanent magnets. Powder particle size ranges
Christenson, Sandia National Laboratories. from 1 to 5 µm; the binder is a methylene-
chloride resistant epoxy. Mild distortion is present
Energy product in the image, due to magnetic perturbation of the
Material (Gauss-Oersted ×10−6 ) imaging electrons. Maximum-energy products of 9
Carbon steel 0.20 MGOe have been obtained with this process.
36% cobalt steel 0.65 Source: T. Christenson, in Gad-el-Hak, (ed.), The
Alnico I 1.4 MEMS Handbook, CRC Press, 2002.
Vicalloy I 1.0
Platinum-cobalt 6.5
Nd2 Fe14 B, fully dense 40
Nd2 Fe14 B, bonded 9
TABLE 13.6 Comparison of properties of permanent-

magnet materials.
ISBN No. 0-13-227271-7
Wafer-Scale Diffusion Bonding
Alumina substrate
Sacrificial
layer
Alignment
gauge pin
Nickel substrate (structural)
Diffusion bond and release
All-nickel structure
(a) (b)
FIGURE 13.48 (a) Multilevel MEMS fabrication through wafer-scale diffusion bonding. (b) A
suspended ring structure, for measurement of tensile strain, formed by two-layer wafer-
scale diffusion bonding. Source: After T. Christenson, Sandia National Laboratories.

ISBN No. 0-13-227271-7
HEXSIL Process
1. Etch deep in silicon wafer 6. Deposit electroless nickel
2. Deposit sacrificial oxide 7. Lap and polish to oxide layer
3. Deposit undoped poly
8. HF etch release and mold ejection
9. Go to step 2: Repeat mold cycle
4. Deposit in-situ doped poly Wafer
Sacrificial oxide
Undoped poly
FIGURE 13.49 Illustrations of the HEXagonal honeycomb
structure, SILicon micromachining, and thin-film deposition
Doped poly (HEXSIL process).
5. Blanket etch planar
surface layer to oxide Electroless nickel

ISBN No. 0-13-227271-7
HEXSIL Example
(a) (b)
FIGURE 13.50 (a) SEM image of micro-scale tweezers, used in microassembly and
microsurgery. (b) Detailed view of the tweezers. Source: Courtesy of MEMS Precision
Instruments.

ISBN No. 0-13-227271-7
Instant Masking
Developed mask Elastomeric Selectively

(elastomer) insulator deposited material
+ Anode
Substrate Plating Substrate Substrate

bath
1. 2. 3.
FIGURE 13.51 The instant masking process: (1) bare substrate, (2) during deposition, with
the substrate and instant mask in contact, and (3) the resulting pattern deposit. Source: After
A. Cohen, MEMGen Corporation.

ISBN No. 0-13-227271-7
Carbon Nanotubes
Graphite structure
Zigzag Chiral
Armchair
FIGURE 13.52 Forms of carbon nanotubes: armchair, zigzag, and chiral. Armchair nanotubes are noteworthy
for their high electrical conductivity, whereas zigzag and chiral nanotubes are semiconductors.

ISBN No. 0-13-227271-7
Case Study:
Mirror
Mirror -10 Hinge Mirror +10

Mirror support
Digital
post
Landing tips
Micromirror
Address
Yoke
electrode
Torsion hinge
Electrode
Device
Hinge support post
support post
Landing
sites
Metal 3 Yoke Landing CMOS
address pads tip substrate
Bias/Reset
bus
FIGURE 13.53 The Texas Instruments
To SRAM
(a) (b)
Digital Pixel Technology (DPTTM)
Device. (a) Exploded view of a single
digital micromirror device (DMDTM);
(b) view of two adjacent DMD pixels;
(c) images of DMD arrays, with some
mirrors removed for clarity; each
mirror measures approximately 17 µm
(670 µin.) on a side; (d) a typical DPT
device, used for digital projection
systems, high definition televisions, and
other image display systems. The device
shown contains 1,310,720
(c) (d)
micromirrors and measures less than
50 mm (2 in.) per side. Source: Texas
Instruments Corp.
ISBN No. 0-13-227271-7
Fabrication Sequence for Case Study
CMOS Sacrificial CMP Hinge Yoke Hinge post
Metal-3 level spacer-1 oxide
Silicon substrate with CMOS circuits

1. Pattern spacer-1 layer 4. Etch yoke and strip oxide
Mirror Mirror mask Spacer-2
Oxide hinge mask Hinge metal
2. Deposit hinge metal; deposit 5. Deposit spacer-2 and mirror

and pattern oxide hinge mask
Mirror Mirror post
Yoke metal Oxide mask

Yoke Hinge
FIGURE 13.54 Manufacturing sequence for the Texas Instruments

DMD device.
3. Deposit yoke and pattern 6. Pattern mirror and etched
yoke oxide mask sacrificial spacers

ISBN No. 0-13-227271-7
Ceramic Flat Package for DMD
Hermetic optical window DMD
(Corning 7056)
Glass-to-metal Gold wire bonds
fused seal
Kovar frame
Seam weld
Kovar seal ring
Ceramic header Zeolite getters
Heat sink
FIGURE 13.55 Ceramic flat package construction used for the DMD device. See also Fig. 13.29.

ISBN No. 0-13-227271-7

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Wafers and Chips

FIGURE 13.1 (a) A 300-mm (11.8 in.) wafer with

Manufacturing Processes for Engineering Materials, 5th ed.

(a) (b) (c)

SiO2 SiO2 SiO2 SiO2 SiO2 SiO2

Manufacturing Processes for Engineering Materials, 5th ed.

IC Fabrication Internal diameter

Sequence (b) Wafer preparation

Similar cycle is repeated

FIGURE 13.3 General fabrication sequences for integrated circuits.

Total number of particles/ft3 equal to

Manufacturing Processes for Engineering Materials, 5th ed.

[100] [100] [100]

Manufacturing Processes for Engineering Materials, 5th ed.

Diamond–metal bonded wheel

Silicon ingot Silicon

FIGURE 13.6 Finishing operations on a silicon ingot

Manufacturing Processes for Engineering Materials, 5th ed.

{110} plane {100} planes {100} plane

mm (6 in.) diameter wafers, but notches are more Primary

Manufacturing Processes for Engineering Materials, 5th ed.

FIGURE 13.9 Growth of silicon dioxide, showing consumption of silicon.

Manufacturing Processes for Engineering Materials, 5th ed.

Photolithography Electron-beam lithography

Resist Resist Direct write

X-ray lithography Ion-beam lithography

Method Wavelength (nm) Finest feature size (nm)

TABLE 13.1 General characteristics of lithography techniques.

Manufacturing Processes for Engineering Materials, 5th ed.

3. Ramp-up 4. Final spin speed

Manufacturing Processes for Engineering Materials, 5th ed.

Exposed image Exposed image

Manufacturing Processes for Engineering Materials, 5th ed.

SiO2 etched Developed image

Manufacturing Processes for Engineering Materials, 5th ed.

Mask stage x,y mask

Wafer stage Scan

FIGURE 13.14 Schematic illustration of the SCALPEL process.

Manufacturing Processes for Engineering Materials, 5th ed.

(a) (b) (c)

Manufacturing Processes for Engineering Materials, 5th ed.

FIGURE 13.16 Soft lithography techniques. (a) Micro-

Manufacturing Processes for Engineering Materials, 5th ed.

TABLE 13.2 Comparison of etch rates.

Manufacturing Processes for Engineering Materials, 5th ed.

Nitride etch SiO2 etch

TABLE 13.2 General characteristics of silicon etching operations.

Manufacturing Processes for Engineering Materials, 5th ed.

Etch front Etch front Final shape Etch front

FIGURE 13.17 Etching directionality. (a)

Etch rate (µm/hour)

Manufacturing Processes for Engineering Materials, 5th ed.

Manufacturing Processes for Engineering Materials, 5th ed.

1. n Silicon Sample of n-type silicon

Mask Expose photoresist

6. Etch silicon dioxide

p FIGURE 13.20 Sequence in processing of a p-type

Manufacturing Processes for Engineering Materials, 5th ed.

Neutral Ion Volatile product Neutral Ion Volatile product

Manufacturing Processes for Engineering Materials, 5th ed.

Manufacturing Processes for Engineering Materials, 5th ed.

Level 3—Busses Level 4—Cable

Level Element Interconnection