III
Andrew Menezes
BT13ECE088
1) PACKAGE
CODE:
library ieee;
use ieee.std_logic_1164.all;
package packed is
component ANDTWO is
port(a,b:in bit;
y:out bit);
end component;
component ORTWO is
port(a,b:in bit;
y:out bit);
end component;
component NORTWO is
port(a,b:in bit;
y:out bit);
end component;
component NANDTWO is
port(a,b:in bit;
y:out bit);
end component;
component XORTWO is
port(a,b:in bit;
y:out bit);
end component;
component XNORTWO is
port(a,b:in bit;
y:out bit);
end component;
function risingedge (wave:std_logic) return std_logic;
function convert (digit:integer) return std_logic_vector;
end packed;
CONCLUSION:
The package and package body for gates and both functions
were written using VHDL code.
2) 4 BIT BINARY UP COUNTER
entity upcounter is
port(CLOCK,RESET : in std_logic;
COUNT : out std_logic_vector(3 downto 0));
end upcounter;
WAVEFORMS:
TECHNOLOGY MAPS:
CONCLUSION:
A four bit binary up counter was designed using if…else
statements.