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1 1

VFKTA
2
Rosetta 10FT/10FTG 2

LA-9862P REV 1.0 Schematic


Intel Processor (Ivy Bridge/Sandy Bridge)+
3 PCH(Panther Point) 3

2013-02-06 Rev 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 1 of 46
A B C D E
A B C D E

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Intel CPU
Ivy Bridge Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
17W Dual Channel page 11,12
BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333/1600 MT/s
1
BGA-1023 1

31mm*24mm

page 5,6,7,8,9,10
eDP 1.1 2x
2.7GT/s

FDI X8 DMI X4
2.7GT/s 5GT/s

USB30 2x
LVDS & eDP Conn. 5V 5GT/s USB Right
USB20 port 0,1
USB20 3x USB30 port 1,2
page 13 page 29
5V 480MHz

2
Intel PCH USB20 2x CardReader GL834L Int. Camera 2
HDMI Conn. Panther Point 5V 480MHz USB20 port 8
page 28
USB port 11
page 22
page 15

FCBGA-989
RJ45 RTL8106E & 8111G PCIe Gen1 1x PCIe Gen1 1x PCIeMini Card WLAN and BT
PCIe port 1 1.5V 5GT/s 25mm*25mm 1.5V 5GT/s
Conn. page 27
PCIe port 2 &USB port 9
page 26
USB20 2x
USB20 2x 5V 480MHz
5V 480MHz
USB Left
USB20 port 2
page 27 SATA Gen3 1x SATA HDD
SATA port 0
5V 6GHz(600MB/s) page 25
To sub-board
SATA Gen2 1x SATA ODD
5V 3GHz(300MB/s) SATA port 2
page 16,17,18,19,20,21,22,23,24 page 25

3 3

LPC BUS HD Audio


3.3V 33 MHz 3.3V 24MHz

RTC CKT. SPI ROM


page 16
KB9012 HDA Codec
(4MB) page 16 page 32 ALC259/269
page 30
DC/DC Interface CKT.
page 34

Touch Pad Int.KBD G-Sensor LED+LID/B SPK Conn JPIO


page 31
Power Circuit DC/DC page 33 page 33 page 25 page 33 (HP &page
MIC)31
page 35,36,37,38,39,40,
41,42,43

GCLK
4
SLG3NB244VTR 4
page 26

Power/B
page 33
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
To sub-board Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 2 of 46
A B C D E
5 4 3 2 1

http://laptopblue.vn/ DESIGN CURRENT 0.1A +3VL


B+
Ipeak=8.5A, Imax=5.95A, Iocp min=10.2 DESIGN CURRENT 5A +5VALW
PCH_PWR_EN#

P-CHANNEL
+5VALW_PCH
SUSP# AO-3413
D D

DESIGN CURRENT 2A +1.8VS


SY8032ABC

SUSP#

DESIGN CURRENT 6A +5VS


TPS22966DPUR

RT8243AZQW KB_LED
DESIGN CURRENT 400mA +5VS_LED
P-CHANNEL
AO-3413

+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191-330T1U

ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413

Ipeak=5A, Imax=3.5A, Iocp min=6.12A DESIGN CURRENT 5A +3VALW

DESIGN CURRENT 330mA +3V_LAN


C C
WOWL_EN#
DESIGN CURRENT 3A +3V_WLAN
P-CHANNEL
AO-3413

PCH_PWR_EN#

P-CHANNEL
+3VALW_PCH
AO-3413
SUSP#

DESIGN CURRENT 6A +3VS


TPS22966DPUR
LCD_ENVDD

DESIGN CURRENT 1.5A +LCD_VDD


APL3512ABI

VR_ON
DESIGN CURRENT 65A +CPU_CORE
ISL95833HRTZ DESIGN CURRENT 40A
B +GFX_CORE B

SUSP#

Ipeak=14.37A, Imax=10.06A, Iocp min=17.24A +1.05VS_VCCP


SY8208DQNC

VCCP_PWRGOOD
DESIGN CURRENT 6A +VCCSA
G978F11U
SYSON
Ipeak=16.66A, Imax=11.66A, Iocp min=20A DESIGN CURRENT 2A +1.5V
RT8207MZQW 0.75VR_ON
DESIGN CURRENT 1.5A +0.75VS
SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU


FDS6676AS
DESIGN CURRENT 2A +1.5VS
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 3 of 46
5 4 3 2 1
A B C D E

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( O MEANS ON X MEANS OFF )
Voltage Rails BTO Option Table
+5VS Function CPU PCH
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW description IVB i5 3337U IVB i3 3227U IVB i3 2375M IVB P 2117U IVB C 847 Panther Point
+1.8VS
+VSB explain IVB i5 3337U IVB i3 3227U IVB i3 2375M IVB P 2117U IVB C 847 HM76 HM70
power +1.5VS
plane CPUI53337UR1@ CPUI33227UR1@ CPUI32375MR1@ CPUP2117UR1@ CPUC847R1@ HM76R1@ HM70R1@
+1.5V_CPU
BTO CPUI53337UR3@ CPUI33227UR3@ CPUI32375MR3@ CPUP2117UR3@ CPUC847R3@ HM76R3@ HM70R3@
1
+0.75VS 1

+CPU_CORE
+GFX_CORE Function LVDS-eDP Camera & Mic USB S&C CRT EC
+VCCSA
description LVDS-eDP Camera & Mic 14640 14641 CRT EC
+1.05VS_VCCP
State
+3V_WLAN explain LVDS eDP Camera & Mic 14640 14641 w/ CRT w/o CRT KB9012 NPCE885N
+3V_LAN
BTO LVDS@ IEDP@ CAM_EMI@ 14640@ 14641@ CRT@ CRT_EMI@ NOCRT@ 9012@ 885@
+LCD_VDD

Function WOWL G-SENSOR ZPODD GCLK Touch Screen


S0
O O O O O O description WOWL G-SENSOR ZPODD GCLK non-GCLK Touch Screen

S1 explain w/ w/o G-SENSOR w/ w/o GCLK non-GCLK Touch Screen


O O O O O O
BTO WOWL@ NOWOWL@ GSENSOR@ ZPODD@ NONZP@ GCLK@ NOGCLK@ TOUCH_EMI@
S3
O O O O O X
2 2
S5 S4/AC Function Sleep & Music KB Light EMI/ESD/RF part ISPD
O O O O X X
S5 S4/ Battery only
description Sleep & Music KB Light EMI/ESD/RF part HDMI Logo
O O O X X X
explain w/ S&M w/o S&M KB Light EMI/ESD/RF part HDMI Logo
S5 S4/AC & Battery
don't exist O X X X X X BTO 269@ 259@ KBL@ EMI@ @EMI@ ESD@ @ESD@ @RF@ HDMI45@

Red Word: always un-mount


PCH SM Bus Address

Power Device HEX Address


+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b

+3VS Touch Pad 2C H 0010 1100 b

3 3

SIGNAL
EC SM Bus1 Address EC SM Bus2 Address STATE SLP_S3# SLP_S4# SLP_S5#

Full ON HIGH HIGH HIGH


Power Device HEX Address Power Device HEX Address
S1(Power On Suspend) HIGH HIGH HIGH
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b
+3VL Smart Charger 12 H 0001 0010 b +3VS G-Sensor 40 H 0100 0000 b S3 (Suspend to RAM) LOW HIGH HIGH
+3VL USB S&C 14640 35 H 0011 0101 b
S4 (Suspend to Disk) LOW LOW HIGH
Power Device HEX Address 10/22A Add G-sensor reference Hemen S5 (Soft OFF) LOW LOW LOW

G3 LOW LOW LOW

10/22A Add Smart Charger SMBus address: 0x12 Hemen


we Add already
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 4 of 46
A B C D E
A B C D E

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UC1B Stuff RC158&RC157 if do not support eDP
100 MHz
J3 CLK_CPU_DMI
BCLK H2 CLK_CPU_DMI# CLK_CPU_DMI 17 +1.05VS_VCCP
BCLK# CLK_CPU_DMI#17

MISC
@

CLOCKS
1000P_0402_50V7K 2 1 CC62 PM_DRAM_PWRGD_R 21 H_SNB_IVB# F49 120 MHz LVDS@
H_SNB_IVB# PROC_SELECT# AG3 CLK_CPU_EDP CLK_CPU_EDP# RC1571 2 1K_0402_5%
DPLL_REF_CLK AG1 CLK_CPU_EDP# CLK_CPU_EDP 17
ESD@
1 2 CC63 C57 DPLL_REF_CLK# CLK_CPU_EDP#17
180P_0402_50V8J H_PWRGOOD_R T1 PAD TP@ TP_SKTOCC# CLK_CPU_EDP RC1581 2 1K_0402_5%
PROC_DETECT# LVDS@
ESD@ 11/30 Change CC63 from @ESD@
1 2 H_THERMTRIP# to ESD@ for ESD request
CC20 T2 PAD TP@ H_CATERR# C49 @ESD@
100P_0402_50V8J CATERR# H_DRAMRST# 1 2

THERMAL
1 CC34 180P_0402_50V8J 1

H_PECI A48 AT30 H_DRAMRST#


32 H_PECI PECI SM_DRAMRST# H_DRAMRST# 7
by ESD requestion and place near CPU by ESD requestion and place near CPU
RC159 BF44 SM_RCOMP_0 RC56 2 1 140_0402_1% DDR3 Compensation Signals
SM_RCOMP[0]

DDR3
MISC
+1.05VS_VCCP 1 2 H_PROCHOT#_R C45 BE43 SM_RCOMP_1 RC59 2 1 25.5_0402_1% Layout Note:Place these
32 H_PROCHOT# PROCHOT# SM_RCOMP[1]
56_0402_5% BG43 SM_RCOMP_2 RC61 2 1 200_0402_1% resistors near Processor
SM_RCOMP[2]
RC44 2 1 62_0402_5% H_PROCHOT#
H_THERMTRIP# D45
21 H_THERMTRIP# THERMTRIP#
H_DRAMRST# 1 2 ESD@
RC45 2 1 10K_0402_5% H_PWRGOOD N53
CC35 100P_0402_50V8J
PRDY# N55
PREQ#
L56 XDP_TCK T3 PAD TP@
TCK L55 XDP_TMS T4 PAD TP@
TMS

PWR MANAGEMENT
J58 XDP_TRST# 1 2 Routed as a single daisy chain
TRST# RC55 51_0402_5%

JTAG & BPM


@ H_PM_SYNC C48 M60 XDP_TDI
18 H_PM_SYNC PM_SYNC TDI
1000P_0402_50V7K 2 1 CC70 H_PECI L59 XDP_TDO T6 PAD TP@
TDO T7 PAD TP@
@
1000P_0402_50V7K 2 1 CC67 H_PM_SYNC 21 H_PWRGOOD
1 2 H_PWRGOOD_R B46
Rshort@
UNCOREPWRGOOD K58
RC183 0_0402_5%
DBR# Close to CPU side
@
1000P_0402_50V7K 2 1 CC66 BUF_CPU_RST#
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R BE45 G58
RC170 130_0402_5% SM_DRAMPWROK BPM#[0] E55
BPM#[1] E59
BPM#[2] G55
2 Please place near JCPU BPM#[3] G59 2
BUF_CPU_RST# D44 BPM#[4] H60
RESET# BPM#[5] J59
BPM#[6] J61
BPM#[7]
+3VALW_PCH

2 1 DRAMPWROK +3VALW_PCH
RC11 200_0402_5% +1.5V_CPU

IVY-BRIDGE_BGA1023 <BOM>
1

02/20 Delete CC33 0.1U CPU@

RC14
UC3 200_0402_5%
5

10K_0402_5% 74AHC1G09GW_TSSOP5
2

2 RC13 1 1
P

+3VS B 4 PM_SYS_PWRGD_BUF
DRAMPWROK 2 O
18 DRAMPWROK A
G
3

3 3

Buffered Rest to CPU XDP Connector FAN Control Circuit


+3VS
For power consumption
+5VS +3VS
02/20 Delete CC36 0.1U

1
1A Rshort@
+1.05VS_VCCP 1 2 R2 JFAN Conn@
PLT_RST# 20,26,27,32
R1 10K_0402_5% 6
0_0603_5% 5 GND
GND
1

UC2 4

2
PLT_RST# 1 RC38 3 4
OE# 32 FANPWM 3
5 75_0402_5% 2
VCC 32 FAN_SPEED1 2
+FAN1 1
2 RC35 1
2

IN 43_0402_1%
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# 02/20 change R1 to short pad ACES_50273-0040N-001
3 OUT for part count reduce
GND 02/20 Delete C4 0.01U
74AHC1G125GW_SOT353-5

1
1
D1 C5
4 4
BAS16_SOT23-3 2

2
10U_0603_6.3V6M

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_JTAG/XDP/FAN
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 5 of 46
A B C D E
A B C D E

http://laptopblue.vn/ +1.05VS_VCCP
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 m ohm (4 mils)

1
RC1 PEG_ICOMPO signals should be routed with -
24.9_0402_1% max length = 500 mils
UC1A
- typical impedance = 14.5 m ohm (12 mils)

2
G3 PEG_COMP
PEG_ICOMPI G1
1 DMI_PTX_CRX_N0 M2 PEG_ICOMPO G4 1
18 DMI_PTX_CRX_N0 DMI_RX#[0] PEG_RCOMPO
DMI_PTX_CRX_N1 P6
18 DMI_PTX_CRX_N1 DMI_RX#[1]
DMI_PTX_CRX_N2 P1
18 DMI_PTX_CRX_N2 DMI_RX#[2]
DMI_PTX_CRX_N3 P10 H22
18 DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0] J21
DMI_PTX_CRX_P0 N3 PEG_RX#[1] B22
18 DMI_PTX_CRX_P0 DMI_RX[0] PEG_RX#[2]
DMI_PTX_CRX_P1 P7 D21
18 DMI_PTX_CRX_P1 DMI_RX[1] PEG_RX#[3]

DMI
DMI_PTX_CRX_P2 P3 A19
18 DMI_PTX_CRX_P2 DMI_RX[2] PEG_RX#[4]
DMI_PTX_CRX_P3 P11 D17
18 DMI_PTX_CRX_P3 DMI_RX[3] PEG_RX#[5] B14
DMI_CTX_PRX_N0 K1 PEG_RX#[6] D13
DMI_CTX_PRX_N0 18 DMI_TX#[0] PEG_RX#[7]
DMI_CTX_PRX_N1 M8 A11
DMI_CTX_PRX_N1 18 DMI_TX#[1] PEG_RX#[8]
DMI_CTX_PRX_N2 N4 B10
DMI_CTX_PRX_N2 18 DMI_TX#[2] PEG_RX#[9]
DMI_CTX_PRX_N3 R2 G8
DMI_CTX_PRX_N3 18 DMI_TX#[3] PEG_RX#[10] A8
DMI_CTX_PRX_P0 K3 PEG_RX#[11] B6
DMI_CTX_PRX_P0 18 DMI_TX[0] PEG_RX#[12]
DMI_CTX_PRX_P1 M7 H8
DMI_CTX_PRX_P1 18 DMI_TX[1] PEG_RX#[13]
DMI_CTX_PRX_P2 P4 E5
DMI_CTX_PRX_P2 18 DMI_TX[2] PEG_RX#[14]
DMI_CTX_PRX_P3 T3 K7
DMI_CTX_PRX_P3 18 DMI_TX[3] PEG_RX#[15]
K22
PEG_RX[0] K19
PEG_RX[1] C21
FDI_CTX_PRX_N0 U7 PEG_RX[2] D19
18 FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
FDI_CTX_PRX_N1 W11 C19
18 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
FDI_CTX_PRX_N2 W1 D16
18 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
FDI_CTX_PRX_N3 AA6 C13
18 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
FDI_CTX_PRX_N4 W6 D12
18 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
FDI_CTX_PRX_N5 V4 C11

PCI EXPRESS -- GRAPHICS


18 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
FDI_CTX_PRX_N6 Y2 C9
18 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
FDI_CTX_PRX_N7 AC9 F8
18 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]

Intel(R) FDI
C8
2 PEG_RX[11] C5 2
FDI_CTX_PRX_P0 U6 PEG_RX[12] H6
18 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
FDI_CTX_PRX_P1 W10 F6
18 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
FDI_CTX_PRX_P2 W3 K6
18 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
FDI_CTX_PRX_P3 AA7
18 FDI_CTX_PRX_P3 FDI0_TX[3]
FDI_CTX_PRX_P4 W7 G22
18 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
FDI_CTX_PRX_P5 T4 C23
18 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
FDI_CTX_PRX_P6 AA3 D23
18 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
FDI_CTX_PRX_P7 AC8 F21
18 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] H19
FDI_FSYNC0 AA11 PEG_TX#[4] C17
18 FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
FDI_FSYNC1 AC12 K15
18 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] F17
FDI_INT U11 PEG_TX#[7] F14
18 FDI_INT FDI_INT PEG_TX#[8] A15
FDI_LSYNC0 AA10 PEG_TX#[9] J14
18 FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
FDI_LSYNC1 AG8 H13
18 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] M10
PEG_TX#[12] F10
PEG_TX#[13] D9
PEG_TX#[14] J4
RC2 1 2 24.9_0402_1% EDP_COMP AF3 PEG_TX#[15]
+1.05VS_VCCP eDP_COMPIO
AD2 F22
H_EDP_HPD# AG11 eDP_ICOMPO PEG_TX[0] A23
eDP_HPD# PEG_TX[1] D24
eDP_COMP signals should be PEG_TX[2] E21
shorted near balls and AG4 PEG_TX[3] G19
routed with typical 13 H_EDP_AUXN eDP_AUX# PEG_TX[4]
AF4 B18
13 H_EDP_AUXP eDP_AUX PEG_TX[5]
impedance <25m ohm PEG_TX[6]
K17
eDP

G17
AC3 PEG_TX[7] E14
13 H_EDP_TXN0 eDP_TX#[0] PEG_TX[8]
10/24 SWAP pin H_EDP_AUXN/P AC4 C15
3 13 H_EDP_TXN1 eDP_TX#[1] PEG_TX[9] 3
AE11 K13
AE7 eDP_TX#[2] PEG_TX[10] G13
eDP_TX#[3] PEG_TX[11] K10
AC1 PEG_TX[12] G10
13 H_EDP_TXP0 eDP_TX[0] PEG_TX[13]
02/20 Swap H_EDP_TXN[0\1] to H_EDP_TXP[0\1] AA4 D8
13 H_EDP_TXP1 eDP_TX[1] PEG_TX[14]
AE10 K4
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3]

+1.05VS_VCCP IVY-BRIDGE_BGA1023 <BOM>


CPU@
2

RC10
1K_0402_5%
1

H_EDP_HPD#
1

D
2 2N7002_SOT23-3
13 CPU_EDP_HPD QC1
G
S IEDP@
3
2

IEDP@
RC9
100K_0402_5%
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_DMI/PEG/FDI
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 6 of 46
A B C D E
A B C D E

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11 DDR_A_D[0..63]
12 DDR_B_D[0..63]

UC1C UC1D

DDR_A_D0 AG6 DDR_B_D0 AL4


DDR_A_D1 AJ6 SA_DQ[0] AU36 DDRA_CLK0 DDR_B_D1 AL1 SB_DQ[0] BA34 DDRB_CLK0
SA_DQ[1] SA_CK[0] DDRA_CLK0 11 SB_DQ[1] SB_CK[0] DDRB_CLK0 12
DDR_A_D2 AP11 AV36 DDRA_CLK0# DDR_B_D2 AN3 AY34 DDRB_CLK0#
SA_DQ[2] SA_CK#[0] DDRA_CLK0# 11 SB_DQ[2] SB_CK#[0] DDRB_CLK0# 12
DDR_A_D3 AL6 AY26 DDRA_CKE0 DDR_B_D3 AR4 AR22 DDRB_CKE0
SA_DQ[3] SA_CKE[0] DDRA_CKE0 11 SB_DQ[3] SB_CKE[0] DDRB_CKE0 12
DDR_A_D4 AJ10 DDR_B_D4 AK4
DDR_A_D5 AJ8 SA_DQ[4] DDR_B_D5 AK3 SB_DQ[4]
DDR_A_D6 AL8 SA_DQ[5] DDR_B_D6 AN4 SB_DQ[5]
DDR_A_D7 AL7 SA_DQ[6] DDR_B_D7 AR1 SB_DQ[6]
1 DDR_A_D8 AR11 SA_DQ[7] DDR_B_D8 AU4 SB_DQ[7] 1
DDR_A_D9 AP6 SA_DQ[8] AT40 DDRA_CLK1 DDR_B_D9 AT2 SB_DQ[8] BA36 DDRB_CLK1
SA_DQ[9] SA_CK[1] DDRA_CLK1 11 SB_DQ[9] SB_CK[1] DDRB_CLK1 12
DDR_A_D10 AU6 AU40 DDRA_CLK1# DDR_B_D10 AV4 BB36 DDRB_CLK1#
SA_DQ[10] SA_CK#[1] DDRA_CLK1# 11 SB_DQ[10] SB_CK#[1] DDRB_CLK1# 12
DDR_A_D11 AV9 BB26 DDRA_CKE1 DDR_B_D11 BA4 BF27 DDRB_CKE1
SA_DQ[11] SA_CKE[1] DDRA_CKE1 11 SB_DQ[11] SB_CKE[1] DDRB_CKE1 12
DDR_A_D12 AR6 DDR_B_D12 AU3
DDR_A_D13 AP8 SA_DQ[12] DDR_B_D13 AR3 SB_DQ[12]
DDR_A_D14 AT13 SA_DQ[13] DDR_B_D14 AY2 SB_DQ[13]
DDR_A_D15 AU13 SA_DQ[14] DDR_B_D15 BA3 SB_DQ[14]
DDR_A_D16 BC7 SA_DQ[15] DDR_B_D16 BE9 SB_DQ[15]
DDR_A_D17 BB7 SA_DQ[16] BB40 DDRA_SCS0# DDR_B_D17 BD9 SB_DQ[16] BE41 DDRB_SCS0#
SA_DQ[17] SA_CS#[0] DDRA_SCS0# 11 SB_DQ[17] SB_CS#[0] DDRB_SCS0# 12
DDR_A_D18 BA13 BC41 DDRA_SCS1# DDR_B_D18 BD13 BE47 DDRB_SCS1#
SA_DQ[18] SA_CS#[1] DDRA_SCS1# 11 SB_DQ[18] SB_CS#[1] DDRB_SCS1# 12
DDR_A_D19 BB11 DDR_B_D19 BF12
DDR_A_D20 BA7 SA_DQ[19] DDR_B_D20 BF8 SB_DQ[19]
DDR_A_D21 BA9 SA_DQ[20] DDR_B_D21 BD10 SB_DQ[20]
DDR_A_D22 BB9 SA_DQ[21] DDR_B_D22 BD14 SB_DQ[21]
DDR_A_D23 AY13 SA_DQ[22] DDR_B_D23 BE13 SB_DQ[22]
DDR_A_D24 AV14 SA_DQ[23] AY40 DDRA_ODT0 DDR_B_D24 BF16 SB_DQ[23] AT43 DDRB_ODT0
SA_DQ[24] SA_ODT[0] DDRA_ODT0 11 SB_DQ[24] SB_ODT[0] DDRB_ODT0 12
DDR_A_D25 AR14 BA41 DDRA_ODT1 DDR_B_D25 BE17 BG47 DDRB_ODT1
SA_DQ[25] SA_ODT[1] DDRA_ODT1 11 SB_DQ[25] SB_ODT[1] DDRB_ODT1 12
DDR_A_D26 AY17 DDR_B_D26 BE18
DDR_A_D27 AR19 SA_DQ[26] DDR_B_D27 BE21 SB_DQ[26]
DDR_A_D28 BA14 SA_DQ[27] DDR_B_D28 BE14 SB_DQ[27]
DDR_A_D29 AU14 SA_DQ[28] DDR_B_D29 BG14 SB_DQ[28]
DDR_A_D30 BB14 SA_DQ[29] DDR_B_D30 BG18 SB_DQ[29]
SA_DQ[30] 11
DDR_A_DQS#[0..7] SB_DQ[30] 12
DDR_B_DQS#[0..7]
DDR_A_D31 BB17 AL11 DDR_A_DQS#0 DDR_B_D31 BF19 AL3 DDR_B_DQS#0
DDR_A_D32 BA45 SA_DQ[31] SA_DQS#[0] AR8 DDR_A_DQS#1 DDR_B_D32 BD50 SB_DQ[31] SB_DQS#[0] AV3 DDR_B_DQS#1
DDR_A_D33 AR43 SA_DQ[32] SA_DQS#[1] AV11 DDR_A_DQS#2 DDR_B_D33 BF48 SB_DQ[32] SB_DQS#[1] BG11 DDR_B_DQS#2
DDR_A_D34 AW48 SA_DQ[33] SA_DQS#[2] AT17 DDR_A_DQS#3 DDR_B_D34 BD53 SB_DQ[33] SB_DQS#[2] BD17 DDR_B_DQS#3
DDR_A_D35 BC48 SA_DQ[34] SA_DQS#[3] AV45 DDR_A_DQS#4 DDR_B_D35 BF52 SB_DQ[34] SB_DQS#[3] BG51 DDR_B_DQS#4
DDR_A_D36 BC45 SA_DQ[35] SA_DQS#[4] AY51 DDR_A_DQS#5 DDR_B_D36 BD49 SB_DQ[35] SB_DQS#[4] BA59 DDR_B_DQS#5
DDR_A_D37 AR45 SA_DQ[36] SA_DQS#[5] AT55 DDR_A_DQS#6 DDR_B_D37 BE49 SB_DQ[36] SB_DQS#[5] AT60 DDR_B_DQS#6
DDR SYSTEM MEMORY A
SA_DQ[37] SA_DQS#[6] SB_DQ[37] SB_DQS#[6]

DDR SYSTEM MEMORY B


DDR_A_D38 AT48 AK55 DDR_A_DQS#7 DDR_B_D38 BD54 AK59 DDR_B_DQS#7
DDR_A_D39 AY48 SA_DQ[38] SA_DQS#[7] DDR_B_D39 BE53 SB_DQ[38] SB_DQS#[7]
2 DDR_A_D40 BA49 SA_DQ[39] DDR_B_D40 BF56 SB_DQ[39] 2
DDR_A_D41 AV49 SA_DQ[40] DDR_B_D41 BE57 SB_DQ[40]
DDR_A_D42 BB51 SA_DQ[41] DDR_B_D42 BC59 SB_DQ[41]
DDR_A_D43 AY53 SA_DQ[42] DDR_B_D43 AY60 SB_DQ[42]
DDR_A_D44 BB49 SA_DQ[43] DDR_B_D44 BE54 SB_DQ[43]
DDR_A_D45 AU49 SA_DQ[44] AJ11 DDR_A_DQS0 DDR_A_DQS[0..7]11 DDR_B_D45 BG54 SB_DQ[44]
DDR_A_D46 BA53 SA_DQ[45] SA_DQS[0] AR10 DDR_A_DQS1 DDR_B_D46 BA58 SB_DQ[45] AM2 DDR_B_DQS0 DDR_B_DQS[0..7]12
DDR_A_D47 BB55 SA_DQ[46] SA_DQS[1] AY11 DDR_A_DQS2 DDR_B_D47 AW59 SB_DQ[46] SB_DQS[0] AV1 DDR_B_DQS1
DDR_A_D48 BA55 SA_DQ[47] SA_DQS[2] AU17 DDR_A_DQS3 DDR_B_D48 AW58 SB_DQ[47] SB_DQS[1] BE11 DDR_B_DQS2
DDR_A_D49 AV56 SA_DQ[48] SA_DQS[3] AW45 DDR_A_DQS4 DDR_B_D49 AU58 SB_DQ[48] SB_DQS[2] BD18 DDR_B_DQS3
DDR_A_D50 AP50 SA_DQ[49] SA_DQS[4] AV51 DDR_A_DQS5 DDR_B_D50 AN61 SB_DQ[49] SB_DQS[3] BE51 DDR_B_DQS4
DDR_A_D51 AP53 SA_DQ[50] SA_DQS[5] AT56 DDR_A_DQS6 DDR_B_D51 AN59 SB_DQ[50] SB_DQS[4] BA61 DDR_B_DQS5
DDR_A_D52 AV54 SA_DQ[51] SA_DQS[6] AK54 DDR_A_DQS7 DDR_B_D52 AU59 SB_DQ[51] SB_DQS[5] AR59 DDR_B_DQS6
DDR_A_D53 AT54 SA_DQ[52] SA_DQS[7] DDR_B_D53 AU61 SB_DQ[52] SB_DQS[6] AK61 DDR_B_DQS7
DDR_A_D54 AP56 SA_DQ[53] DDR_B_D54 AN58 SB_DQ[53] SB_DQS[7]
DDR_A_D55 AP52 SA_DQ[54] DDR_B_D55 AR58 SB_DQ[54]
DDR_A_D56 AN57 SA_DQ[55] DDR_B_D56 AK58 SB_DQ[55]
DDR_A_D57 AN53 SA_DQ[56] DDR_B_D57 AL58 SB_DQ[56]
DDR_A_D58 AG56 SA_DQ[57] DDR_B_D58 AG58 SB_DQ[57]
DDR_A_D59 AG53 SA_DQ[58] DDR_B_D59 AG59 SB_DQ[58]
DDR_A_D60 AN55 SA_DQ[59] DDR_A_MA[0..15] 11 DDR_B_D60 AM60 SB_DQ[59]
AN52 SA_DQ[60] BG35 AL59 SB_DQ[60] BF32 DDR_B_MA[0..15] 12
DDR_A_D61 DDR_A_MA0 DDR_B_D61 DDR_B_MA0
DDR_A_D62 AG55 SA_DQ[61] SA_MA[0] BB34 DDR_A_MA1 DDR_B_D62 AF61 SB_DQ[61] SB_MA[0] BE33 DDR_B_MA1
DDR_A_D63 AK56 SA_DQ[62] SA_MA[1] BE35 DDR_A_MA2 DDR_B_D63 AH60 SB_DQ[62] SB_MA[1] BD33 DDR_B_MA2
SA_DQ[63] SA_MA[2] BD35 DDR_A_MA3 SB_DQ[63] SB_MA[2] AU30 DDR_B_MA3
SA_MA[3] AT34 DDR_A_MA4 SB_MA[3] BD30 DDR_B_MA4
SA_MA[4] AU34 DDR_A_MA5 SB_MA[4] AV30 DDR_B_MA5
SA_MA[5] BB32 DDR_A_MA6 SB_MA[5] BG30 DDR_B_MA6
DDR_A_BS0 BD37 SA_MA[6] AT32 DDR_A_MA7 DDR_B_BS0 BG39 SB_MA[6] BD29 DDR_B_MA7
DDR_A_BS0 11 SA_BS[0] SA_MA[7] DDR_B_BS0 12 SB_BS[0] SB_MA[7]
DDR_A_BS1 BF36 AY32 DDR_A_MA8 DDR_B_BS1 BD42 BE30 DDR_B_MA8
DDR_A_BS1 11 SA_BS[1] SA_MA[8] DDR_B_BS1 12 SB_BS[1] SB_MA[8]
DDR_A_BS2 BA28 AV32 DDR_A_MA9 DDR_B_BS2 AT22 BE28 DDR_B_MA9
DDR_A_BS2 11 SA_BS[2] SA_MA[9] DDR_B_BS2 12 SB_BS[2] SB_MA[9]
BE37 DDR_A_MA10 BD43 DDR_B_MA10
3 SA_MA[10] BA30 DDR_A_MA11 SB_MA[10] AT28 DDR_B_MA11 3
SA_MA[11] BC30 DDR_A_MA12 SB_MA[11] AV28 DDR_B_MA12
DDR_A_CAS# BE39 SA_MA[12] AW41 DDR_A_MA13 DDR_B_CAS# AV43 SB_MA[12] BD46 DDR_B_MA13
DDR_A_CAS# 11 SA_CAS# SA_MA[13] DDR_B_CAS# 12 SB_CAS# SB_MA[13]
DDR_A_RAS# BD39 AY28 DDR_A_MA14 DDR_B_RAS# BF40 AT26 DDR_B_MA14
DDR_A_RAS# 11 SA_RAS# SA_MA[14] DDR_B_RAS# 12 SB_RAS# SB_MA[14]
DDR_A_WE# AT41 AU26 DDR_A_MA15 DDR_B_WE# BD45 AU22 DDR_B_MA15
DDR_A_WE# 11 SA_WE# SA_MA[15] DDR_B_WE# 12 SB_WE# SB_MA[15]

IVY-BRIDGE_BGA1023 <BOM> IVY-BRIDGE_BGA1023 <BOM>


CPU@ CPU@

+1.5V

2013/02/06 change QC3 to


1

SB00000PF00 for X1 code


RC76
1K_0402_5%

RC77
2

QC3 1K_0402_5%
3 1 1 2
S

H_DRAMRST# DDR3_DRAMRST#_R
5 H_DRAMRST# SM_DRAMRST# 11,12
2

BSS138_NL_SOT23-3
RC78
G
2

4.99K_0402_1%

11/28 Change RC73 to 0 ohm


1

4 (do not use short pad on this location) 4


02/20 Change RC73 to short pad
RC73 for part count reduce
1 Rshort@ 2 DRAMRST_CNTRL
9,17
DRAMRST_CNTRL_PCH
0_0402_5% 2013/02/06 Confim with rick_Chu ,
delete CC22 , because HW timing

2013/02/06 PVT Delete RC3.


1
CC37 Security Classification Compal Secret Data Compal Electronics, Inc.
0.047U_0402_25V6K Issued Date 2012/04/19 2015/04/19 Title
Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_DDR3
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 7 of 46
A B C D E
A B C D E

+CPU_CORE UC1F
33A
POWER http://laptopblue.vn/
8.5A
+1.05VS_VCCP
+1.05VS_VCCP

AF46
VCCIO[1]

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
AG48
VCCIO[3]

ESD@ CC17

ESD@ CC18

ESD@ CC19
AG50 1 1 1
A26 VCCIO[4] AG51
A29 VCC[1] VCCIO[5] AJ17
A31 VCC[2] VCCIO[6] AJ21
A34 VCC[3] VCCIO[7] AJ25 2 2 2
1 A35 VCC[4] VCCIO[8] AJ43 1
A38 VCC[5] VCCIO[9] AJ47
A39 VCC[6] VCCIO[10] AK50
A42 VCC[7] VCCIO[11] AK51
C26 VCC[8] VCCIO[12] AL14
VCC[9] VCCIO[13] For DDR
C27 AL15
C32 VCC[10] VCCIO[14] AL16
C34 VCC[11] VCCIO[15] AL20
C37 VCC[12] VCCIO[16] AL22
VCC[13] VCCIO[17] by ESD requestion and place near CPU
C39 AL26
C42 VCC[14] VCCIO[18] AL45
D27 VCC[15] VCCIO[19] AL48
D32 VCC[16] VCCIO[20] AM16
D34 VCC[17] VCCIO[21] AM17 11/30 install 3 CAP(100pF)CC17,CC18,CC19
D37 VCC[18] VCCIO[22] AM21 on +1.05Vs_Vccp and must close to CPU
D39 VCC[19] VCCIO[23] AM43

PEG IO AND DDR IO


D42 VCC[20] VCCIO[24] AM47
E26 VCC[21] VCCIO[25] AN20
E28 VCC[22] VCCIO[26] AN42
E32 VCC[23] VCCIO[27] AN45
E34 VCC[24] VCCIO[28] AN48
E37 VCC[25] VCCIO[29]
E38 VCC[26]
VCC[27]

CORE SUPPLY
F25
F26 VCC[28]
F28 VCC[29]
F32 VCC[30]
F34 VCC[31]
F37 VCC[32] AA14
F38 VCC[33] VCCIO[30] AA15
F42 VCC[34] VCCIO[31] AB17
G42 VCC[35] VCCIO[32] AB20
2 H25 VCC[36] VCCIO[33] AC13 2
H26 VCC[37] VCCIO[34] AD16
H28 VCC[38] VCCIO[35] AD18
H29 VCC[39] VCCIO[36] AD21
H32 VCC[40] VCCIO[37] AE14
VCC[41] VCCIO[38] For PEG
H34 AE15
H35 VCC[42] VCCIO[39] AF16
H37 VCC[43] VCCIO[40] AF18
H38 VCC[44] VCCIO[41] AF20
H40 VCC[45] VCCIO[42] AG15
J25 VCC[46] VCCIO[43] AG16
J26 VCC[47] VCCIO[44] AG17
J28 VCC[48] VCCIO[45] AG20
J29 VCC[49] VCCIO[46] AG21
J32 VCC[50] VCCIO[47] AJ14
J34 VCC[51] VCCIO[48] AJ15
J35 VCC[52] VCCIO[49]
J37 VCC[53]
J38 VCC[54] +1.05VS_VCCP
J40 VCC[55]
J42 VCC[56]
K26 VCC[57] W16
K27 VCC[58] VCCIO50 W17
K29 VCC[59] VCCIO51
K32 VCC[60]
K34 VCC[61]
K35 VCC[62]
K37 VCC[63]
K39 VCC[64] 1mA
K42 VCC[66] BC22
L25 VCC[67] VCCIO_SEL
L28 VCC[68]
3 L33 VCC[69] 3
L36 VCC[70] +1.05VS_VCCP
L40 VCC[71]
N26 VCC[72] +1.05VS_VCCP +1.05VS_VCCP
N30 VCC[73] AM25
QUIET
RAILS

N34 VCC[74] VCCPQE[1] AN22


N38 VCC[75] VCCPQE[2]
VCC[76] 1
CC71
1

1
1U_0402_6.3V6K
RC91 RC89
2 130_0402_5% 75_0402_5%
2

2
A44 H_CPU_SVIDALRT# 1 2
VIDALERT# B43 VR_SVID_ALRT# 42
RC90 43_0402_1% 42
VIDSCLK VR_SVID_CLK
SVID

C44
VIDSOUT VR_SVID_DAT 42
+CPU_CORE Pull high resistor on VR side
2

RC93
100_0402_1%
1

F43
VCC_SENSE VCCSENSE 42
SENSE LINES

G43
VSS_SENSE VSSSENSE 42
1

VCCIO_SENSE
VCCIO_SENSE 40
RC97
1

RC98 100_0402_1%
AN16 10_0402_1%
4 VCCIO_SENSE AN17 4
2

VSS_SENSE_VCCIO

+1.05VS_VCCP Close to CPU


2

IVY-BRIDGE_BGA1023 <BOM>
1

CPU@ RC96
10_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

Close to CPU Ivy Bridge_POWER-1


2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 8 of 46
A B C D E
A B C D E

http://laptopblue.vn/
Intel DDR Vref M3
+GFX_CORE UC1G POWER +V_SM_VREF should
+1.5V_CPU

29A have 20 mil trace width RC120 1K_0402_0.5%


1 2
AY43 +V_SM_VREF BSS138_NL_SOT23-3
AA46 SM_VREF CC65 1 2 QC7

VREF
VAXG[1]

0.1U_0402_10V7K
AB47 3 1

D
1 RC109 1K_0402_0.5% +VREF_DQA_M3 +VREF_DQA
AB50 VAXG[2] BE7
VAXG[3] SA_DIMM_VREFDQ +VREF_DQA_M3
AB51 BG7
1 VAXG[4] SB_DIMM_VREFDQ +VREF_DQB_M3 1
AB52 11/28

G
2
AB53 VAXG[5] 2 Change CC53 100u to 47U 0805 (SE00000PL00)
AB55 VAXG[6] Add CC50 (SE00000PL00)
AB56 VAXG[7]
AB58 VAXG[8] 5A 7,17
DRAMRST_CNTRL_PCH
AB59 VAXG[9]
VAXG[10]

2
G
AC61
AD47 VAXG[11] +1.5V_CPU
AD48 VAXG[12] 3 1
VAXG[13] +VREF_DQB_M3 +VREF_DQB
AD50 Place TOP IN BGA

D
AD51 VAXG[14] AJ28 CC57 CC51 CC52 CC55 CC54 CC56 CC53 CC50 QC8
VAXG[15] VDDQ[1]

- 1.5V RAILS
BSS138_NL_SOT23-3

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

47U_0805_6.3V6M

47U_0805_6.3V6M
AD52 AJ33
AD53 VAXG[16] VDDQ[2] AJ36
VAXG[17] VDDQ[3] 2 2 2 2 2 2

1
AD55 AJ40
AD56 VAXG[18] VDDQ[4] AL30
AD58 VAXG[19] VDDQ[5] AL34 @ @

2
AD59 VAXG[20] VDDQ[6] AL38 1 1 1 1 1 1
AE46 VAXG[21] VDDQ[7] AL42
N45 VAXG[22] VDDQ[8] AM33
P47 VAXG[23] VDDQ[9] AM36
P48 VAXG[24] VDDQ[10] AM40
+1.5V_CPU Decoupling:
P50 VAXG[25] VDDQ[11] AN30 2X 47U(MLCC), 6X 10U, 8X 1U
P51 VAXG[26] VDDQ[12] AN34
P52 VAXG[27] VDDQ[13] AN38
P53 VAXG[28] VDDQ[14] AR26 Place BOT OUT BGA

DDR3
P55 VAXG[29] VDDQ[15] AR28

GRAPHICS
P56 VAXG[30] VDDQ[16] AR30
P61 VAXG[31] VDDQ[17] AR32 CC82 CC81 CC80 CC79 CC78 CC87 CC86 CC85
VAXG[32] VDDQ[18]

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
T48 AR34 1 1 1 1 1 1 1 1
T58 VAXG[33] VDDQ[19] AR36
T59 VAXG[34] VDDQ[20] AR40
T61 VAXG[35] VDDQ[21] AV41
2 U46 VAXG[36] VDDQ[22] AW26 2 2 2 2 2 2 2 2 2
V47 VAXG[37] VDDQ[23] BA40
V48 VAXG[38] VDDQ[24] BB28
V50 VAXG[39] VDDQ[25] BG33
V51 VAXG[40] VDDQ[26]
V52 VAXG[41]
V53 VAXG[42]
V55 VAXG[43]
V56 VAXG[44]
V58 VAXG[45]
V59 VAXG[46]
W50 VAXG[47] 1mA
W51 VAXG[48]
W52 VAXG[49]
W53 VAXG[50]
W55 VAXG[51]
+GFX_CORE W56 VAXG[52]
W61 VAXG[53]
Y48 VAXG[54]
VAXG[55] VCCSA_VID0 VCCSA_VID1 +VCCSA
Y61
VAXG[56]
1

RC105 0 0 0.90 V
100_0402_1%
+1.5V_CPU
For Sandy Bridge
Close to CPU 0 1 0.80 V
2

QUIET RAILS

AM28
SENSE
LINES

VCC_AXG_SENSE F45 VCCDQ[1] AN26


VCC_AXG_SENSE 42 VAXG_SENSE VCCDQ[2]
VSS_AXG_SENSE G45 1 1 0 0.725 V
VSS_AXG_SENSE 42 VSSAXG_SENSE
RC106 CC72
1 2 1U_0402_6.3V6K
VCCPLL Decoupling: 100_0402_1%
2
1 1 0.675 V
3 1X 330U (6m ohm), 1X 10U, 2x1U 1.2A
3
1.8V RAIL

02/20 change RC119 to short pad


1 Rshort@ 2 +1.8VS_VCCPLL BB3
+1.8VS VCCPLL[1]
RC119 0_0805_5% CC60 BC1
VCCPLL[2]
1U_0402_6.3V6K

Reserve for power consumption 1 1 BC4


CC59 VCCPLL[3]
Remove on PVT phase 02/20 Delete CC61 +1.5V_CPU +1.5V
10U_0603_6.3V6M
2 2 BC43
VDDQ_SENSE BA43 CC46 1 2@ 0.1U_0402_10V7K
VSS_SENSE_VDDQ
SENSE LINES

+1.5V_CPU +1.5VS
+VCCSA L17 6A CC47 1 2@ 0.1U_0402_10V7K JP@ PJ1
L21 VCCSA[1] 2 1
Place TOP IN BGA VCCSA[2] 2 1
N16 CC48 1 2@ 0.1U_0402_10V7K
CC44 CC42 CC41 CC43 CC40 N20 VCCSA[3] JUMP_43X39
VCCSA[4] +1.5V
47U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

47U_0805_6.3V6M

N22 CC45 1 2@ 0.1U_0402_10V7K


SA RAIL

P17 VCCSA[5]
2 2 2 VCCSA[6]
Vgs=10V,Id=14.5A,Rds=6mohm QC4
1

P20 U10 1 8
R16 VCCSA[7] VCCSA_SENSE 2 S D 7
VCCSA[8] S D

2
@ @ R18 1 3 6 02/20 Delete CC83
2

1 1 1 R21 VCCSA[9] RC203 CC68 4 S D 5


U15 VCCSA[10] 470_0805_5% @ 10U_0603_6.3V6M G D
VCCSA VID

V16 VCCSA[11] FDS6676AS_SO8 RC204


V17 VCCSA[12] D48 H_VCCSA_VID0 2013/02/06 change QC5,QH3,QH4,QW1, 2 RUN_ON_CPU1.5VS3 1 2
H_VCCSA_VID0 41 B+

3 1
VCCSA[13] VCCSA_VID[0]
lines

Place BOT OUT BGA V18 D49 H_VCCSA_VID1 Q6 ,QA1 QR1 Q53 from SB00000EO10 to 220K_0402_5%
V21 VCCSA[14] VCCSA_VID[1] H_VCCSA_VID1 41 SB00000DH00 DVT 2nd source for X1 code issue
VCCSA[15]

6
W20 Please kindly check whether QC5B 1
CC77 CC76 CC75 CC74 CC73 VCCSA[16] CC69 RC205 QC5A
there is pull-down resister
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 in PWR-side or HW-side SUSP 5 0.1U_0402_25V6 820K_0402_5%


2 SUSP
2 SUSP 34
2N7002DW-T/R7_SOT363-6

2
IVY-BRIDGE_BGA1023 <BOM> 2N7002DW-T/R7_SOT363-6

1
4 2 2 2 2 2 CPU@ 4

+VCCSA Decoupling:
2X 47U (MLCC), 3X 10U, 5X 1U
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
11/28 Change CC44 100u to 0805
size (SE00000PL00), Add CC40 (SE00000PL00)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_POWER-2
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 9 of 46
A B C D E
A B C D E

http://laptopblue.vn/
UC1H
UC1I
CFG Straps for Processor
UC1E (CFG[17:0] internal pull high 5~15K to VCCIO)
A13 AM38 BG17 M4
A17 VSS[1] VSS[91] AM4 BG21 VSS[181] VSS[250] M58 CFG2
A21 VSS[2] VSS[92] AM42 BG24 VSS[182] VSS[251] M6 CFG0 B50 N59
VSS[3] VSS[93] VSS[183] VSS[252] CFG[0] BCLK_ITP

1
A25 AM45 BG28 N1 TP@ T89 PAD C51 N58
A28 VSS[4] VSS[94] AM48 BG37 VSS[184] VSS[253] N17 CFG2 B54 CFG[1] BCLK_ITP# RC79
A33 VSS[5] VSS[95] AM58 BG41 VSS[185] VSS[254] N21 D53 CFG[2] 1K_0402_1%
A37 VSS[6] VSS[96] AN1 BG45 VSS[186] VSS[255] N25 CFG4 A51 CFG[3] N42 @
A40 VSS[7] VSS[97] AN21 BG49 VSS[187] VSS[256] N28 CFG5 C53 CFG[4] RSVD30 L42

2
A45 VSS[8] VSS[98] AN25 BG53 VSS[188] VSS[257] N33 CFG6 C55 CFG[5] RSVD31 L45
A49 VSS[9] VSS[99] AN28 BG9 VSS[189] VSS[258] N36 CFG7 H49 CFG[6] RSVD32 L47
1 A53 VSS[10] VSS[100] AN33 C29 VSS[190] VSS[259] N40 A55 CFG[7] RSVD33 1
A9 VSS[11] VSS[101] AN36 C35 VSS[191] VSS[260] N43 H51 CFG[8]
AA1 VSS[12] VSS[102] AN40 C40 VSS[192] VSS[261] N47 K49 CFG[9] M13
VSS[13] VSS[103] VSS[193] VSS[262] CFG[10] RSVD34 PEG Static Lane Reversal - CFG2 is for the 16x
AA13 AN43 D10 N48 K53 M14
AA50 VSS[14] VSS[104] AN47 D14 VSS[194] VSS[263] N51 F53 CFG[11] RSVD35 U14
AA51 VSS[15] VSS[105] AN50 D18 VSS[195] VSS[264] N52 G53 CFG[12] RSVD36 W14
VSS[16] VSS[106] VSS[196] VSS[265] CFG[13] RSVD37 1: Normal Operation; Lane # definition
AA52 AN54 D22 N56 L51 P13
AA53 VSS[17] VSS[107] AP10 D26 VSS[197] VSS[266] N61 F51 CFG[14] RSVD38 matches socket pin map definition
VSS[18] VSS[108] VSS[198] VSS[267] CFG[15] CFG2
AA55 AP51 D29 P14 D52
AA56 VSS[19] VSS[109] AP55 D35 VSS[199] VSS[268] P16 L53 CFG[16] AT49 0:Lane Reversed
AA8
AB16
AB18
VSS[20]
VSS[21]
VSS[22]
VSS[110]
VSS[111]
VSS[112]
AP7
AR13
AR17
D4
D40
D43
VSS[200]
VSS[201]
VSS[202]
VSS[269]
VSS[270]
VSS[271]
P18
P21
P58 H43
CFG[17] RSVD39
RSVD40
K24
* CFG4

RESERVED
AB21 VSS[23]
VSS[24]
VSS[113]
VSS[114]
AR21 D46 VSS[203]
VSS[204] VSS VSS[272]
VSS[273]
P59 K43 VCC_VAL_SENSE
VSS_VAL_SENSE RSVD41
AH2

1
AB48 AR41 D50 P9 AG13
AB61 VSS[25] VSS[115] AR48 D54 VSS[205] VSS[274] R17 RSVD42 AM14 RC82
AC10 VSS[26] VSS[116] AR61 D58 VSS[206] VSS[275] R20 H45 RSVD43 AM15 1K_0402_1%
AC14 VSS[27] VSS[117] AR7 D6 VSS[207] VSS[276] R4 K45 VAXG_VAL_SENSE RSVD44 IEDP@
AC46 VSS[28] VSS[118] AT14 E25 VSS[208] VSS[277] R46 VSSAXG_VAL_SENSE

2
AC6 VSS[29] VSS[119] AT19 E29 VSS[209] VSS[278] T1 N50
VSS[30] VSS[120] VSS[210] VSS[279]
AD17
VSS[31] VSS[121]
AT36 E3
VSS[211] VSS[280]
T47 F48
VCC_DIE_SENSE TheseRSVD45
pins are for solder joint
AD20 AT4 E35 T50
AD4 VSS[32] VSS[122] AT45 E40 VSS[212] VSS[281] T51 TP@ PAD T87
reliability and non-critical to
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
F13
F15
VSS[213]
VSS[214]
VSS[215]
VSS[282]
VSS[283]
VSS[284]
T52
T53
H48
K48 RSVD6
RSVD7
function. For BGA only. Embedded Display Port Presence Strap
AE8 AU1 F19 T55 A4
AF1 VSS[36] VSS[126] AU11 F29 VSS[216] VSS[285] T56 DC_TEST_A4 C4 1 : Disabled; No Physical Display Port
AF17
AF21
AF47
VSS[37]
VSS[38]
VSS[39]
VSS[127]
VSS[128]
VSS[129]
AU28
AU32
AU51
F35
F40
F55
VSS[217]
VSS[218]
VSS[219]
VSS[286]
VSS[287]
VSS[288]
U13
U8
V20
BA19
AV19
AT21
RSVD8
RSVD9
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
D3
D1
A58
DC_TEST_C4_D3
* attached to Embedded Display Port
VSS[40] VSS[130] VSS[220] VSS[289] RSVD10 DC_TEST_A58 CFG4
AF48 AU7 G51 V61 BB21 A59 0 : Enabled; An external Display Port
AF50 VSS[41] VSS[131] AV17 G6 VSS[221] VSS[290] W13 BB19 RSVD11 DC_TEST_A59 C59 DC_TEST_A59_C59
2 AF51 VSS[42] VSS[132] AV21 G61 VSS[222] VSS[291] W15 AY21 RSVD12 DC_TEST_C59 A61 device is connected to the Embedded 2
AF52 VSS[43] VSS[133] AV22 H10 VSS[223] VSS[292] W18 BA22 RSVD13 DC_TEST_A61 C61 DC_TEST_A61_C61 Display Port
AF53 VSS[44] VSS[134] AV34 H14 VSS[224] VSS[293] W21 AY22 RSVD14 DC_TEST_C61 D61
AF55 VSS[45] VSS[135] AV40 H17 VSS[225] VSS[294] W46 AU19 RSVD15 DC_TEST_D61 BD61
AF56 VSS[46] VSS[136] AV48 H21 VSS[226] VSS[295] W8 AU21 RSVD16 DC_TEST_BD61 BE61
AF58 VSS[47] VSS[137] AV55 H4 VSS[227] VSS[296] Y4 BD21 RSVD17 DC_TEST_BE61 BE59 DC_TEST_BE61_BE59
AF59 VSS[48] VSS[138] AW13 H53 VSS[228] VSS[297] Y47 BD22 RSVD18 DC_TEST_BE59 BG61
AG10 VSS[49] VSS[139] AW43 H58 VSS[229] VSS[298] Y58 BD25 RSVD19 DC_TEST_BG61 BG59 DC_TEST_BG61_BG59
AG14 VSS[50] VSS[140] AW61 J1 VSS[230] VSS[299] Y59 BD26 RSVD20 DC_TEST_BG59 BG58
AG18 VSS[51] VSS[141] AW7 J49 VSS[231] VSS[300] G48 BG22 RSVD21 DC_TEST_BG58 BG4
AG47 VSS[52] VSS[142] AY14 J55 VSS[232] VSS[301] BE22 RSVD22 DC_TEST_BG4 BG3
AG52 VSS[53] VSS[143] AY19 K11 VSS[233] BG26 RSVD23 DC_TEST_BG3 BE3 DC_TEST_BG3_BE3
AG61 VSS[54] VSS[144] AY30 K21 VSS[234] BE26 RSVD24 DC_TEST_BE3 BG1
AG7 VSS[55] VSS[145] AY36 K51 VSS[235] BF23 RSVD25 DC_TEST_BG1 BE1 DC_TEST_BG1_BE1
AH4 VSS[56] VSS[146] AY4 K8 VSS[236] A5 BE24 RSVD26 DC_TEST_BE1 BD1
AH58 VSS[57] VSS[147] AY41 L16 VSS[237] VSS_NCTF_1 A57 RSVD27 DC_TEST_BD1
AJ13 VSS[58] VSS[148] AY45 L20 VSS[238] VSS_NCTF_2 BC61 CFG7
AJ16 VSS[59] VSS[149] AY49 L22 VSS[239] VSS_NCTF_3 BD3
VSS[60] VSS[150] VSS[240] VSS_NCTF_4

1
AJ20 AY55 L26 BD59
AJ22 VSS[61] VSS[151] AY58 L30 VSS[241] VSS_NCTF_5 BE4 IVY-BRIDGE_BGA1023 <BOM> RC85
VSS[62] VSS[152] VSS[242]
NCTF

AJ26 AY9 L34 VSS_NCTF_6 BE58 1K_0402_1%


AJ30 VSS[63] VSS[153] BA1 L38 VSS[243] VSS_NCTF_7 BG5 @
VSS[64] VSS[154] VSS[244] VSS_NCTF_8 CPU@
AJ34 BA11 L43 BG57

2
AJ38 VSS[65] VSS[155] BA17 L48 VSS[245] VSS_NCTF_9 C3
AJ42 VSS[66] VSS[156] BA21 L61 VSS[246] VSS_NCTF_10 C58
AJ45 VSS[67] VSS[157] BA26 M11 VSS[247] VSS_NCTF_11 D59
AJ48 VSS[68] VSS[158] BA32 M15 VSS[248] VSS_NCTF_12 E1
AJ7 VSS[69] VSS[159] BA48 VSS[249] VSS_NCTF_13 E61
VSS[70] VSS[160] VSS_NCTF_14 PEG DEFER TRAINING
AK1 BA51
AK52 VSS[71] VSS[161] BB53
AL10 VSS[72] VSS[162] BC13 1: (Default) PEG Train immediately
3
AL13
AL17
AL21
VSS[73]
VSS[74]
VSS[75]
VSS[163]
VSS[164]
VSS[165]
BC5
BC57
BD12
CFG7 * following xxRESETB de assertion 3
IVY-BRIDGE_BGA1023 <BOM>
AL25 VSS[76] VSS[166] BD16
VSS[77] VSS[167] 0: PEG Wait for BIOS for training
AL28 BD19
VSS[78] VSS[168] CPU@
AL33 BD23
AL36 VSS[79] VSS[169] BD27 CFG6
AL40 VSS[80] VSS[170] BD32
AL43 VSS[81] VSS[171] BD36 CFG5
AL47 VSS[82] VSS[172] BD40
VSS[83] VSS[173]

1
AL61 BD44
AM13 VSS[84] VSS[174] BD48 RC83 RC84
AM20 VSS[85] VSS[175] BD52 1K_0402_1% 1K_0402_1%
AM22 VSS[86] VSS[176] BD56 @ @
AM26 VSS[87] VSS[177] BD8

2
AM30 VSS[88] VSS[178] BE5
AM34 VSS[89] VSS[179] BG13
VSS[90] VSS[180]

PCIE Port Bifurcation Straps

IVY-BRIDGE_BGA1023 <BOM> 11: (Default) x16 - Device 1 functions 1 and 2


CPU@
* disabled

CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled;


function 2 disabled

01: Reserved - (Device 1 function 1 disabled;


function 2 enabled)
4 4

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Ivy Bridge_GND/RSVD/CFG
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 10 of 46
A B C D E
5 4 3 2 1

+1.5V

1
JDDR3L
2
+1.5V http://laptopblue.vn/
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS2
VSS1
DQ4
4
6
DDR_A_D4
DDR_A_D5
Standard Type DDR_A_DQS[0..7] 7
DDR_A_D1 7 DQ0 DQ5 8
1 DQ1 VSS3 DDR_A_DQS#[0..7] 7
CD1 9 10 DDR_A_DQS#0
11 VSS4 DQS#0 12 DDR_A_DQS0
DM0 DQS0 DDR_A_D[0..63] 7
0.1U_0402_10V7K

13 14
2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
DQ2 DQ6 DDR_A_MA[0..15] 7
DDR_A_D3 17 18 DDR_A_D7
19 DQ3 DQ7 20
D DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 D
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_DQS1 29 DQS#1 DM1 30
Close to JDDRL.1 31 DQS1 RESET# 32 SM_DRAMRST# 7,12
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15
02/20 Delete CD2, CD15 37 DQ11 DQ15 38
DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3 +1.5V
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DQ26 DQ30

1
DDR_A_D27 69 70 DDR_A_D31
71 DQ27 DQ31 72 RD1
VSS25 VSS26 1K_0402_1%

2
73 74
7 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 7
75 76
VDD1 VDD2 +VREF_DQA
77 78 DDR_A_MA15
C 79 NC1 A15 80 DDR_A_MA14 C
7 DDR_A_BS2 BA2 A14

1
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11 RD2
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 1K_0402_1%
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6

2
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
101 VDD9 VDD10 102
7 DDRA_CLK0 CK0 CK1 DDRA_CLK1 7
103 104
7 DDRA_CLK0# CK0# CK1# DDRA_CLK1# 7
105 106
DDR_A_MA10 107 VDD11 VDD12 108 +1.5V
A10/AP BA1 DDR_A_BS1 7
109 110
7 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 7
111 112
VDD13 VDD14

1
113 114
7 DDR_A_WE# WE# S0# DDRA_SCS0# 7
115 116 RD6
7 DDR_A_CAS# CAS# ODT0 DDRA_ODT0 7
117 118 1K_0402_1%
DDR_A_MA13 119 VDD15 VDD16 120
A13 ODT1 DDRA_ODT1 7
121 122
7

2
DDRA_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CAA
127 NCTEST VREF_CA 128
VSS27 VSS28

1
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37 RD7
133 DQ33 DQ37 134 1K_0402_1%
VSS29 VSS30 1
DDR_A_DQS#4 135 136 CD16
DQS#4 DM4
0.1U_0402_10V7K

DDR_A_DQS4 137 138

2
139 DQS4 VSS31 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2
B DDR_A_D35 143 DQ34 DQ39 144 B
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45 02/20 Delete CD2, CD15
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 close to JDDRL.126 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170 +1.5V +1.5V +0.75VS
DDR_A_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55 CD8 1 2 10U_0603_6.3V6M CD20 1 2 0.1U_0402_10V7K CD24 2 1 1U_0402_6.3V6K
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60 CD9 1 2 10U_0603_6.3V6M CD17 1 2 0.1U_0402_10V7K CD21 2 1 1U_0402_6.3V6K
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184 CD10 1 2 10U_0603_6.3V6M CD18 1 2 0.1U_0402_10V7K
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7 CD11 1 2 10U_0603_6.3V6M CD19 1 2 0.1U_0402_10V7K
189 DM7 DQS7 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62 CD12 1 2 10U_0603_6.3V6M
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196 CD13 1 2 10U_0603_6.3V6M
197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA PM_SMBDATA 12,17,26,33
201 202
SA1 SCL PM_SMBCLK 12,17,26,33
1 203 204
+0.75VS VTT1 VTT2 +0.75VS
A 205 206 A
CD26 G1 G2
2 LCN_DAN06-K4406-0102
Conn@

0.1U_0402_10V7K

SPD setting (SA0, SA1) Security Classification Compal Secret Data Compal Electronics, Inc.
PU/PD by Channel A/B Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
->Channel A 00 DDRIII-SODIMM0
->Channel B 01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 11 of 46
5 4 3 2 1
A B C D E

+1.5V
JDDR3H
+1.5V
http://laptopblue.vn/
DDR3 SO-DIMM B
1 2
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS2
VSS1
DQ4
4
6
DDR_B_D4
DDR_B_D5
Standard Type
DDR_B_D1 7 DQ0 DQ5 8
9 DQ1 VSS3 10 DDR_B_DQS#0
11 VSS4 DQS#0 12 DDR_B_DQS0
CD27 13 DM0 DQS0 14
1 VSS5 VSS6
DDR_B_D2 15 16 DDR_B_D6
DQ2 DQ6 DDR_B_DQS#[0..7]7
DDR_B_D3 17 18 DDR_B_D7
DQ3 DQ7

0.1U_0402_10V7K
1 19 20 1
02/20 Delete CD28, CD46 2 DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12 DDR_B_DQS[0..7]7
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
DQ9 DQ13 DDR_B_D[0..63] 7
25 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DQS#1 DM1 DDR_B_MA[0..15] 7
DDR_B_DQS1 29 30
DQS1 RESET# SM_DRAMRST# 7,11
31 32
DDR_B_D10 33 VSS11 VSS12 34 DDR_B_D14
DDR_B_D11 35 DQ10 DQ14 36 DDR_B_D15
Close to JDDRH.1 37 DQ11 DQ15 38 +1.5V
DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
DQ17 DQ21

1
43 44
DDR_B_DQS#2 45 VSS15 VSS16 46 RD10
DDR_B_DQS2 47 DQS#2 DM2 48 1K_0402_1%
49 DQS2 VSS17 50 DDR_B_D22
DDR_B_D18 51 VSS18 DQ22 52 DDR_B_D23

2
DDR_B_D19 53 DQ18 DQ23 54 11/28 Move RD10, RD11 to page 12
55 DQ19 VSS19 56 DDR_B_D28
VSS20 DQ28 +VREF_DQB
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 59 DQ24 DQ29 60
DQ25 VSS21

1
61 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3 RD11
65 DM3 DQS3 66 1K_0402_1%
DDR_B_D26 67 VSS23 VSS24 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31

2
71 DQ27 DQ31 72
VSS25 VSS26

73 74
7 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 7
75 76
2 77 VDD1 VDD2 78 DDR_B_MA15 2
79 NC1 A15 80 DDR_B_MA14
7 DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
101 VDD9 VDD10 102
7 DDRB_CLK0 CK0 CK1 DDRB_CLK1 7
103 104
7 DDRB_CLK0# CK0# CK1# DDRB_CLK1# 7
105 106
DDR_B_MA10 107 VDD11 VDD12 108 +1.5V
A10/AP BA1 DDR_B_BS1 7
109 110
7 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 7
111 112
VDD13 VDD14

1
113 114
7 DDR_B_WE# WE# S0# DDRB_SCS0# 7
115 116 RD12
7 DDR_B_CAS# CAS# ODT0 DDRB_ODT0 7
117 118 1K_0402_1%
DDR_B_MA13 119 VDD15 VDD16 120
A13 ODT1 DDRB_ODT1 7
121 122
7

2
DDRB_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CAB
127 NCTEST VREF_CA 128
VSS27 VSS28

1
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37 02/20 Delete CD28, CD46 RD13
133 DQ33 DQ37 134 CD47 1K_0402_1%
VSS29 VSS30 1
0.1U_0402_10V7K

DDR_B_DQS#4 135 136


DDR_B_DQS4 137 DQS#4 DM4 138

2
139 DQS4 VSS31 140 DDR_B_D38
3 DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 2 3
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D42 157 VSS37 VSS38 158 DDR_B_D46
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
Close to JDDRH.126 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
161 DQ43 DQ47 162
DDR_B_D48 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168 +1.5V +1.5V +0.75VS
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172 CD31 1 2 47U_0805_6.3V6M
173 DQS6 VSS43 174 DDR_B_D54 CD33 1 2 0.1U_0402_10V7K CD45 2 1 1U_0402_6.3V6K
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55 CD41 1 2 10U_0603_6.3V6M
DDR_B_D51 177 DQ50 DQ55 178 CD29 1 2 0.1U_0402_10V7K CD42 2 1 1U_0402_6.3V6K
179 DQ51 VSS45 180 DDR_B_D60 CD36 1 2 10U_0603_6.3V6M
DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61 CD30 1 2 0.1U_0402_10V7K
DDR_B_D57 183 DQ56 DQ61 184 CD37 1 2 10U_0603_6.3V6M
185 DQ57 VSS47 186 DDR_B_DQS#7 CD32 1 2 0.1U_0402_10V7K
187 VSS48 DQS#7 188 DDR_B_DQS7 CD38 1 2 10U_0603_6.3V6M
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D62 CD39 1 2 10U_0603_6.3V6M
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196 CD40 1 2 10U_0603_6.3V6M
197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA PM_SMBDATA 11,17,26,33
2 1 201 202
SA1 SCL PM_SMBCLK 11,17,26,33
1 RD15 10K_0402_5% +0.75VS 203 204
4 VTT1 VTT2 +0.75VS 4
11/28 Change CD31 47U 1206
205 206 to 0805 size (SE00000PL00)
CD49 G1 G2
2 LCN_DAN06-K4806-0102
0.1U_0402_10V7K Conn@

SPD setting (SA0, SA1) Security Classification Compal Secret Data Compal Electronics, Inc.
PU/PD by Channel A/B Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title
->Channel A 00 DDRIII-SODIMM1
->Channel B 01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 12 of 46
A B C D E
A B C D E

For eDP Panel


http://laptopblue.vn/
LCD POWER CIRCUIT
Reserve for power consumption
CAM_EMI@ Need check eDP&LVDS both 3V power rail.
USB20_N11_R 1 2 USB20_N11 Remove on PVT phase
1 2 20
+3VS
IEDP@ USB20_P11_R 4 3 USB20_P11
4 3 20
C890 1 20.1U_0402_10V7K LVDS_EDID_CLK 02/20 Change R106 to shortpad +LCD_VDD
6 H_EDP_AUXP
IEDP@
W=60mils W=60mils
L55 WCM-2012-900T_0805 U16
C891 1 20.1U_0402_10V7K LVDS_EDID_DATA 1.5A 1 +LCD_VDD_OUT 1 Rshort@ 2 I rush=1.5A
6 H_EDP_AUXN VOUT
IEDP@ Reserve for EMI request 5 R106 0_0805_5%
1 C912 1 20.1U_0402_10V7K LVDS_TXOUT0+ VIN 1
H_EDP_TXP0 6
IEDP@ 2
C913 1 20.1U_0402_10V7K LVDS_TXOUT0- +LCD_VDD_SS 4 GND
H_EDP_TXN0 6 SS
IEDP@ 2013/02/06 Add R266 ,
C914 1 20.1U_0402_10V7K LVDS_TXOUT1+ @TOUCH_EMI@ R267 Co-lay L57 3
H_EDP_TXP1 6 EN
IEDP@ 1 2

1
C915 1 20.1U_0402_10V7K LVDS_TXOUT1- R267 0_0402_5% APL3512ABI-TRG_SOT23-5
H_EDP_TXN1 6
C7
TOUCH_EMI@ 0.015u_0402_16V_X7R

2
USB20_P8_R 1 2 USB20_P8
1 2 20
19 LCD_ENVDD

2
USB20_N8_R 4 3 USB20_N8
4 3 20
R112
L57 WCM-2012-900T_0805 100K_0402_5%
02/20 Change C7 to SE076153K80 (15nF)
1 2 for LCD sequence tuning

1
R266 0_0402_5%
@TOUCH_EMI@

Reserve for EMI request

For LVDS 1ch Panel LVDS colay eDP cable


1 LVDS@ 2 LVDS_TXOUT0+
Pin define will be change after ME ready
LCD_TXOUT0+ 19
R262 0_0402_5%
2 1 LVDS@ 2 LVDS_TXOUT0- 2
LCD_TXOUT0- 19
R263 0_0402_5%
1 LVDS@ 2 LVDS_TXOUT1+ +5VS
LCD_TXOUT1+ 19
R265 0_0402_5%
1 LVDS@ 2 LVDS_TXOUT1- JLVDS
LCD_TXOUT1- 19
R264 0_0402_5% 1 +5VS_LVDS_TOUCH 1 Rshort@ 2 20mils
LCD_TXOUT2+ 19 LCD_TXOUT2+ pin1-4 Touch function for panel 1 2 USB20_N8_R R390 0_0603_5%
2 3 USB20_P8_R
LCD_TXOUT2- 3 4 BKOFF#
LCD_TXOUT2- 19 4 5 INT_MIC_DATA
LCD_TXCLK+ 5 6 INT_MIC_CLK INT_MIC_DATA 30
LCD_TXCLK+ 19 pin5-10 For Webcam with single or dual MIC 6 7 INT_MIC_CLK 30
LCD_TXCLK- 7 8 USB20_P11_R +3VS
LCD_TXCLK- 19 8 9 USB20_N11_R
1 LVDS@ 2 LVDS_EDID_CLK 9 10 +3VS_LVDS_CAM 1 Rshort@ 2
19 LCD_EDID_CLK 10 20mils
R300 0_0402_5% 11 +LCD_VDD R389 0_0603_5%
1 LVDS@ 2 LVDS_EDID_DATA 11 12 +3VS
19 LCD_EDID_DATA pin11-30 For LVDS or EDP panel 12 +LCD_VDD Irush=1.5A 60mils
R299 0_0402_5% 13 +3VS
13 14 LVDS_EDID_CLK
14 15 LVDS_EDID_DATA
15 16 LVDS_TXOUT0-
16 17 LVDS_TXOUT0+
17 18 LVDS_TXOUT1-
18 19 LVDS_TXOUT1+
19 20 LCD_TXOUT2-
20 21 LCD_TXOUT2+
21 22
22 23 LCD_TXCLK-
23 24 LCD_TXCLK+
24 25
25 26 LED_PWM CPU_EDP_HPD 6
26 27 BKOFF#_R
3 27 28 3
28 29
29 30
30 +LCD_INV Irush=1.5A 60mils
31
GND 32
GND 33
GND 34
GND 35
GND B+
Irush=1.5A 60mils
Conn@ +LCD_INV
L2
Reserve for eDP panel potential issue 2 1
FBMA-L11-201209-221LMA30T_0805
+3VS EMI@

IEDP@1 2 IEDP@
5

R103 0_0402_5% U17 LED_PWM 1 2


PCH_PWM 19
1 RB751V40_SC76-2 D17
P

IN1 EC_ENBKL 19,32


BKOFF#_R 1 2 4
D15 RB751V40_SC76-2 O 2
IN2 BKOFF# 32
G

1
LVDS@
1

R131
3

R113 SN74AHC1G08DCKR_SC70-5 47K_0402_5%


10K_0402_5%

2
2

1 2
R147 0_0402_5%
4 LVDS@ 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 13 of 46
A B C D E
A B C D E

http://laptopblue.vn/ CRT CONNECTOR

1 1

UMA_CRT_R 19 L3 1 2 NBQ100505T-800Y_0402 CRT_R_L


CRT_EMI@
UMA_CRT_G 19 L4 1 2 NBQ100505T-800Y_0402 CRT_G_L
CRT_EMI@
UMA_CRT_B 19 L5 1 2 NBQ100505T-800Y_0402 CRT_B_L
CRT_EMI@ T65, T66: for ATE
JCRT
CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@ 6
T65 PAD 11
R138 R139 R140 CRT_R_L 1

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
7

150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1

1
CRT_DDC_DAT 12
C238 C239 C240 C241 C242 C243 CRT_G_L 2
8
2 2 2 2 2 2 HSYNC 13
CRT_B_L 3

2
+HDMI_5V_OUT 9
VSYNC 14 G 16
T66 PAD 4 17
G
10
CRT_DDC_CLK 15
USE HDMI POWER 5
11/28
change BOM structureC238 C239 C240 C-H_13-12201513CP
C241 C242 C243 to CRT@EMI@ Conn@
2 2

02/20 Delete C250 0.1u

CRT@
U49 +HDMI_5V_OUT
+HDMI_5V_OUT 1 8 1 2
VCC_SYNC BYP C15 0.22U_0402_16V7K

+3VS 2 3 CRT_R_L
VCC_VIDEO VIDEO1

2
+3VS 7 4 CRT_G_L R153 R159
VCC_DDC VIDEO2 4.7K_0402_5% 4.7K_0402_5%

19 UMA_CRT_DATA 10 5 CRT_B_L CRT@ CRT@

1
DDC_IN1 VIDEO3

19 UMA_CRT_CLK 11 9 CRT_DDC_DAT
DDC_IN2 DDC_OUT1

3 13 12 CRT_DDC_CLK 3
19 UMA_CRT_VSYNC SYNC_IN1 DDC_OUT2

19 15 14 22_0402_5% VSYNC_R 1 CRT@ 2 R62 VSYNC


UMA_CRT_HSYNC SYNC_IN2 SYNC_OUT1

6 16 22_0402_5% HSYNC_R 1 CRT@ 2 R63 HSYNC


GND SYNC_OUT2

TPD7S019-15DBQR_SSOP16

CRT@
11/29 add 22-ohm (PN: SD028220A80)
on CRT HSYNC/VSYNC trace.

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 14 of 46
A B C D E
A B C D E

http://laptopblue.vn/ OE# A Y

1
RPY1
8 UMA_HDMI_CLK
HDMI POWER CIRCUIT
+3VS L L L
2 7 UMA_HDMI_DATA VIN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m
3 6 HDMI_SCLK L H H
+HDMI_5V_OUT
4 5 HDMI_SDATA Current Limit: TYP=0.8A ; MAX=1A
H X Z
2.2K_0804_8P4R_5%
1 1
+HDMI_5V_OUT
+HDMI_5V_OUT UY2
RY1 1 5
OUT IN +5VS
HDMI_HPD_U 1 2 HDMI_HPD_C
1K_0402_5% 1 2
CY18 GND
2

2
+3VS RY2 CY4 3 4
100K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_10V7K FLG EN

1
UY1 2 AP2151DWG-7_SOT25-5
1
SA00006H000

OE#
P
2 4 HDMI_HPD

1
A Y

G
74AHCT1G125GW_SOT353-5

3
11/28 Update HDMI current limited IC

2
G
from AP230W-7 to AP2151DDWG-7.
BSS138 1N SOT23-3
UMA_HDMI_CLK 3 1 HDMI_SCLK
19 UMA_HDMI_CLK 2 1
S

D
QY1 +3VS
RY3
2
G

2.2K_0402_5%
BSS138 1N SOT23-3
UMA_HDMI_DATA 3 1 HDMI_SDATA HDMI_HPD
19 UMA_HDMI_DATA HDMI_HPD 19,21
S

QY2

2013/02/06 change QY1 QY2


to SB00000PF00 for X1 code
2 2

LY1 EMI@
CY2 1 2 0.1U_0402_16V7K HDMI_TXC- 1 2
19 UMA_HDMI_CLK- 1 2

19 UMA_HDMI_CLK+
CY1 1 2 0.1U_0402_16V7K HDMI_TXC+ 4
4 3
3 HDMI Connector
WCM-2012HS-900T_4P JHDMI
HDMI_HPD_C 19
18 HP_DET
+HDMI_5V_OUT +5V
17
HDMI_SDATA 16 DDC/CEC_GND
LY2 EMI@ HDMI_SCLK 15 SDA
CY5 1 2 0.1U_0402_16V7K HDMI_TXD0- 1 2 14 SCL
19 UMA_HDMI_TX0- 1 2 Reserved
13
HDMI_R_CK- 12 CEC
CY3 1 2 0.1U_0402_16V7K HDMI_TXD0+ 4 3 11 CK-
19 UMA_HDMI_TX0+ 4 3 CK_shield
HDMI_R_CK+ 10
WCM-2012HS-900T_4P HDMI_R_D0- 9 CK+
8 D0-
HDMI_R_D0+ 7 D0_shield
HDMI_R_D1- 6 D0+
5 D1-
HDMI_R_D1+ 4 D1_shield 23
LY3 EMI@ HDMI_R_D2- 3 D1+ GND 22
CY7 1 2 0.1U_0402_16V7K HDMI_TXD1- 1 2 2 D2- GND 21
3 19 UMA_HDMI_TX1- 1 2 D2_shield GND 3
HDMI_R_D2+ 1 20
D2+ GND
CY6 1 2 0.1U_0402_16V7K HDMI_TXD1+ 4 3
19 UMA_HDMI_TX1+ 4 3 Conn@
WCM-2012HS-900T_4P

11/28 Add @ to JHDMI

680 +-5% 8P4R


HDMI_R_D0- 5 4
HDMI_R_D0+ 6 3
LY4 EMI@ HDMI_R_CK- 7 2
CY9 1 2 0.1U_0402_16V7K HDMI_TXD2- 1 2 HDMI_R_CK+ 8 1
19 UMA_HDMI_TX2- 1 2
RPY3
CY8 1 2 0.1U_0402_16V7K HDMI_TXD2+ 4 3
19 UMA_HDMI_TX2+ 4 3
WCM-2012HS-900T_4P
680 +-5% 8P4R
HDMI_R_D1- 5 4
HDMI_R_D1+ 6 3
12/04 SWAP RPY4 netname HDMI_R_D2- 7 2
HDMI_R_D2+ 8 1

RPY4

1
QY4 D
ZZZ HDMI45@ 2
+5VS
HDMI Royalty G
10/18 Modify the BOM structure @ to HDMI45@ ,

RO0000003HM change Location HDMI to ZZZ. S

3
2N7002KW_SOT323-3
4 4
HDMI W/Logo + HDCP

HDMI W/O Logo: RO0000001HM


HDMI W/Logo: RO0000002HM
HDMI W/Logo + HDCP: RO0000003HM Security Classification Compal Secret Data Compal Electronics, Inc.
please manually load Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

this virtual material to 45@ BOM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn.
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 15 of 46
A B C D E
5 4 3 2 1

+RTCVCC
CMOS Setting, near DDR Door
RH23 1
20K_0402_5%
2 PCH_RTCRST#

CH4 1
JCMOS SP@ 26
1 2

2
PCH_RTCX1_R
1
http://laptopblue.vn/
RH26 GCLK@

0_0402_5%
2 PCH_RTCX1
UH1A

1U_0402_6.3V6K 2 1 NOGCLK@ PCH_RTCX1 A20 INT.PH 20K C38 LPC_AD0


RTCX1 FWH0 / LAD0 LPC_AD0 32
Placement near to YH1 CH2 15P_0402_50V8J INT.PH 20K A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 32

LPC
PCH_RTCX2 C20 INT.PH 20K B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 32

1
10M_0402_5%

NOGCLK@
iME Setting. NOGCLK@ INT.PH 20K C37 LPC_AD3
FWH3 / LAD3 LPC_AD3 32
JME SP@ PCH_RTCRST# D20
RTCRST#

RH2
RH24 1 2 PCH_SRTCRST# 1 2 YH1 D36 LPC_FRAME#
PCH_SRTCRST# G22 FWH4 / LFRAME# LPC_FRAME# 32
20K_0402_5% 32.768KHZ_12.5P_1TJF125DP1A000D

1
CH5 1 2 SRTCRST# E36
INT.PH 20K

2
2 1 NOGCLK@ SM_INTRUDER# K22 LDRQ0# K36

RTC
D
1U_0402_6.3V6K
INTRUDER# INT.PH 20K
LDRQ1# / GPIO23 D
CH3 15P_0402_50V8J
PCH_INTVRMEN C17 V5 SERIRQ
INTVRMEN SERIRQ SERIRQ 32

Integrated SUS 1.05V VRM Enable AM3 SATA_PRX_C_DTX_N0


SATA0RXN 25
SATA_PRX_C_DTX_N0
High - Enable Internal VRs AZ_BITCLK N34 AM1 SATA_PRX_C_DTX_P0
HDA_BCLK SATA0RXP 25
SATA_PRX_C_DTX_P0
PCH_INTVRMEN AP7 SATA_PTX_DRX_N0

SATA 6G
(must be always pulled high) AZ_SYNC L34 INT.PD 20K SATA0TXN AP5 SATA_PTX_DRX_P0
25
SATA_PTX_DRX_N0
25
HDD
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0
PCH_SPKR T10 INT.PD 20K AM10
30 PCH_SPKR SPKR SATA1RXN AM8
+RTCVCC AZ_RST# K34 SATA1RXP AP11
HDA_RST# SATA1TXN AP10
RH12 1 2 SM_INTRUDER# SATA1TXP
1M_0402_5% AZ_SDIN0_HD E34 INT.PD 20K AD7 SATA_PRX_C_DTX_N2
30 AZ_SDIN0_HD HDA_SDIN0 SATA2RXN 25
SATA_PRX_C_DTX_N2
RH33 1 2 PCH_INTVRMEN AD5 SATA_PRX_C_DTX_P2
25
G34 SATA2RXP AH5 SATA_PTX_DRX_N2 SATA_PRX_C_DTX_P2
+3VS
330K_0402_5% PCH_SPKR HDA_SDIN1 INT.PD 20K SATA2TXN 25
SATA_PTX_DRX_N2 ODD
AH4 SATA_PTX_DRX_P2
High = Enabled "No Reboot Mode" C34 SATA2TXP 25
SATA_PTX_DRX_P2
@
*
Low = Disabled (Default) HDA_SDIN2 INT.PD 20K
1 2 PCH_SPKR AB8

IHDA
A34 SATA3RXN AB10
RH36 1K_0402_5%
HDA_SDIN3 INT.PD 20K SATA3RXP AF3
SATA3TXN AF1
1 Rshort@ 2 AZ_SDOUT A36 SATA3TXP
32 PWRME_CTRL HDA_SDO INT.PD 20K
RH25 0_0402_5% Y7

SATA
SATA4RXN Y5 RPH1 +3VS
+RTCBATT SATA4RXP
C36 AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN AD1 SERIRQ 1 8
SATA4TXP
1

Change Net name due to N32 PCH_GPIO21 2 7


HDA_DOCK_RST# / GPIO13 Y3 PCH_GPIO19 3 6
this function is high SATA5RXN
DH1 Y1 SATA_LED# 4 5
+RTCVCC BAS40-04_SOT23-3
active SATA5RXP AB3
C PCH_JTAG_TCK J3 SATA5TXN AB1 C
JTAG_TCKINT.PD 20K
T70 PAD 10K_0804_8P4R_5%
SATA5TXP
3

PCH_JTAG_TMS H7 Y11
+3VL T67 PAD JTAG_TMSINT.PH 20K SATAICOMPO

JTAG
1
PCH_JTAG_TDI K5 Y10 SATAICOMP 1 2
JTAG_TDI INT.PH 20K
CH8 T68 PAD +1.05VS_PCH
SATAICOMPI RH43 37.4_0402_1%
0.1U_0402_10V7K PCH_JTAG_TDO H1
2 T69 PAD JTAG_TDO AB12
SATA3RCOMPO
AB13 SATA3_COMP 1 2
SATA3COMPI +1.05VS_PCH
RH48 49.9_0402_1%

RPH2 PCH_SPICLK T3 AH1 RBIAS_SATA3 1 2


AZ_BITCLK_HD 1 8 AZ_BITCLK SPI_CLK SATA3RBIAS RH41 750_0402_1%
30 AZ_BITCLK_HD 2 7 AZ_SYNC_R PCH_SPICS0# Y14
30 AZ_SYNC_HD SPI_CS0#
3 6 AZ_RST#
30 AZ_RST_HD# 4 5 AZ_SDOUT PCH_SPICS1# T1
30 AZ_SDOUT_HD SPI_CS1#

SPI
P3 SATA_LED#
33_8P4R_5% SATALED#
PCH_SPIDI V4 V14 PCH_GPIO21
SPI_MOSI INT.PD 20K SATA0GP / GPIO21
PCH_SPIDO U3 P1 PCH_GPIO19
SPI_MISO INT.PH 20K
HDA_SDO SATA1GP / GPIO19 PCH_GPIO19 20(PH)
INT.PH 20K
BOOT BIOS Strap Bit 0
ME debug mode, PANTHER-POINT_FCBGA989
HM76R3@
this signal has a weak internal pull down
*Low = Disable (default)
High = Enable (flash descriptor security overide)
11/28 Change UH3 from socket to IC,
B
HDA_SYNC modify the footprint 11/29 change UH4 2M ROM circuit to "@".
11/29 change RH267 change
from shortpad to 0-ohm
B

*This signal has a weak internal pull


H=>On Die PLL is supplied by 1.5V
down +3VALW_PCH
10/19A Change RH66 to short pad
L=>On Die PLL is supplied by 1.8V SPI ROM for BIOS & ME (4MByte ) SPI ROM for Win8 (2MByte )
Need to pull high for Chief River Mobile platform 02/20 Delete CH100 0.1U
UH4 @
+3VALW_PCH RH269 PCH_SPICS1# 1 8
PCH_SPIDO 1 @ 2 PCH_SPI1_DO 2 CS# VCC 7 RH267 0_0402_5%
+3VALW_PCH 0_0402_5% 3 SO HOLD# 6 PCH_SPI1_CLK 1 @ 2 PCH_SPICLK
+3VALW_PCH WP# SCLK
02/20 Delete CH6 0.1U 4 5 PCH_SPI1_DI 1 2 PCH_SPIDI
+5VS UH3 10/18B change from +3vs to +3VALW_PCH GND SI RH271 @ 0_0402_5%
2

PCH_SPICS0# 1 8 MX25L1606EM2I-12G_SO8
RH55 PCH_SPIDO 1 Rshort@ 2 PCH_SPI0_DO 2 CS# VCC 7 RH66 0_0402_5%
RH68 3 DO HOLD# 6 PCH_SPI0_CLK 1 Rshort@ 2 PCH_SPICLK
1K_0402_5% +3VALW_PCH WP# CLK
2
G

0_0402_5% 4 5 PCH_SPI0_DI 1 Rshort@ 2 PCH_SPIDI 10/19A Change RH267 to short pad


QH1 GND DI RH67 0_0402_5%
1

AZ_SYNC_R 3 1 AZ_SYNC 02/20 change RH67, 32M EN25Q32B-104HIP SOP 8P


RH68 to short pad 10/19A Remove RH65, CH7 10/19A Remove RH69, CH21
S

4MB ROM P/N: 2MB ROM P/N:


( )
2

2013/02/06 change UH3 from SA00003K800


RH56
1M_0402_5%
BSS138_NL_SOT23-3 EOL to SA00004LI00 for X1 code
SA00003K800 SA000041N00
SA00004LI00 SA00003FO10
1

Socket: SP07000F500/SP07000H900
Please place UH3 & UH4 close to UH1 PCH,
please place RH66, RH67, RH68 near UH3
A
Please place RH267 near RH66, Please place RH271 near RH67, A
Please place RH269 near RH68.
RPH9
1 8 PCH_SPI0_DO
32 EC_SDIO 2 7 PCH_SPICS0#
32 EC_CS0# 3 6 PCH_SPI0_CLK
32 EC_SCK 4 5 PCH_SPI0_DI
32 EC_SDI
33_8P4R_5% Security Classification Compal Secret Data Compal Electronics, Inc.
885@ Issued Date 2012/04/19 2015/04/19 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_HDA/JTAG/SATA/SPI/LPC
Reserve for NPCE885N EC Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 16 of 46
5 4 3 2 1
5 4 3 2 1

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UH1B
+3VS
PCIE_PRX_C_LANTX_N1 BG34 +3VALW_PCH RH102 4.7K_0402_5%
27
PCIE_PRX_C_LANTX_N1 PERN1

5
PCIE_PRX_C_LANTX_P1 BJ34 E12 PCH_SMBALERT# QH3B RH103 4.7K_0402_5%
27
PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11 RPH5
LAN PCIE_PTX_C_LANRX_N1 CH13 2 1 0.1U_0402_10V7K
27 PCIE_PTX_LANRX_N1 AV32 (PH)
CH11 2 1 0.1U_0402_10V7K PCIE_PTX_LANRX_P1 AU32 PETN1 H14 PCH_SMBCLK 5 4 PCH_SMBDATA 3 4
PCIE_PTX_C_LANRX_P1 27 PETP1 SMBCLK PM_SMBDATA 11,12,26,33
6 3 PCH_SMBCLK

2
PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA 7 2 PCH_SMLDATA1 QH3A 2N7002DW-T/R7_SOT363-6
26
PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34 8 1 PCH_SMLCLK1
26
PCIE_PRX_WLANTX_P2 PERP2
WLAN PCIE_PTX_C_WLANRX_N2 CH14 2 1 0.1U_0402_10V7K
26 PCIE_PTX_WLANRX_N2 BB32 6 1
11,12,26,33
PETN2 PM_SMBCLK
PCIE_PTX_C_WLANRX_P2 CH17 2 1 0.1U_0402_10V7K
26
PCIE_PTX_WLANRX_P2 AY32 2.2K_0804_8P4R_5%
PETP2 A12

SMBUS
DRAMRST_CNTRL_PCH 2N7002DW-T/R7_SOT363-6
SML0ALERT# / GPIO60 7,9
DRAMRST_CNTRL_PCH
BG36
BJ36 PERN3 C8 PCH_SMLCLK0
PERP3 SML0CLK +3VS

5
D AV34 QH4B D
AU34 PETN3 G12 PCH_SMLDATA0
PETP3 SML0DATA 3 4
+3VS EC_SMB_DA2 25,32
BF36
PERN4

2
BE36 QH4A 2N7002DW-T/R7_SOT363-6
AY34 PERP4 C13 LAN_EN
PETN4 SML1ALERT# / PCHHOT# / GPIO74 LAN_EN 27
RH1041 2 10K_0402_5% CLKREQ_WLAN# BB34 6 1
25,32
PETP4 E14 PCH_SMLCLK1 EC_SMB_CK2
RH95 1 2 10K_0402_5% CLKREQ_LAN# BG37 SML1CLK / GPIO58

PCI-E*
2N7002DW-T/R7_SOT363-6
BH37 PERN5 M16 PCH_SMLDATA1
AY36 PERP5 SML1DATA / GPIO75
Intel Spec: PETN5
BB36
PCIECLK_RQ0# is suspend well, PETP5 2013/02/06 change QC5,QH3,QH4,QW1,
but we pull high to +3VS BJ38 Q6 ,QA1 QR1 Q53 from SB00000EO10 to
for LAN en/disable function BG38 PERN6 SB00000DH00 DVT 2nd source for X1 code issue
AU36 PERP6 M7 +3VALW_PCH

Controller
AV36 PETN6 CL_CLK1
PETP6 DRAMRST_CNTRL_PCH RH76 1 2 1K_0402_5%
Control Link only for support Intel IAMT.

Link
+3VALW_PCH BG40 T11
RPH10 BJ40 PERN7 CL_DATA1 PCH_SMLCLK0 RH73 2 1 2.2K_0402_5%
AY40 PERP7
8 1 EC_SMI# BB40 PETN7 P10 PCH_SMLDATA0 RH77 2 1 2.2K_0402_5%
EC_SMI# 21,32 PETP7 CL_RST1#
7 2 USB_OC#0
USB_OC#0 20,29,32
6 3 SLP_CHG_CB1 BE38
SLP_CHG_CB1 20,29 PERN8
5 4 SLP_CHG_CB0 SLP_CHG_CB0 BC38
20,29 PERP8
AW38
10K_0804_8P4R_5% AY38 PETN8 +3VALW_PCH
PETP8
M10 PCH_GPIO47 PCH_GPIO47 2 1
CLK_LAN# Y40 PEG_A_CLKRQ# / GPIO47 RH89 10K_0402_5%
CLK_LAN# 27 CLKOUT_PCIE0N
LAN CLK_LAN Y39
CLK_LAN 27 CLKOUT_PCIE0P AB37 9/28 Delete CLK_VGA,
C CLKREQ_LAN# J2 CLKOUT_PEG_A_N AB38 C
change CLK_REQ_VGA#to PCH_GPIO47

CLOCKS
CLKREQ_LAN# 27 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P

CLK_WLAN# AB49 AV22 RPH3


CLK_WLAN# 26 CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI#5
WLAN CLK_WLAN AB47 AU22 PCH_CLK_DMI 1 8
CLK_WLAN 26 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5 PCH_CLK_DMI# 2 7
CLKREQ_WLAN# M1 CLKIN_GND1# 3 6
CLKREQ_WLAN# 26 PCIECLKRQ1# / GPIO18 AM12 CLKIN_GND1 4 5
CLKOUT_DP_N AM13 CLK_CPU_EDP#5
AA48 CLKOUT_DP_P CLK_CPU_EDP 5 120 MHz for eDP
10K_0804_8P4R_5%
AA47 CLKOUT_PCIE2N
CLKOUT_PCIE2P BF18 PCH_CLK_DMI# RPH4
V10 CLKIN_DMI_N BE18 PCH_CLK_DMI CLK_DOT# 1 8
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P CLK_DOT 2 7
CLK_SATA 3 6
Y37 BJ30 CLKIN_GND1# CLK_SATA# 4 5
Y36 CLKOUT_PCIE3N CLKIN_GND1_N BG30 CLKIN_GND1
CLKOUT_PCIE3P CLKIN_GND1_P 10K_0804_8P4R_5%
+3VALW_PCH A8
PCIECLKRQ3# / GPIO25 G24 CLK_DOT# CLK_14M_PCH RH87 1 2 10K_0402_5%
RPH6 CLKIN_DOT_96N E24 CLK_DOT From Clock Gen.
1 8 LVDS_SEL Y43 CLKIN_DOT_96P
2 7 PASSWORD_CLEAR# Y45 CLKOUT_PCIE4N
3 6 PCH_SMBALERT# CLKOUT_PCIE4P AK7 CLK_SATA#
4 5 LAN_EN L12 CLKIN_SATA_N AK5 CLK_SATA @EMI@ @EMI@
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P CLK_PCILOOP 1 2 1 2
10K_0804_8P4R_5% RH70 10_0402_5% CH9 10P_0402_50V8J
V45 K45 CLK_14M_PCH
V46 CLKOUT_PCIE5N REFCLK14IN
CLKOUT_PCIE5P
L14 H45 CLK_PCILOOP
PCIECLKRQ5# / GPIO44 INT. PH 20K CLKIN_PCILOOPBACK CLK_PCILOOP 20
B RH37 B
+3VALW_PCH AB42 V47 PCH_X1 1 2 PCH_X1
CLKOUT_PEG_B_N XTAL25_IN PCH_X1_R 26
Note: place in DDR area AB40 V49 PCH_X2 0_0402_5%
CLKOUT_PEG_B_P XTAL25_OUT GCLK@
PASSWORD_CLEAR# E6
1 LVDS@ 2 PANEL_SEL PEG_B_CLKRQ# / GPIO56
Placement near to YH2
1

RH119 10K_0402_5% JPW Y47 XCLK_RCOMP 1 2


XCLK_RCOMP +1.05VS_VCCDIFFCLKN
SP@ V40 RH115 90.9_0402_1%
V42 CLKOUT_PCIE6N
2

CLKOUT_PCIE6P
LVDS_SEL T13
1 IEDP@ 2 PANEL_SEL PCIECLKRQ6# / GPIO45
INT. PD 20K
RH276 10K_0402_5% V38 K43 CLK_FLEX0
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 T72 PAD +3VS
V37 INT. PD 20K NOGCLK@
FLEX CLOCKS

CLKOUT_PCIE7P F47 CLK_FLEX1 RH117 2 1 1M_0402_5%


CLKOUTFLEX1 / GPIO65 T74 PAD
PANEL_SEL K12 INT. PH 20K INT. PD 20K
PCIECLKRQ7# / GPIO46 H47 CLK_FLEX2 NOGCLK@YH2 25MHZ_20PF_7V25000016
CLKOUTFLEX2 / GPIO66 T73 PAD
AK14 INT. PD 20K
AK13 CLKOUT_ITPXDP_N K49 PCH_GPIO67 1 2 PCH_X1 1 3 PCH_X2
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 RH261 10K_0402_5% 1 3
GND GND
1 1
HM76R3@ PANTHER-POINT_FCBGA989 CH26 CH27
9/28 Change DGPU_PRSNT# to PCH_GPIO67, 2 4
then pull high to +3VS 27P_0402_50V8J 27P_0402_50V8J
NOGCLK@ 2 2 NOGCLK@
LVDS_SEL PANEL_SEL
PCH_GPIO67
LVDS_SEL H L PANEL_SEL H L
PCH_GPIO67 H L
A
Single A
Channel (Default) Dual Channel LVDS EDP
M/B SKU UMA DIS/OPT
Compal common design SW request to
add DGPU_Present on this GPIO67

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_PCI-E/SMBUS/CLK
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 17 of 46
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn/
UH1C

BC24 BJ14
6 DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 6
FDI_CTX_PRX_N0
BE20 AY14
+3VALW_PCH 6 DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 6
FDI_CTX_PRX_N1
BG18 BE14
6 DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 6
FDI_CTX_PRX_N2
BG20 BH13
6 DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 6
FDI_CTX_PRX_N3
RPH7 BC12
FDI_RXN4 6
FDI_CTX_PRX_N4
1 8 PCH_SUSPWRDN#_R BE24 BJ12
6 DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 6
FDI_CTX_PRX_N5
2 7 RI# BC20 BG10
D 6 DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 6
FDI_CTX_PRX_N6 D
3 6 PCH_LOW_BAT# BJ18 BG9
6 DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 6
FDI_CTX_PRX_N7
4 5 EC_SWI# BJ20
6 DMI_CTX_PRX_P3 DMI3RXP BG14
FDI_RXP0 6
FDI_CTX_PRX_P0
10K_0804_8P4R_5% AW24 BB14
6 DMI_PTX_CRX_N0 DMI0TXN FDI_RXP1 6
FDI_CTX_PRX_P1
AW20 BF14
6 DMI_PTX_CRX_N1 DMI1TXN FDI_RXP2 6
FDI_CTX_PRX_P2
BB18 BG13
6 DMI_PTX_CRX_N2 DMI2TXN FDI_RXP3 6
FDI_CTX_PRX_P3
AV18 BE12 RH128 0_0402_5%
6 DMI_PTX_CRX_N3 DMI3TXN FDI_RXP4 6
FDI_CTX_PRX_P4

DMI
FDI
BG12 PCH_DPWROK 1 Rshort@ 2 PCH_RSMRST#
FDI_RXP5 6
FDI_CTX_PRX_P5
2 1 PCH_RSMRST# AY24 BJ10
6 DMI_PTX_CRX_P0 DMI0TXP FDI_RXP6 6
FDI_CTX_PRX_P6
RH163 10K_0402_5% AY20 BH9
6 DMI_PTX_CRX_P1 DMI1TXP FDI_RXP7 6
FDI_CTX_PRX_P7
AY18 Do not support DeepSX state
6 DMI_PTX_CRX_P2 DMI2TXP
AU18
6 DMI_PTX_CRX_P3 DMI3TXP AW16
FDI_INT FDI_INT 6
1 2 DMI_COMP BJ24 AV12
+1.05VS_PCH DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 6
RH126 49.9_0402_1%
RPH17 BG25 BC10
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 6
1 8 PM_PWROK
2 7 PCH_GPIO32 1 2 RBIAS_CPY BH21 AV14
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 6
3 6 PCH_GPIO37 RH127 750_0402_1%
PCH_GPIO37 21 +RTCVCC
4 5 BB10
FDI_LSYNC1 FDI_LSYNC1 6
10K_0804_8P4R_5%
DSWVREN RH150 2 1 330K_0402_5%
Reserve this signal to EC by SW demand A18 DSWVREN
DSWVRMEN
2011/10/18a

System Power Management


10/12 Delete OPTIMUS_EN# pull down 1 @ 2 SUSACK#_R C12 INT.PH 20K E22 PCH_DPWROK DSWVREN must be always pulled high to +RTCVCC
32 SUSACK# SUSACK# DPWROK
RH133 0_0402_5%

C
PM_PWROK XDP_DBRESET# +3VS
1
RH47
2
1K_0402_5%
XDP_DBRESET# K3
SYS_RESET# WAKE#
B9 EC_SWI#
EC_SWI#(PH) 27 * ::
DSWVREN - Internal Deep Sleep 1.05V regulator
H Enable
L Disable C
P12 N3 PCH_GPIO32
2 2 32,42 VGATE SYS_PWROK CLKRUN# / GPIO32
@ESD@ @ESD@
CC26 CC27
PM_PWROK L22 G8 SUS_STAT# T76 PAD
100P_0402_50V8J 100P_0402_50V8J 32 PM_PWROK PWROK SUS_STAT# / GPIO61
1 1
2013/02/06 PVT 32.768 KHz
Reserve CC26 CC27 L10 N14 Follow EC check list demand,
APWROK SUSCLK / GPIO62 CLK_EC 32
but don't implement CLKRUN# this fuction
DRAMPWROK B13 D10 PM_SLP_S5#
5 DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 32
SUSACK#_R 2 @ 1 PCH_SUSPWRDN#_R
RH282 0_0402_5% PCH_RSMRST# C21 H4 PM_SLP_S4#
PCH_RSMRST# 32 RSMRST# SLP_S4# PM_SLP_S4# 32

Stuff R137 if EC does not want to (PH) PCH_SUSPWRDN#_R K16 F4 PM_SLP_S3#


SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 32
1 @ 2
involve in the handshake mechanism 32 PCH_SUSPWRDN#
RH132 0_0402_5%
for the DeepSX state entry and exit PBTN_OUT# E20 G10 PM_SLP_A#
PWRBTN#INT.PH 20K
32 PBTN_OUT# T77 PAD
SLP_A#
INT.PD 20K
1 2 PCH_ACIN H20 G16 PM_SLP_SUS# T78 PAD
+3VALW_PCH ACPRESENT / GPIO31 SLP_SUS#
RH161 330K_0402_5%
DH2
1 2 PCH_LOW_BAT# E10 AP14 H_PM_SYNC
32,37 ACIN BATLOW# / GPIO72 INT.PH 20K PMSYNCH H_PM_SYNC 5
CH751H-40PT_SOD323-2
RI# A10 K14
(PH) RI# SLP_LAN# / GPIO29

PANTHER-POINT_FCBGA989
B Reserve this signal to EC by SW demand HM76R3@ B

2011/10/18a

DH5
PM_PWROK 2 1 PCH_RSMRST#

CH751H-40PT_SOD323-2

DH6
1 2
POK 32,38
CH751H-40PT_SOD323-2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_DMI/FDI/PM
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 18 of 46
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn/ UH1D

13,32 EC_ENBKL J47 INT.PD 50 SDVO_TVCLKINN AP43


EC_ENBKL L_BKLTEN
1 2 EC_ENBKL 13 LCD_ENVDD M45 INT.PD 50 SDVO_TVCLKINP AP45
LCD_ENVDD L_VDD_EN
RH125 100K_0402_5%
PCH_PW M 13 P45 INT.PD 50 SDVO_STALLN AM42
PCH_PW M L_BKLTCTL
INT.PD 50 SDVO_STALLP AM40
13 LCD_EDID_CLK LCD_EDID_CLK T40
K47 L_DDC_CLK AP39
13 LCD_EDID_DATA LCD_EDID_DATA
L_DDC_DATA INT.PD 50 SDVO_INTN
INT.PD 50 AP40
LCTL_CLK T45 SDVO_INTP
D D
LCTL_DATA P39 L_CTRL_CLK
L_CTRL_DATA
INT.PD 20K
1 2 LVDS_IBG AF37 P38
LVD_IBG SDVO_CTRLCLK UMA_HDMI_CLK15
RH143 2.37K_0402_1% AF36 M39 15
LVD_VBG SDVO_CTRLDATA UMA_HDMI_DATA
INT.PD 20K
AE48
AE47 LVD_VREFH AT49
LVD_VREFL DDPB_AUXN AT47
DDPB_AUXP AT40 HDMI_HPD 02/20 Delete RH254 100K
DDPB_HPD HDMI_HPD 15,21
13 AK39
LCD_TXCLK- LVDSA_CLK#

LVDS
13 AK40 AV42
LCD_TXCLK+ LVDSA_CLK DDPB_0N UMA_HDMI_TX2-15
AV40 15
+3VS DDPB_0P UMA_HDMI_TX2+
13 AN48 AV45
LCD_TXOUT0- LVDSA_DATA#0 DDPB_1N UMA_HDMI_TX1-15
RPH8 AM47 AV46
13 LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P 15
UMA_HDMI_TX1+ HDMI

Digital Display Interface


13 AK47 AU48
LCD_TXOUT2- LVDSA_DATA#2 DDPB_2N UMA_HDMI_TX0-15
1 8 LCTL_CLK AJ48 AU47 15
LVDSA_DATA#3 DDPB_2P UMA_HDMI_TX0+
2 7 LCTL_DATA AV47
DDPB_3N UMA_HDMI_CLK-15
3 6 LCD_EDID_CLK 13 AN47 AV49 15
LCD_TXOUT0+ LVDSA_DATA0 DDPB_3P UMA_HDMI_CLK+
4 5 LCD_EDID_DATA 13 AM49
LCD_TXOUT1+ LVDSA_DATA1
13 AK49
LCD_TXOUT2+ LVDSA_DATA2
2.2K_0804_8P4R_5% AJ47 P46
LVDSA_DATA3 DDPC_CTRLCLK P42
DDPC_CTRLDATA
INT.PD 20K
2 1 UMA_CRT_DATA AF40
RH142 2.2K_0402_5% AF39 LVDSB_CLK# AP47
CRT@ LVDSB_CLK DDPC_AUXN AP49
2 1 UMA_CRT_CLK AH45 DDPC_AUXP AT38 RH141 2 1 100K_0402_5%
RH144 2.2K_0402_5% AH47 LVDSB_DATA#0 DDPC_HPD
C CRT@ AF49 LVDSB_DATA#1 AY47 C
AF45 LVDSB_DATA#2 DDPC_0N AY49
LVDSB_DATA#3 DDPC_0P AY43
AH43 DDPC_1N AY45
AH49 LVDSB_DATA0 DDPC_1P BA47
AF47 LVDSB_DATA1 DDPC_2N BA48
AF43 LVDSB_DATA2 DDPC_2P BB47
LVDSB_DATA3 DDPC_3N BB49
DDPC_3P

14 UMA_CRT_B N48 M43


UMA_CRT_B CRT_BLUE DDPD_CTRLCLK
1 2 UMA_CRT_B 14 UMA_CRT_G P49 M36
UMA_CRT_G CRT_GREEN DDPD_CTRLDATA
RH154 150_0402_1% 14 UMA_CRT_R T49 INT.PD 20K
UMA_CRT_R CRT_RED
CRT@
1 2 UMA_CRT_G AT45
DDPD_AUXN

CRT
RH156 150_0402_1% 14 UMA_CRT_CLK UMA_CRT_CLK T39 AT43
CRT@ UMA_CRT_DATA M40 CRT_DDC_CLK DDPD_AUXP BH41 RH255 2 1 100K_0402_5%
14 UMA_CRT_DATA CRT_DDC_DATA DDPD_HPD
1 2 UMA_CRT_R
RH152 150_0402_1% BB43
CRT@ M47 DDPD_0N BB45
14 UMA_CRT_HSYNC CRT_HSYNC DDPD_0P
14 M49 BF44
UMA_CRT_VSYNC CRT_VSYNC DDPD_1N BE44
DDPD_1P BF42
2 1 CRT_IREF T43 DDPD_2N BE42
RH138 1K_0402_0.5% T42 DAC_IREF DDPD_2P BJ42
CRT_IRTN DDPD_3N BG42
CRT@ DDPD_3P
PANTHER-POINT_FCBGA989
B HM76R3@ B

RH138
1K_0402_5%
NOCRT@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_CRT/LVDS/HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 19 of 46
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn/
UH1E
AY7
RSVD1 AV7 10/24B PLT_RST# Add RH173 100K Pull Down to GND
BG26 RSVD2 AU3
BJ26 TP1 RSVD3 BG4
BH25 TP2 RSVD4
BJ16 TP3 AT10
BG16 TP4 RSVD5 BC8 PLT_RST#
AH38 TP5 RSVD6 9/28 Delete PLTRST_VGA# Circuit
D AH37 TP6 AU2 D
AK43 TP7 RSVD7 AT4
TP8 RSVD8

2
AK45 AT3
C18 TP9 RSVD9 AT1 RH173
N30 TP10 RSVD10 AY3 100K_0402_5%
H3 TP11 RSVD11 AT5
AH12 TP12 RSVD12 AV3

1
AM4 TP13 RSVD13 AV1
AM5 TP14 RSVD14 BB1
Y13 TP15 RSVD15 BA3
K24 TP16 RSVD16 BB5
L24 TP17 RSVD17 BB3
AB46 TP18 RSVD18 BB7
AB45 TP19 RSVD19 BE8
TP20 RSVD20

RSVD
BD4
RSVD21 BF6
RSVD22
B21 AV5 NV_ALE
+3VS M20 TP21 RSVD23 AV10
RPH12 AY16 TP22 RSVD24
BG46 TP23 AT8
1 8 PCH_GPIO52 TP24 RSVD25
2 7 PCH_GPIO2 AY5
3 6 PCH_GPIO51 RSVD26 BA2
4 5 ODD_DA# U3RXDN1 BE28 RSVD27
29 U3RXDN1 USB3Rn1
U3RXDN2 BC30 AT12 Note: HM70 only enable
29 U3RXDN2 USB3Rn2 RSVD28
8.2K_0804_8P4R_5% BE32 BF3 USB port 0, 1, 2, 3, 8, 9, 10, 11
BJ32 USB3Rn3 RSVD29
U3RXDP1 BC28 USB3Rn4
29 U3RXDP1 USB3Rp1
RPH13 U3RXDP2 BE30
29 U3RXDP2 USB3Rp2
BF32 INT.PD 20K
1 8 PCI_PIRQD# BG32 USB3Rp3 C24 USB20_N0
C USB3Rp4 USBP0N USB20_N0 29 C
2 7 PCI_PIRQA# U3TXDN1 AV26 A24 USB20_P0 USB-Right1 Intel Anti-Theft Techonlogy
29 U3TXDN1 USB3Tn1 USBP0P USB20_P0 29
3 6 PCI_PIRQB# U3TXDN2 BB26 C25 USB20_N1
29 U3TXDN2 USB3Tn2 USBP1N USB20_N1 29
4 5 PCI_PIRQC# AU28 B25 USB20_P1 USB-Right2 High=Endabled
USB3Tn3 USBP1P USB20_P1 29
AY30 C26 USB20_N2 NV_ALE
USB3Tn4 USBP2N USB20_N2 27
8.2K_0804_8P4R_5% U3TXDP1 AU26 A26 USB20_P2 Low=Disable(floating)
29 U3TXDP1 U3TXDP2 AY26 USB3Tp1 USBP2P K28 USB20_N3 USB20_P2 27 USB-Left *
29 U3TXDP2 USB3Tp2 USBP3N USB20_N3 28
AV28 H28 USB20_P3 CardReader
USB3Tp3 USBP3P USB20_P3 28 +1.8VS
10K_0402_5% RH176 AW30 EHCI 1 E28
1 2 PCH_GPIO54 USB3Tp4 USBP4N D28
USBP4P C28 NV_ALE 1 @ 2
USBP5N A28 RH164 1K_0402_5%
8.2K_0402_5% RH305 USBP5P C29
1 2 PCH_GPIO4 USBP6N B29
PCI_PIRQA# K40 USBP6P N28
8.2K_0402_5% RH306 PCI_PIRQB# K38 PIRQA# USBP7N M28
PIRQB# USBP7P

PCI
1 2 PCH_GPIO5 PCI_PIRQC# H38 L30 USB20_N8
PIRQC# USBP8N USB20_N8 13
PCI_PIRQD# G38 K30 USB20_P8 Touch Screen
PIRQD# USBP8P USB20_P8 13
8.2K_0402_5% RH307 G30 USB20_N9
USBP9N USB20_N9 26
1 2 PCH_GPIO50 PCH_GPIO50 C46 E30 USB20_P9 BT
REQ1# / GPIO50 USBP9P USB20_P9 26

USB
PCH_GPIO52 C44 C30 10/18B Add USB port 10 for NFC
PCH_GPIO54 E40 REQ2# / GPIO52 USBP10N A30 11/28 Delete NFC Function
REQ3# / GPIO54 EHCI 2 USBP10P L32 USB20_N11
NFC
USBP11N USB20_N11 13
PCH_GPIO51 D47 INT.PU 20K K32 USB20_P11 Int. Camera
GNT1# / GPIO51 USBP11P USB20_P11 13
E42 INT.PU 20K G32
9/28 change DGPU_RST#/ DGPU_PWR_EN F46 GNT2# / GPIO53 USBP12N E32
to PCH_GPIO50/54, then PCH_GPIO50 8.2k GNT3# / GPIO55 INT.PU 20K USBP12P C32
pull high to +3vs USBP13N A32
PCH_GPIO2 G42 USBP13P
ODD_DA# G40 PIRQE# / GPIO2
25 ODD_DA# PIRQF# / GPIO3
PCH_GPIO4 C42 C33 USBBIAS 1 2
PCH_GPIO5 D44 PIRQG# / GPIO4 USBRBIAS# RH165 22.6_0402_1%
PIRQH# / GPIO5
B B33
Within 500 mils B
PCI_PME# K10 USBRBIAS
2013/02/28change RH167 pin2 netname
T80 PAD PME# INT.PU 20K
from CLK_EC_R to CLK_PCI_EC_R PLT_RST# C6 A14 USB_OC#0 USB-Right Rear
2013 back to CLK_EC_R as the same for DIS 5,26,27,32 PLT_RST# PLTRST# OC0# / GPIO59 USB_OC#0 17,29,32
K20 USB_CHG_OC# OC#1 PH @ page 26
OC1# / GPIO40 B17 USB_OC#2 USB_CHG_OC# 29,32 USB-Right Front CB0 PH @ page 27
OC2# / GPIO41 USB_OC#2 27,32 USB-Left
32 22_0402_5% 1 EMI@ 2 RH167 CLK_EC_R H49 INT.PD 20K C16 SLP_CHG_CB1
CLK_PCI_EC CLK_PCH H43 CLKOUT_PCI0 OC3# / GPIO42 L16 SLP_CHG_CB0 SLP_CHG_CB1 17,29 +3VALW_PCH
17 CLK_PCILOOP
0_0402_5% RH166 INT.PD
CLKOUT_PCI1 20K OC4# / GPIO43 SLP_CHG_CB0 17,29
CLK_PCI_DDR J48 INT.PD 20K A16 USB_OC#5_7
T81 PAD CLKOUT_PCI2 OC5# / GPIO9
1 K42 INT.PD 20K D14 RPH11
CLKOUT_PCI3 OC6# / GPIO10
22P_0402_50V8J
CH115

H40 INT.PD 20K C14


CLKOUT_PCI4 OC7# / GPIO14 PCH_GPIO28 1 8
21 PCH_GPIO28
@RF@2012/10/19A Change RH166 to short pad USB_CHG_OC# 2 7
2 2013/02/06 PVT change back to 0 ohm again PANTHER-POINT_FCBGA989 USB_OC#2 3 6
HM76R3@ USB_OC#5_7 4 5

10K_0804_8P4R_5%

11/30 Move PLT_RST# ESD capacitor (CH104)


to EC side (CB13) and mount 0.1u for ESD request
Boot BIOS Strap
PCH_GPIO51 PCH_GPIO19 Boot BIOS Loaction
ESD@
180P_0402_50V8J 1 2 CH105 ODD_DA# LPC
0 0
0 1 Reserved
1 0 PCI
1K_0402_5% 2 @ 1 RH293 PCH_GPIO51
1 1 SPI *
1K_0402_5% 2 @ 1 RH294 PCH_GPIO19
16
A PCH_GPIO19 A

10/18 Need confirm PCH_GPIO55, A16 Swap Override Strap


10/19A remove RH295
Low= A16 swap override Enable
WL_OFF# * High= A16 swap override Disable Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_PCI/USB/NAND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 20 of 46
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn/ UH1F +3VS


INT.PH 20K
HDMI_HPD 15,19 T7 C40 ODD_EN# 34
+3VALW _PCH HDMI_HPD BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN#
INT.PH 20K RPH16
A42 B41
TACH1 / GPIO1INT.PH 20K CPU_PGA_BGA#
TACH5 / GPIO69 for common BIOS on PBA/BGA CPU 1 8
INT.PH 20K ODD_EN#
2 1 H36 C41 2 7
TACH2 / GPIO6INT.PH 20K
EC_LID_OUT# SPK_DET 31 GATEA20
TACH6 / GPIO70 SPK_DET
RH204 1K_0402_5% INT.PH 20K KB_RST# 3 6
E38 A40 4 5
TACH3 / GPIO7INT.PH 20K
32 EC_SCI# EC_SCI#
TACH7 / GPIO71
D D
C10 INT.PH 20K 11/28 Change SPK_DET0 10K_0804_8P4R_5%
17,32(PH) EC_SMI# GPIO8 to SPK_DET, delete SPK_DET1
+3VS C4 CPU_PGA_BGA# 2 1
LAN_PHY_PWR_CTRL / GPIO12 RH181 10K_0402_5%
G2 P4
GPIO15 INT.PD 20K
32 EC_LID_OUT# EC_LID_OUT# GATEA20 32
A20GATE GATEA20
1 2 ODD_DETECT# INT.PD 350 AU16
RH178 200K_0402_5% PCH_GPIO16 U2 PECI
SATA4GP / GPIO16 P5 KB_RST#
RCIN# KB_RST# 32
2 1 PCH_GPIO17

GPIO
RH179 10K_0402_5% PCH_GPIO17 D40 INT.PH 20K AY11 H_PW RGOOD
TACH0 / GPIO17 PROCPWRGD H_PW RGOOD 5

CPU/MISC
2 1 PCH_GPIO38 T5 AY10 PCH_THRMTRIP# 1 2 Non-Harman detection
SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP#5
RH180 10K_0402_5% RH191 390_0402_5%
9/28 change VGA_PWROK to PCH_GPIO17, E8 INT.PH 20K T14
10k pull high to +3vs GPIO24 INIT3_3V#
This signal has weak internal
E16 AY1
GPIO27 INT.PH 20K INT.PD 20K
PCH_GPIO27 NV_CLE 0 ONKYO
DF_TVS pull-up, can't be pulled low
P8
(PH) PCH_GPIO28 20 GPIO28 INT.PH 20K
AH8
SPK_DET
PCH_GPIO34 K1 TS_VSS1 (GPIO70)
+3VS 10/24DChange BT_ON# to PCH_GPIO34 STP_PCI# / GPIO34 AK11
1 Non-Brand
K4 TS_VSS2
RPH15 GPIO35 AH10
1 8 V8 TS_VSS3
PCH_GPIO34 25 ODD_DETECT#
ODD_DETECT#
SATA2GP / GPIO36 INT.PD 20K
2 7 PCH_GPIO16 AK10
3 6 M5 TS_VSS4
EC_SCI#
PCH_GPIO37 18 SATA3GP / GPIO37 INT.PD 20K
4 5 PCH_GPIO49 (PH)
C PCH_GPIO38 N2 P37 C
10K_0804_8P4R_5% (PH) SLOAD / GPIO38 NC_1
M3
SDATAOUT0 / GPIO39
269@ SM_DET V13 BG2
2 1 SM_DET 9/28 change OPTIMUS_EN# to PCH_GPIO38, SDATAOUT1 / GPIO48 VSS_NCTF_15
10k pull high to +3vs @ESD@
RH200 10K_0402_5% PCH_GPIO49 V3 BG48 H_THERMTRIP# 1 2
SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
D6 BH3 CC21
259@ GPIO57 VSS_NCTF_17 100P_0402_50V8J
2 1 SM_DET BH47
RH201 10K_0402_5% VSS_NCTF_18
Follow Compal ORB A4 BJ4
2 @ 1 PCH_GPIO27 VSS_NCTF_1 VSS_NCTF_19
and Intel Check list 460603 V1.5
RH199 10K_0402_5% A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
A45 BJ45
VSS_NCTF_3 VSS_NCTF_21

NCTF
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22
DMI & FDI Termination Voltage
SM_DET BIOS setup Speaker Type BOM A5 BJ5
VSS_NCTF_5 VSS_NCTF_23
(GPIO48) A6 BJ6 Set to VCC when HIGH
VSS_NCTF_6 VSS_NCTF_24
NV_CLE
1 S&M option Harman/Kardon 269@ B3 C2 Set to VSS when LOW
VSS_NCTF_7 VSS_NCTF_25
B47 C48
VSS_NCTF_8 VSS_NCTF_26
BD1 D1 +1.8VS
B 0 Non Harman 259@ VSS_NCTF_9 VSS_NCTF_27 B
BD49 D49
VSS_NCTF_10 VSS_NCTF_28

1
BE1 E1 RH187
VSS_NCTF_11 VSS_NCTF_29
2.2K_0402_5%
BE49 E49
VSS_NCTF_12 VSS_NCTF_30

2
BF1 F1
VSS_NCTF_13 VSS_NCTF_31 NV_CLE 2 1 H_SNB_IVB# 5
BF49 F49 RH189 1K_0402_5%
VSS_NCTF_14 VSS_NCTF_32
GPIO28
On-Die PLL Voltage Regulator PANTHER-POINT_FCBGA989

* H: Enable HM76R3@
L: Disable

OPTIMUS_EN#

GPIO8 OPTIMUS_EN# H L
Integrated Clock Chip Enable (Removed)
H: Disable
L: Enable SKU NonOPT Optimus
*
A A

Integrated clock enable functionality


is achieved by soft-strap Security Classification Compal Secret Data Compal Electronics, Inc.
The current default is clock enable Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_CPU/GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 21 of 46
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn/
+1.05VS_VCCP UH1G POWER +3VS

JP@ PJ4
PCH Power Rail Table
1730mA RH309 LH1
Refer to PCH EDS R1.0
2 1 1U_0402_6.3V6K +1.05VS_PCH AA23 U48 +VCCA_DAC 0.1U_0402_10V7K 1 2 +VCCA_DAC_R2 1
2 1 AC23 VCCCORE[1] 1mA VCCADAC 1_0603_1% BLM18PG181SN1D_0603
VCCCORE[2] 1 1
JUMP_43X79 1 1 1 1 AD21 CH35 CH36 CH37 S0 Iccmax

CRT
AD23 VCCCORE[3] U47
CH32 CH33 CH31 CH34
VCCCORE[4] VSSADAC
0.01U_0402_25V7K 10U_0603_6.3V6M Voltage Rail Voltage Current (A)
D AF21 D

VCC CORE
10U_0603_6.3V6M AF23 VCCCORE[5] 2 2
2 2 2 2 AG21 VCCCORE[6] +3VS
VCCCORE[7]
V_PROC_IO 1.05 0.001
AG23
AG24 VCCCORE[8] AK36 +VCCA_LVDS 1 Rshort@ 2
1U_0402_6.3V6K 1U_0402_6.3V6K
VCCCORE[9] 1mA VCCALVDS
AG26 RH208 0_0402_5% V5REF 5 0.001
AG27 VCCCORE[10] AK37
AG29 VCCCORE[11] VSSALVDS
AJ23 VCCCORE[12]
VCCCORE[13]
V5REF_Sus 5 0.001
+1.8VS

LVDS
AJ26 AM37
AJ27 VCCCORE[14] VCCTX_LVDS[1] LH2
AJ29 VCCCORE[15] AM38 +VCCTX_LVDS 2 1
VCCCORE[16] VCCTX_LVDS[2]
0.01U_0402_25V7K Vcc3_3 3.3 0.228
AJ31 1 BLM18PG181SN1D_0603
VCCCORE[17] AP36
+1.05VS_PCH 60mA VCCTX_LVDS[3]
CH40
CH38 CH39 22U_0805_6.3V6M VccADAC 3.3 0.063
AP37 0.01U_0402_25V7K
AN19 VCCTX_LVDS[4] 2
VCCIO[28]
VccADPLLA 1.05 0.08
This pin can be left as NC if BJ22 +3VS
On-Die VR is enabled (Default) PAD T82 VCCAPLLEXP
VccADPLLB 1.05 0.08
V33
AN16 VCC3_3[6]

HVCMOS
VCCIO[15]
1 VccCore 1.05 1.7
AN17 CH42
VCCIO[16] V34 0.1U_0402_10V7K
VCC3_3[7]
VccDMI 1.1 0.047
AN21 2
VCCIO[17] +VCCAFDI_VRM +1.5VS
AN26 VccIO 1.05 3.711
VCCIO[18] RH221 0_0402_5%
AN27 AT16 +VCCAFDI_VRM 1 Rshort@ 2
C VCCIO[19] 3709mA VCCVRM[3] C
VccASW 1.05 0.903
+1.05VS_PCH AP21 +VCCP_VCCDMI +1.05VS_VCCP
VCCIO[20] RH213 0_0402_5%
1U_0402_6.3V6K AP23 AT20 +VCCP_VCCDMI 1 Rshort@ 2 VccSPI 3.3 0.01
VCCIO[21] VCCDMI[1]
1
+1.05VS_PCH

DMI
1 1 1 1 1 AP24
VCCIO[22]

VCCIO
CH43 CH45 CH46 CH47 CH44 RH214 0_0402_5% CH48 VccDSW 3.3 0.001
AP26 AB36 +1.05VS_VCC_DMI 1 Rshort@ 2 1U_0402_6.3V6K
10U_0603_6.3V6M 1U_0402_6.3V6K VCCIO[23] 75mA VCCCLKDMI 2
2 2 2 2 2 1
AT24 VccDFTERM 1.8 0.002
VCCIO[24] CH49
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
AN33 2 VccRTC 3.3 N/A
VCCIO[25]
VCCDFTERM
AN34 AG16 +1.8VS
+3VS VCCIO[26] VCCDFTERM[1]
VccSus3_3 3.3 0.095
BH29 AG17
VCC3_3[3] VCCDFTERM[2]
1 DFT / SPI 1 VccSusHDA 3.3 0.01
CH50 190mA
0.1U_0402_10V7K AJ16 CH51
VCCDFTERM[3] 0.1U_0402_10V7K VccVRM 1.5 0.167
2 +VCCAFDI_VRM AP16 2
VCCVRM[2] AJ17
VCCDFTERM[4]
VccCLKDMI 1.05 0.07
This pin can be left as NC if BG6
PAD T83 VccAFDIPLL +3VALW_PCH
On-Die VR is enabled (Default) VccSSC 1.05 0.095
AP17
+1.05VS_PCH VCCIO[27] V1 10/18B Change VCCSPI from +3VS to +3VALW_PCH
FDI

20mA VCCSPI
VccDIFFCLKN 1.05 0.055
AU20 1
B +VCCP_VCCDMI VCCDMI[2] B
CH53 VccALVDS 3.3 0.001
PANTHER-POINT_FCBGA989 1U_0402_6.3V6K
2
HM76R3@ VccTX_LVDS 1.8 0.04

+3VALW to +3VALW_PCH
+3VALW +3VALW_PCH

QH2
AO3413_SOT23

3 1
S

D
CH111

CH112

CH113
G

1 1
2

0.01U_0402_25V7K

0.1U_0402_10V7K
0.1U_0402_25V6

2 2

A A

PCH_PWR_EN# 2 1
23,34 PCH_PWR_EN#
RH3 47K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_POWER-1
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 22 of 46
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn/
+5VALW +5VALW_PCH

+3VS

LH5
1 2 +3VS_VCC_CLKF33
10UH_LB2012T100MR_20% 1 1
This pin can be left as NC if
CH73 CH74 QH6
10U_0603_6.3V6M 1U_0402_6.3V6K On-Die VR is enabled (Default) AO3413_SOT23
2 2 UH1J POWER +1.05VS_PCH 3 1

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
AD49 N26
+3VALW_PCH VCCACLK VCCIO[29]

G
1 1

2
D P26 D
VCCIO[30] 1

CH59
T16 CH56
VCCDSW3_3 3mA

CH80
P28 1U_0402_6.3V6K
VCCIO[31] 2 2
1 2
CH55 V12 T27
0.1U_0402_10V7K DCPSUSBYP VCCIO[32] RH328
T29 2 1
2 VCCIO[33] +3VALW_PCH 22,34 PCH_PWR_EN#
+3VS_VCC_CLKF33 T38 47K_0402_5%
VCC3_3[5]
T23
BH23 VCCSUS3_3[7]
VCCAPLLDMI2 1
119mA VCCSUS3_3[8] T24 CH60 +3VALW_PCH
AL29 0.1U_0402_10V7K
+1.05VS_PCH VCCIO[14] V23
VCCSUS3_3[9] 2

USB
1 Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB
AL24 V24
DCPSUS[3] VCCSUS3_3[10] CH61
P24 0.1U_0402_10V7K
VCCSUS3_3[6] 2
AA19 +5VALW_PCH +3VALW_PCH
+1.05VS_PCH VCCASW[1] T26
VCCIO[34] +1.05VS_PCH
AA21 1010mA
VCCASW[2]

2
AA24 1mA M26 +PCH_V5REF_SUS RH232 DH3
VCCASW[3] V5REF_SUS
10_0402_5%
1 1 AA26 CH751H-40PT_SOD323-2

Clock and Miscellaneous


CH64 CH65 VCCASW[4] AN23

1
AA27 DCPSUS[4] +PCH_V5REF_SUS
22U_0805_6.3V6M VCCASW[5] AN24
2 2 VCCSUS3_3[1] +3VALW_PCH 1
AA29 CH63
22U_0805_6.3V6M VCCASW[6] 1 2
AA31 CH66 0.1U_0402_10V7K 0.1U_0402_10V7K
C VCCASW[7] 2 C
1U_0402_6.3V6K AC26 P34 +PCH_V5REF_RUN
1 1 1
VCCASW[8] 1mA V5REF +3VALW_PCH
CH67 CH68 CH69 AC27
VCCASW[9] N20
+1.05VS_PCH 1U_0402_6.3V6K 1U_0402_6.3V6K AC29 VCCSUS3_3[2]

PCI/GPIO/LPC
2 2 2 VCCASW[10] 1 +5VS +3VS
N22 CH70 CH63 & CH71 are
LH7 AC31 VCCSUS3_3[3] 1U_0402_6.3V6K
VCCASW[11] different by Intel CRB.
1 2 +1.05VS_VCCADPLLA P20
VCCSUS3_3[4]

2
BLM18PG181SN1D_0603 AD29 2
LH8 VCCASW[12] P22 RH237 DH4
1 2 +1.05VS_VCCADPLLB AD31 VCCSUS3_3[5] +3VS
VCCASW[13] 10_0402_5%
BLM18PG181SN1D_0603 CH751H-40PT_SOD323-2
W21 AA16

1
VCCASW[14] VCC3_3[1] +PCH_V5REF_RUN
1 1 1 1 +3VS 1
CH93 CH94 CH95 CH96 W23 W16 CH72 1
1U_0402_6.3V6K VCCASW[15] VCC3_3[8] 0.1U_0402_10V7K
1U_0402_6.3V6K W24 T34 CH71
2 2 2 2 VCCASW[16] VCC3_3[4] 2 1U_0402_6.3V6K
10U_0603_6.3V6M 10U_0603_6.3V6M W26 1 2 2
VCCASW[17] CH75
W29 0.1U_0402_10V7K +3VS
VCCASW[18]
W31 AJ2
VCCASW[19] VCC3_3[2] +1.05VS_PCH
1
W33
VCCASW[20] AF13 CH76
VCCIO[5] 0.1U_0402_10V7K
+VCCRTCEXT N16 2
DCPRTC 1
1 AH13 CH77
CH78 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14
B VCCVRM[4] VCCIO[13] 2 B
2 Place CH77 near pin AF13, AH13, AH14, AF14
AF14 This pin can be left as NC if
+1.05VS_VCCADPLLA BD47 VCCIO[6]
VCCADPLLA 80mA On-Die VR is enabled (Default)

SATA
AK1
+1.05VS_PCH +1.05VS_VCCADPLLB BF47 VCCAPLLSATA +VCCAFDI_VRM
VCCADPLLB 80mA
Place CH79 near pin AF17 1 AF11 +VCCAFDI_VRM
AF17 VCCVRM[1] +1.05VS_PCH
CH79
VCCIO[7] 55mA
1U_0402_6.3V6K AF33
AF34 VCCDIFFCLKN[1] AC16
+1.05VS_PCH +1.05VS_VCCDIFFCLKN 2 +1.05VS_VCCDIFFCLKN AG34 VCCDIFFCLKN[2] VCCIO[2]
RH247 0_0402_5% +1.05VS_PCH VCCDIFFCLKN[3] AC17
VCCIO[3] 1
1 Rshort@ 2 +1.05VS_VCCDIFFCLKN CH82
1 AG33 AD17 1U_0402_6.3V6K
CH81 VCCSSC 95mA VCCIO[4]
1 2
1U_0402_6.3V6K CH84
1U_0402_6.3V6K +VCCSST V16 Place CH82 near pin AC16, AC17, AD17
2 DCPSST +1.05VS_PCH
2 1
0.1U_0402_10V7K
T17 T21
CH85 V19 DCPSUS[1] VCCASW[22]
2 DCPSUS[2]
MISC

+1.05VS_VCCP V21
VCCASW[23]
1mA
CPU

0.1U_0402_10V7K BJ8
V_PROC_IO T19
VCCASW[21]
1 1 1
CH87 CH88 +RTCVCC
CH86 +3VALW_PCH
4.7U_0603_6.3V6K 0.1U_0402_10V7K 0.1U_0402_10V7K A22 10mA P32
RTC

2 2 2 VCCRTC VCCSUSHDA
HDA

A A
1 1
CH90 PANTHER-POINT_FCBGA989 CH92
Place CH86, CH87, CH88 near pin BJ8 HM76R3@ 0.1U_0402_10V7K
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_POWER-2
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 23 of 46
5 4 3 2 1
5 4 3 2 1

http://laptopblue.vn/
UH1I

AY4 H46
AY42 VSS[159] VSS[259] K18
AY46 VSS[160] VSS[260] K26
AY8 VSS[161] VSS[261] K39
B11 VSS[162] VSS[262] K46
UH1H B15 VSS[163] VSS[263] K7
H5 B19 VSS[164] VSS[264] L18
VSS[0] B23 VSS[165] VSS[265] L2
AA17 AK38 B27 VSS[166] VSS[266] L20
AA2 VSS[1] VSS[80] AK4 B31 VSS[167] VSS[267] L26
AA3 VSS[2] VSS[81] AK42 B35 VSS[168] VSS[268] L28
AA33 VSS[3] VSS[82] AK46 B39 VSS[169] VSS[269] L36
D VSS[4] VSS[83] VSS[170] VSS[270] D
AA34 AK8 B7 L48
AB11 VSS[5] VSS[84] AL16 F45 VSS[171] VSS[271] M12
AB14 VSS[6] VSS[85] AL17 BB12 VSS[172] VSS[272] P16
AB39 VSS[7] VSS[86] AL19 BB16 VSS[173] VSS[273] M18
AB4 VSS[8] VSS[87] AL2 BB20 VSS[174] VSS[274] M22
AB43 VSS[9] VSS[88] AL21 BB22 VSS[175] VSS[275] M24
AB5 VSS[10] VSS[89] AL23 BB24 VSS[176] VSS[276] M30
AB7 VSS[11] VSS[90] AL26 BB28 VSS[177] VSS[277] M32
AC19 VSS[12] VSS[91] AL27 BB30 VSS[178] VSS[278] M34
AC2 VSS[13] VSS[92] AL31 BB38 VSS[179] VSS[279] M38
AC21 VSS[14] VSS[93] AL33 BB4 VSS[180] VSS[280] M4
AC24 VSS[15] VSS[94] AL34 BB46 VSS[181] VSS[281] M42
AC33 VSS[16] VSS[95] AL48 BC14 VSS[182] VSS[282] M46
AC34 VSS[17] VSS[96] AM11 BC18 VSS[183] VSS[283] M8
AC48 VSS[18] VSS[97] AM14 BC2 VSS[184] VSS[284] N18
AD10 VSS[19] VSS[98] AM36 BC22 VSS[185] VSS[285] P30
AD11 VSS[20] VSS[99] AM39 BC26 VSS[186] VSS[286] N47
AD12 VSS[21] VSS[100] AM43 BC32 VSS[187] VSS[287] P11
AD13 VSS[22] VSS[101] AM45 BC34 VSS[188] VSS[288] P18
AD19 VSS[23] VSS[102] AM46 BC36 VSS[189] VSS[289] T33
AD24 VSS[24] VSS[103] AM7 BC40 VSS[190] VSS[290] P40
AD26 VSS[25] VSS[104] AN2 BC42 VSS[191] VSS[291] P43
AD27 VSS[26] VSS[105] AN29 BC48 VSS[192] VSS[292] P47
AD33 VSS[27] VSS[106] AN3 BD46 VSS[193] VSS[293] P7
AD34 VSS[28] VSS[107] AN31 BD5 VSS[194] VSS[294] R2
AD36 VSS[29] VSS[108] AP12 BE22 VSS[195] VSS[295] R48
AD37 VSS[30] VSS[109] AP19 BE26 VSS[196] VSS[296] T12
AD38 VSS[31] VSS[110] AP28 BE40 VSS[197] VSS[297] T31
AD39 VSS[32] VSS[111] AP30 BF10 VSS[198] VSS[298] T37
AD4 VSS[33] VSS[112] AP32 BF12 VSS[199] VSS[299] T4
AD40 VSS[34] VSS[113] AP38 BF16 VSS[200] VSS[300] W34
C AD42 VSS[35] VSS[114] AP4 BF20 VSS[201] VSS[301] T46 C
AD43 VSS[36] VSS[115] AP42 BF22 VSS[202] VSS[302] T47
AD45 VSS[37] VSS[116] AP46 BF24 VSS[203] VSS[303] T8
AD46 VSS[38] VSS[117] AP8 BF26 VSS[204] VSS[304] V11
AD8 VSS[39] VSS[118] AR2 BF28 VSS[205] VSS[305] V17
AE2 VSS[40] VSS[119] AR48 BD3 VSS[206] VSS[306] V26
AE3 VSS[41] VSS[120] AT11 BF30 VSS[207] VSS[307] V27
AF10 VSS[42] VSS[121] AT13 BF38 VSS[208] VSS[308] V29
AF12 VSS[43] VSS[122] AT18 BF40 VSS[209] VSS[309] V31
AD14 VSS[44] VSS[123] AT22 BF8 VSS[210] VSS[310] V36
AD16 VSS[45] VSS[124] AT26 BG17 VSS[211] VSS[311] V39
AF16 VSS[46] VSS[125] AT28 BG21 VSS[212] VSS[312] V43
AF19 VSS[47] VSS[126] AT30 BG33 VSS[213] VSS[313] V7
AF24 VSS[48] VSS[127] AT32 BG44 VSS[214] VSS[314] W17
AF26 VSS[49] VSS[128] AT34 BG8 VSS[215] VSS[315] W19
AF27 VSS[50] VSS[129] AT39 BH11 VSS[216] VSS[316] W2
AF29 VSS[51] VSS[130] AT42 BH15 VSS[217] VSS[317] W27
AF31 VSS[52] VSS[131] AT46 BH17 VSS[218] VSS[318] W48
AF38 VSS[53] VSS[132] AT7 BH19 VSS[219] VSS[319] Y12
AF4 VSS[54] VSS[133] AU24 H10 VSS[220] VSS[320] Y38
AF42 VSS[55] VSS[134] AU30 BH27 VSS[221] VSS[321] Y4
AF46 VSS[56] VSS[135] AV16 BH31 VSS[222] VSS[322] Y42
AF5 VSS[57] VSS[136] AV20 BH33 VSS[223] VSS[323] Y46
AF7 VSS[58] VSS[137] AV24 BH35 VSS[224] VSS[324] Y8
AF8 VSS[59] VSS[138] AV30 BH39 VSS[225] VSS[325] BG29
AG19 VSS[60] VSS[139] AV38 BH43 VSS[226] VSS[328] N24
AG2 VSS[61] VSS[140] AV4 BH7 VSS[227] VSS[329] AJ3
AG31 VSS[62] VSS[141] AV43 D3 VSS[228] VSS[330] AD47
AG48 VSS[63] VSS[142] AV8 D12 VSS[229] VSS[331] B43
AH11 VSS[64] VSS[143] AW14 D16 VSS[230] VSS[333] BE10
AH3 VSS[65] VSS[144] AW18 D18 VSS[231] VSS[334] BG41
B AH36 VSS[66] VSS[145] AW2 D22 VSS[232] VSS[335] G14 B
AH39 VSS[67] VSS[146] AW22 D24 VSS[233] VSS[337] H16
AH40 VSS[68] VSS[147] AW26 D26 VSS[234] VSS[338] T36
AH42 VSS[69] VSS[148] AW28 D30 VSS[235] VSS[340] BG22
AH46 VSS[70] VSS[149] AW32 D32 VSS[236] VSS[342] BG24
AH7 VSS[71] VSS[150] AW34 D34 VSS[237] VSS[343] C22
AJ19 VSS[72] VSS[151] AW36 D38 VSS[238] VSS[344] AP13
AJ21 VSS[73] VSS[152] AW40 D42 VSS[239] VSS[345] M14
AJ24 VSS[74] VSS[153] AW48 D8 VSS[240] VSS[346] AP3
AJ33 VSS[75] VSS[154] AV11 E18 VSS[241] VSS[347] AP1
AJ34 VSS[76] VSS[155] AY12 E26 VSS[242] VSS[348] BE16
AK12 VSS[77] VSS[156] AY22 G18 VSS[243] VSS[349] BC16
AK3 VSS[78] VSS[157] AY28 G20 VSS[244] VSS[350] BG28
VSS[79] VSS[158] G26 VSS[245] VSS[351] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[246] VSS[352]
G36 VSS[247]
HM76R3@ G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]

PANTHER-POINT_FCBGA989

A HM76R3@ A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH_GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 24 of 46
5 4 3 2 1
A B C D E

SATA HDD Conn.


JHDD
Close to JHDD http://laptopblue.vn/
SATA ODD Conn
Power Consumption
1
GND 2 SATA_PTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K JODD
Close to JODD
A+ 16
SATA_PTX_DRX_P0
3 SATA_PTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K Peak 1800 mA
A- 16
SATA_PTX_DRX_N0
4 1 Read (CD) 1100 mA
GND 5 SATA_PRX_DTX_N0 C368 1 2 0.01U_0402_25V7K GND 2 SATA_PTX_C_DRX_P2 C376 1 2 0.01U_0402_25V7K
B- 6
16
SATA_PRX_C_DTX_N0 A+ 16
SATA_PTX_DRX_P2 Read (DVD) 950 mA
SATA_PRX_DTX_P0 C370 1 2 0.01U_0402_25V7K 3 SATA_PTX_C_DRX_N2 C377 1 2 0.01U_0402_25V7K
B+ 7
16
SATA_PRX_C_DTX_P0 A- 4
16
SATA_PTX_DRX_N2 Write 1300 mA
GND GND 5 SATA_PRX_DTX_N2 C378 1 2 0.01U_0402_25V7K Standby 20mA
B- 16
SATA_PRX_C_DTX_N2
6 SATA_PRX_DTX_P2 C375 1 2 0.01U_0402_25V7K
1 B+ 16
SATA_PRX_C_DTX_P2 1
8 7
V33 9 GND
V33 10 10/24Dchange JHDD pin 10
V33 11 +3VS 10/19A Add +3VS on JHDD from +3vs to NC 8
GND DP ODD_DETECT# 21
12 9
GND +5V +5VS_ODD
13 10
GND 14 +5V 11
V5 MD ODD_DA# 20
15 15 12
V5 16 14 GND GND 13
V5 17 +5VS GND GND
GND 18 +5VS_ODD
DAS/DSS Place components closely ODD CONN.
19 SANTA_202401-1
23 GND 20 +5VS
24 GND V12 21
Place closely JHDD SATA CONN. Conn@
GND V12
1.2A 1 1 1
22 C355 C360 C380
V12
1 1 1
C356 C357 C358 10U_0805_10V4Z 0.1U_0402_10V7K 0.1U_0402_10V7K
SUYIN_127043FR022G196ZR 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 2
Conn@ 10U_0805_10V4Z
2 2 2

G-Sensor
2 2

+5VS +3VS_HDP UG1 GSENSOR@


2 3 VOUTX CG1 1 2 GSENSOR@ 0.033U_0402_16V7K
+3VS_HDP Vdd1 Voutx
12 5 VOUTY CG2 1 2 GSENSOR@ 0.033U_0402_16V7K
Vdd2 Vouty 7 VOUTZ CG3 1 2 GSENSOR@ 0.033U_0402_16V7K
1 1 Voutz
CG12 UG3 GSENSOR@ CG13
1U_0402_6.3V6K 1U_0402_6.3V6K SELF_TEST 4 10
GSENSOR@ 1 5 GSENSOR@ 6 ST NC1 11
2 VIN VOUT 2 8 PD NC2 14
2 FS NC3 15
GND NC4 16
3 4 NC5
SHDN# BP 9 1
+3VS_HDP Rev GND1 13
G9191-330T1U_SOT23-5 GND2
SA000022I00 TSH352TR LGA 16P
SA00004GB00

UG2

1 11
3 17,32 EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 HDPACT 32 3

2
SELF_TEST 2 12 RG9
P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 47K_0402_5%
+3VS_HDP GSENSOR@
+3VS_HDP_R 3 13

1
RESET# P1_4/TXD0

RPG1 GXOUT 4 14
XOUT/P4_7 P1_3/KI3#/AN11/TZOUT HDPLOCK 32
1 8 +3VS_HDP_R RG10 47K_0402_5%
2 7 GXOUT 5 15 VOUTZ 2 1
3 6 GXIN VSS/AVSS P1_2/KI2#/AN10/CMP0_2 GSENSOR@
4 5 +3VS_HDP_M SA00003A600
GXIN 6 16
XIN/P4_6 P4_2/VREF +3VS_HDP
4.7K_8P4R_5%
GSENSOR@ 1
+3VS_HDP 7 17 VOUTX CG6
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_10V7K
GSENSOR@
+3VS_HDP_M 8 18 VOUTY 2
MODE P1_0/KI0#/AN8/CMP0_0

HDPINT RG7 2 1 1K_0402_5% 9 19


32 HDPINT P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
GSENSOR@

1 1 10 20
P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 EC_SMB_DA2 17,32
CG8
CG7 GSENSOR@
0.1U_0402_10V7K 0.1U_0402_10V7K R5F211B4D34SP GSENSOR@
GSENSOR@ 2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/G-Sensor
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. VFKTA
Date: Monday, March 11, 2013 Sheet 25 of 46
A B C D E
A B C D E

http://laptopblue.vn/
Slot 1 Half PCIe Mini Card-WLAN
WLAN&BT Combo module circuits

+3V_WLAN
40 mils BT BT
on module on module
0.1U_0402_10V7K Enable Disable
1 1 1
CM1 CM2 CM3 BT_ON H L
2 2 2
0.1U_0402_10V7K 4.7U_0603_6.3V6K
1 1
10/24D Delete QM1, change BT_ON design

10/24 Remove +1.5VS on WLAN pin6/28/48,


delete CM7, CM8 Delete RM22 (EC will programming H/L)
BT_ON 1 RM27 2 E51_RXD
From 32
EC BT_ON
1K_0402_5%
Reserve +1.5 power rail & cap.
to supoort unknown keypart. For isolate BT_ON and
Compal Debug Card.

10/24Dchange RM24 pin1 netname


from BT_CTRL to BT_ON +3V_WLAN
JWLAN
To EC
(Need pull-up +3VL) 32 1 2
WLAN_WAKE# 1 2
3 4
BT_ON 1 RM24 2 BT_CTRL_R 5 3 4 6
@ 0_0402_5% 7 5 6 8
17 CLKREQ_WLAN# 7 8
9 10
11 9 10 12
17 CLK_WLAN# 11 12
To PCH 17 13 14
CLK_WLAN 13 14
15 16
17
19
15
17
16
18
18
20
To EC +3VALW TO +3V_WLAN for WOWL
WL_OFF# WL_OFF# 32
21 19 20 22 PLT_RST#
21 22 PLT_RST# 5,20,27,32
17 23 24 To PCH
PCIE_PRX_WLANTX_N2 23 24 +3VALW
To PCH 17 25 26
PCIE_PRX_WLANTX_P2 25 26
27 28
29 27 28 30 +3VALW
WLAN/ WiFi 31 29 30 32
PM_SMBCLK 11,12,17,33
17
PCIE_PTX_C_WLANRX_N2 31 32 PM_SMBDATA 11,12,17,33
To PCH 17 33 34
2 PCIE_PTX_C_WLANRX_P2 33 34 2

1
35 36 USB20_N9 20 10/24Dchange RM31 to 10K, Add RM2 2 WOWL@
37 35 36 38 RM31 CM9
37 38 USB20_P9 WiMax/
20 BT Vgs=-4.5V,Id=3A,Rds<97mohm
+3V_WLAN 39 40 WOWL@ 10K_0402_5% 0.1U_0402_10V7K
41 39 40 42 LED_WIMAX#
41 42 LED_WIMAX# 33 1
43 44 Need short PJ3 if system

2
43 44

3
S
45 46 don't support WOWL
47 45 46 48 1 2 1 2
G
2 AO3413_SOT23
47 48 +3VS To 32
EC WOWL_EN#
32 E51_TXD 49 50 RM6 100K_0402_5% QM2
E51_TXD 49 50 +3V_WLAN
32 E51_RXD 51 52 47K_0402_5% 2
D
E51_RXD

1
51 52 RM30 WOWL@ WOWL@

1
53 54 WOWL@ CM10
GND1 GND2 RM2 RM1
Debug card using 0.01U_0402_25V7K
100K_0402_5% 1 1 2
LOTES_AAA-PCI-049-P06-A +3VS
0_0603_5%
Conn@ NOWOWL@

2
10/24 Change PJ3 to RM1 and add BOM structure "NOWOWL@"

+3VL +1.05VS_VCCP +3VALW


0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1 02/20 Delete CCL2, RCL5 1 1


CCL1 CCL3 CCL8
GCLK@ GCLK@ GCLK@
2 2 2
3 3

10/24 10/24 Change CCL2 to @


10/19A Change RCL2 to short pad
1
CCL14 for safety request
GCLK@ 22U_0805_6.3V6M
UCL1 GCLK@ RCL4
2 120_0603_5%
+3VALW 2 10 2 1 +RTC
15 VDD VBAT 11 GCLK@
+3VL +V3.3A NC 02/20 Delete RCL2
8 9 LAN_X1_R_R, LAN_X1_R
VDDIO_25M_A 32K PCH_RTCX1_R 16
+1.05VS_VCCP 3 12
VDDIO_25M_B NC PCH_X1_R_R 1 Rshort@ 2
PCH_X1_R 17
CLK_X1 1 5 PCH_X1_R_R RCL1 0_0402_5%
CLK_X2 16 XTAL_IN 25M_B 6
XTAL_OUT 25M_A
4
7 VSS
13 VSS
17 VSS 14
Thermal Pad VDD_RTC_OUT
2
SLG3NB244VTR_TQFN16_2X3
CCL13
GCLK@ 2.2U_0402_6.3V6M
YCL1 25MHZ 12PF X3G025000DK1H-X 1
PN: SA000057I00 GCLK@
CLK_X1 1 3 CLK_X2
1 3
4
GND GND 4
1 2 4 1
CCL9 CCL12
18P_0402_50V8J 18P_0402_50V8J
GCLK@ GCLK@
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/GCLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0