Design Implementation and Test of Novel Quantum-Dot Cellular Au

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Theses and Dissertations
2012
Design, implementation, and test of novel

quantum-dot cellular automata FPGAs for the
beyond CMOS era
Hemant Balijepalli
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Recommended Citation
Balijepalli, Hemant, "Design, implementation, and test of novel quantum-dot cellular automata FPGAs for the beyond CMOS era"
(2012). Theses and Dissertations. 260.
http://utdr.utoledo.edu/theses-dissertations/260
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A Thesis
entitled
Design, Implementation, and Test of Novel Quantum-dot Cellular Automata FPGAs
for the beyond CMOS Era
By
Hemant Balijepalli
Submitted to the Graduate Faculty as partial fulfillment of the requirements for the
Master of Science Degree in Electrical Engineering
Dr. Mohammed Y Niamat, Committee Chair
Dr. Mansoor Alam, Committee Member
Dr. Junghwan Kim, Committee Member
Dr. Patricia R. Komuniecki, Dean

College of Graduate Studies
May 2012
Copyright 2012, Hemant Balijepalli
This document is copyrighted material. Under copyright law, no parts of this document
may be reproduced without the expressed permission of the author
An Abstract of
Design, Implementation, and Test of Novel Quantum-dot Cellular Automata FPGAs
for the beyond CMOS Era
by
Hemant Balijepalli
Submitted to the Graduate Faculty as partial fulfillment of the requirements for

the Master of Science Degree in Electrical Engineering
May 2012
In 1965, Gordon Moore proposed a law which stated that the number of transistors
on a chip approximately doubles every 24 months. In accordance with this law, over the
decades, CMOS technology has been providing the required dimensions for
implementing high speed, high density, and low power VLSI systems. Current studies
project that the miniaturization of these devices will lead to negative outcomes such as
power dissipation and electro-migration failures. This will result in diminishing returns in
switching performance, diffusion barriers, gate depletion, stray capacitances and off-state
leakage. In the past, researchers have focused on investigating alternative technologies at
the nano scale to potentially replace CMOS technology in the future. As such, many
emerging technologies including Single Electron Transistors (SETs), Spin Transistors,
Resonant Tunneling Diodes (RTDs), and Carbon Nano Tubes (CNTs), and Quantum-dot
Cellular Automata (QCA) are being investigated as potential candidates to replace
conventional CMOS technology.
iii
This research deals with the design, implementation and simulation of novel QCA
based Field Programmable Gate Arrays (FPGAs). The research is divided into two
phases. In the first phase, Multiplexers, Configurable Logic Blocks, and the
Programmable Switch Matrices are designed and simulated. A complete FPGA layout is
subsequently presented. In the second phase of the research, the proposed designs are
tested for possible QCA faults such as cell displacement, cell misalignment, cell
omission, cell rotation and stuck at polarization faults.
The proposed QCA designs are compared with earlier research in terms of number of
QCA cells, area, and latency. Our proposed CLB design shows an improvement of 24%
fewer QCA cells, occupies 62% lesser overall area, and has 53% less latency compared to
previous works.
The circuits in this research are designed, implemented and simulated using the QCA
Designer software tool.
iv
This thesis is dedicated to my father Late Dr. B. S. N. Murthy, who is the
inspiration of my life.
Acknowledgements
I would like to thank Dr. Mohammed Niamat for giving me the opportunity to work
under his guidance and leadership. The important suggestions and valuable advices he
provided me with throughout my research are priceless. I would also like to thank Dr.
Niamat for backing me up with financial support during the crucial stages of my research.
I would like to extend my regards to Dr. Mansoor Alam and Dr. Junghwan Kim for
serving as my committee members.
I would like to thank God, for bestowing this blessed opportunity on me. I am
indebted to my mother for the immense love and confidence, which made this research
happen. I would like to thank my brother Saketh and SIL Meghala for trusting in my
ability and encouraging me throughout my Masters. I would like to thank my cousins
Kalyan and Sravanthi who stood be me all the time with their guidance and support.
I take this opportunity to thank my senior Tejas for his valuable time and suggestions.
I also take the pleasure of thanking my dearest friend Rajesh, whose support was
invaluable. I would like to thank Swetha, for the valuable discussions and support during
the difficult stages of the research. Above all, utmost appreciation to my roommates Adi
and Vishwanath for the support and love they gave me throughout my stay in Toledo.
vi
Table of Contents
Abstract ............................................................................................................................. iii
Acknowledgement ............................................................................................................. vi
List of Tables ................................................................................................................... xiv
List of Figures .................................................................................................................. xvi
1. Introduction ................................................................................................................... 1
1.1 Motivation ................................................................................................................. 1
1.2 Research Objectives .................................................................................................. 4
1.3 Organization of the Thesis ........................................................................................ 8
2. Quantum-dot Cellular Automata .............................................................................. 10
2.1 Introduction ............................................................................................................. 10
2.2 QCA Cells ............................................................................................................... 10
2.3 Clocking in QCA .................................................................................................... 13
2.4 QCA Logic Devices ................................................................................................ 17
2.4.1 Binary Wire ...................................................................................................... 17
2.4.2 QCA Inverted Wire .......................................................................................... 18
vii
2.4.3 Inverter Gate .................................................................................................... 19
2.4.4 Majority Voter ................................................................................................. 21
2.6 Cross-Wiring in QCA ............................................................................................. 24
2.6.1 Coplanar Crossover .......................................................................................... 25
2.6.2 Multi-Layer Crossover ..................................................................................... 26
2.7 QCA Implementation .............................................................................................. 28
2.7.1 Metal QCA ....................................................................................................... 28
2.7.2 Molecular QCA ................................................................................................ 32
2.7.3 Magnetic QCA ................................................................................................. 34
3. Design, Implementation and Simulation of Multiplexers in QCA ......................... 38
3.1 Introduction ............................................................................................................. 38
3.2 Design, Modeling and Simulation of QCA Multiplexers ....................................... 39
3.2.1 The (2:1) Multiplexer ....................................................................................... 40
3.2.2 The (4:1) Multiplexer ....................................................................................... 42
3.2.3 The (8:1) Multiplexer ....................................................................................... 45
3.2.4 Latency and Area comparisons with previous research ................................... 49
4. Design, Modeling and Simulation of a Novel Configurable Logic Block in QCA 50
4.1 Introduction ............................................................................................................. 50
4.1.1 Design, Modeling and Simulation of the Address Decoder ............................ 53
viii
4.1.2 Design, Modeling and Simulation of the Memory Array ................................ 58
4.1.3 Design, Modeling and Simulation of Multiplexers.......................................... 60
4.1.4 Design, Modeling and Simulation of the SR flip flop ..................................... 60
4.1.5 Design, Modeling and Simulation of the Look Up Table in QCA .................. 63
4.1.6 Functional verification of the Configurable Logic Block ................................ 67
4.2 Functional verification of multiple CLBs ............................................................... 70
4.3 Four LUT Configurable Logic Block ..................................................................... 75
4.4 Design parameters and analysis of simulation results ............................................ 76
5. Modeling and Design of a Novel Quantum-dot Cellular Automata Switch for
FPGA ................................................................................................................................ 79
5.1 Introduction ............................................................................................................. 79
5.2 Design of QCA Programmable Switch Matrix (QPSM) ........................................ 81
5.2.1 Design and Simulation of a (1x1) QCA Programmable Switch Matrix (1-
QPSM) ...................................................................................................................... 82
5.2.2 Design and Simulation of a (2 x 2) QCA Programmable Switch Matrix (2-
QPSM) ...................................................................................................................... 84
QPSM) ...................................................................................................................... 86
QPSM) ...................................................................................................................... 87
ix
5.2.5 Design and Simulation of QCA Connection Box (QCB) ................................ 88
5.3 Analysis of the Design Parameters of the QPSM ................................................... 94
5.4 The QCA Field Programmable Gate Array ............................................................ 95
6. Testing and Fault Modeling in QCA ......................................................................... 98
6.1 Introduction ............................................................................................................. 98
6.2 Faults in QCA ......................................................................................................... 99
6.2.1 Cell Displacement ............................................................................................ 99
6.2.2 Cell Misalignment ........................................................................................ 100
6.2.3 Cell Omission.............................................................................................. 102
6.2.4 Cell Rotation ............................................................................................... 104
6.2.5 Stuck at Polarization .................................................................................. 105
6.3 Effect of QCA faults on the proposed CLB .......................................................... 108
6.3.1 Cell Omission at the Decoder ........................................................................ 108
6.3.2 Cell Displacement at the Memory cell........................................................... 109
6.3.3 Cell Rotation Fault at the Multiplexer ........................................................... 110
6.3.4 Stuck at Polarization Fault at the Connecting wire ........................................ 112
6.3.5 Cell Misalignment at the SR-flip flop ............................................................ 113
6.4 Effect of the QCA faults associated with the Multiplexers .................................. 114
6.4.1 Cell Omission Faults ...................................................................................... 114
x
6.4.2 Cell Displacement Faults ............................................................................... 115
6.4.3 Cell Rotation Faults ....................................................................................... 116
6.4.4 Stuck At Polarization Faults .......................................................................... 117
6.4.5 Cell Misalignment Faults ............................................................................... 118
6.5 Design For Testability CLB Architecture ............................................................. 119
6.6 Detection and Location of the Faults .................................................................... 121
6.6.1 Pseudo Code for Fault detection in the Proposed CLB ................................ 122
6.6.2 Flowchart for the Fault Detection in the proposed CLB................................ 123
6.6.3 Detection of Faults in the Proposed CLB ...................................................... 124
7. Summary and Conclusion ........................................................................................ 131
7.1 Summary of the research ...................................................................................... 131
7.2 Contributions......................................................................................................... 132
7.3 Future Work .......................................................................................................... 133
References………………………………………………………………………………135
Appendix A ..................................................................................................................... 143
A.1 Adding Objects to the Layout .............................................................................. 143
A.1.1 Creating Cells ................................................................................................ 143
A.1.2 Adding Labels ............................................................................................... 144
A.2 Bus Layout ........................................................................................................... 144
xi
A.3 Clocking ............................................................................................................... 145
A.4 Creating and Importing Blocks ............................................................................ 147
A.4.1 Create Block .................................................................................................. 147
A.4.2 Import Block ................................................................................................. 147
A.5 Managing Layers.................................................................................................. 148
A.5.1 Layer Ordering .............................................................................................. 149
A.5.2 Creating New Layer ...................................................................................... 150
A.6 Other Manipulating Objects ................................................................................. 151
A.6.1 Rotate ............................................................................................................ 151
A.6.2 Alt Style ........................................................................................................ 151
A.6.3 Copy .............................................................................................................. 152
A.6.4 Translate ........................................................................................................ 152
A.6.5 Mirror ............................................................................................................ 153
A.6.6 Pan................................................................................................................. 153
A.7 Cell Functions .................................................................................................. 153
A.8 Exhaustive Verification........................................................................................ 155
A.9 Vector Table ......................................................................................................... 155
A.10 Engine Options ................................................................................................... 157
A.10.1 Number of Samples ..................................................................................... 158
xii
A.10.2 Convergence Tolerance............................................................................... 159
A.10.3 Radius of Effect .......................................................................................... 159
A.10.4 Relative Permittivity ................................................................................... 160
xiii
List of Tables
2.1 Operation of clock phases in QCA…………………………………………………..16
2.2 Input configurations and the corresponding voltages………………………...….…..30
3.1 The outputs of the (2:1) multiplexer after each stage……………………………….41
3.2 The outputs of the (4:1) multiplexer at each stage…………………………………...44
3.3 The outputs of the (8:1) multiplexer at each stage ………………………….............47
3.4 Comparison of the proposed multiplexer with previous designs…………………….49
4.1 Truth table of a (4:16) Decoder……………………………………………………...54
4.2 Truth table of D-Latch……………………………………………………………….58
4.3 Truth table of the SR-flip flop…………………………………………………….....60
4.4 Truth table of function F……………………………………………………………..66
4.5 Truth table of functions ‘F’ and ‘G’………………………………………................70
4.6 Latency comparison of the proposed CLB with [46] and [47]……………………... 77
4.7 Area comparison of the proposed CLB with [46] and [47]……………….................77
xiv
4.8 Metrics of various components of the CLB……………………………………...…..78
5.1 Flow of signals in each block of the QCA layout…………………………………....93
5.2 Number of QCA cells and Area occupied by (n x n) Switch Matrices………………94
xv
List of Figures
1-1 Taxonomy for Emerging Research Information Processing Devices [2]….…………4
2-1 (a) QCA cell representation (b) Cell polarization = +1 (Logic ‘1’) (c) Cell
Polarization = -1 (Logic ‘0’)……………………………………………..........................11
2-2 Bistable cell polarization…………………………………………………………… 12
2-3 Schematic view of clocking in QCA………………………………………………...14
2-4 Information transfer in a clocked QCA binary wire……………………....................15
2-5 Four phases of the QCA clock…………………………………………………….....16
2-6 (a) Binary wire representation (b) QCA layout of binary wire
(c) Binary wire simulation.................................................................................................18
2-7 (a) QCA inverted chain representation (b) QCA layout of inverter chain (c) Inverter
chain representation……………………………………………………….......................19
2-8 (a) QCA inverter representation (b) QCA layout of an inverter gate
(c) Simulation of the inverter gate……………………………………………………….20
xvi
2-9 (a) Inverted wire as a inverter gate (b) QCA layout of the inverter wire as a inverter
(c) Simulation of inverter wire with normal and inverted outputs……………………….21
2-10 (a) QCA Majority Voter representation (b) QCA layout of Majority Voter (c)
Simulation of Majority Voter …………………………………………………………....22
2-11 (a) QCA representation of AND Gate (b) QCA layout of AND Gate
(c) Simulation of AND Gate ……………………………………………...……………..23
2-12 (a) QCA representation of OR Gate (b) QCA layout of OR Gate
(c) Simulation of OR Gate………………………………………………………...……. 24
2-13 Kink energy with distance D and angle θ……………………..................................25
2-14 (a) Layout of the QCA coplanar crossover (b) Simulation of QCA coplanar
crossover………………………………………………………………………………....26
2-15 QCA layout of the Multi-Layer crossover………………………….……….….......27
2-16 Cross-sectional view of multiple layers of the Multi-layer crossover.......................27
2-17 Metal dot QCA cell……………………………………………………....................28
2-18 Schematic diagram of the four dot metal QCA cell………………………...….…..29
2-19 Majority gate designed using metal dot QCA implementation….............................30
2-20 Majority gate converted into metal dot majority gate………………..............….…31
2-21 Schematic and microscopic view of the clocked shift register..................................31
xvii
2-22 Molecular representation of QCA cell………………………………………….…..32
2-23 The Allyl end-groups which act as dots for QCA…………………………....….....33
2-24 Molecular form of QCA cell…………………………………………….……........34
2-25 Magnetic QCA (a)Representation of Logic ‘1’ and Logic ‘0’ (b)Ground state and
Meta stable state of coupled pairs (c) QCA wire using nano Magnets……………...…..35
2-26 Operation of nano wire……………………………………………………….….....36
2-27 Magnetic QCA representation of the Majority Voter……………….…………......36
2-28 Alignment of magnetic dipoles to demonstrate functionality of Majority
Voter……………………………………………………………………………………..37
3-1 (a) Block diagram of (2:1) multiplexer (b) QCA layout of (2:1) multiplexer…….....40
3-2 Simulation of (2:1) multiplexer...................................................................................42
3-3 (a) Block diagram of the (4:1) multiplexer (b) QCA layout of the (4:1)
multiplexer……………………………………………………………………………….43
3-4 Simulation of the (4:1) multiplexer.............................................................................45
3-5 Block diagram of the (8:1) multiplexer……………………………………….…......46
3-6 QCA layout of the (8:1) multiplexer…………………………………………….…..47
3-7 Simulation of the (8:1) multiplexer………………………………………………….48
4-1 Block Diagram of the Proposed CLB………………………...…………….………..52
xviii
4-2 Block Diagram of the (4:16) Decoder……………………………………....……….54
4-3 Schematic diagram of the (4:16) Decoder……………………….………………......55
4-4 QCA Layout of the (4:16) Decoder……………………………………….…………56
4-5 Simulation of the Address Decoder…………………………….................................57
4-6 Schematic diagram of the D-latch…………………………………….…….…...…..58
4-7 QCA layout of the D-Latch…………………………………………….....................59
4-8 Simulation of the D-Latch……………………………………………….…….….... 59
4-9 Schematic of the SR-Flip Flop……………………………………………....………61
4-10 QCA layout of SR Flip-Flop………………………………………………….........61
4-11 Simulation of SR flip flop when SR= “00”……………………..............................62
4-13 Simulation of SR flip flop when SR= “01”………………………………….…… 63
4-15 Block Diagram of the Proposed Look Up Table (LUT)…………………….……...64
4-16 QCA layout of the Look Up Table (LUT)………………………………….…........65
4-17 Simulation result of function ‘F’...............................................................................67
4-18 QCA layout of the proposed CLB…………………………………….....................68
xix
4-19 Simulation of the CLB when SR= “01”…………………………...........................69
4-20 Simulation of the CLB when SR= “10”……………………………………….......69
4-21 Simulation of the CLB when SR= “11”or “00”………………..……….………….70
4-22 Multiple CLB design………………….....................................................................71
4-23 QCA layout showing multiple CLBs …………………………………….……….. 72
4-24 CLB simulation when SR = ‘10’……………………………………………….…..73
4-25 CLB simulation when SR = ‘01’…………………………………………….…..…74
4-26 CLB simulation when SR = ‘00’ or ‘11’………………………………………...…74
4-27 Four LUT Configurable Logic Block……………………………………………....75
4-28 Latency contribution of each components of the CLB …………………...………..76
4-29 Area occupied by each component of the CLB……………………….……………76
5-1 Island type architecture of an FPGA………………………………………….…… 80
5-2 1x1 QCA Programmable Switch Matrix (1- QPSM)………………………………. 82
5-3 Simulation of 1-QPSM................................................................................................83
5-4 Flow of the signals through 1-QPSM by varying the clock……………………........84
5-4 (cont.) Flow of the signals through 1-QPSM by varying the clock.............................84
5-5 (a) QCA layout of 2-QPSM (b) Simulation of 2-QPSM…….....................................85
xx
5-6 Flow of the signals through the 2-QPSM by varying the clock…………….…….…86
5-7 (a) QCA layout of the 3-QPSM (b) Simulation of 3-QPSM……...............................87
5-8 (a) QCA layout of the 4-QPSM (b) Simulation of 4-QPSM………...........................88
5-9 (a) QCA layout of the Vertical QCB (b) Simulation of Vertical QCB.......................90
5-10 (a) QCA layout of the Horizontal QCB (b) Simulation of Horizontal QCB….…... 91
5-11 Layout showing the proposed QCA Programmable Switch Matrices…………...…92
5-12 Simulation of the QCA layout with Switch Matrices………………...….. ………..93
5-13 Island Type FPGA……………………………………………………….…………95
5-14 QCA layout of Field Programmable Gate Array………………………………..….96
5-15 QCA layout of Field Programmable Gate Array with four LUT based
CLBs………………………………………………………………………………..……97
6-1 QCA layout of a Fault-Free MV gate (b) QCA simulation……………….………....99
6-2 (a) QCA layout of a MV gate with a cell displaced by 42nm (b) QCA simulation of
the faulty circuit...............................................................................................................100
6-3 (a) QCA layout of a MV gate with a cell displaced by 72nm (b) QCA simulation of
the faulty circuit…...........................................................................................................100
6-4 (a) QCA layout of a MV gate with a cell misaligned by 9nm (b) QCA simulation of
the faulty circuit…...........................................................................................................101
xxi
6-5 (a) QCA layout of a MV gate with a cell misaligned by 18nm (b) QCA simulation of
the faulty circuit……………………………………………………...…. ……………..101
6-6 (a) QCA layout of a MV gate with input cell misaligned by 18nm (b) QCA
simulation of the faulty circuit………………………………………………...………. 102
6-7 (a) QCA layout of a MV gate with the missing central cell (b) QCA simulation of the
faulty circuit……………………………………..………...……………………………102
6-8 (a) QCA layout of a MV gate with group of missing cells (b) QCA simulation of the
faulty circuit………………………………………………………………………........ 103
6-9 (a) QCA layout of a binary wire with a missing cell (b) QCA simulation of the faulty
circuit…...........................................................................................................................103
6-10 (a) QCA layout of a MV gate with a rotated central cell (b) QCA simulation of the
faulty circuit ………........................................................................................................105
6-11 (a) QCA layout with rotated cells at inputs of a MV gate (b) QCA simulation of the
faulty circuit…………………………………………………………………………….105
6-12 (a) QCA layout of a MV gate with stuck at zero (s@p-1) fault (b) QCA simulation
of the faulty circuit……………………………………………………………………...107
6-13 (a) QCA layout of a MV gate with multiple stuck at zero (s@p-1) faults (b) QCA
simulation of the faulty circuit…………………………………………….....................107
6-14 (a) Majority Voter with stuck at zero (s@p-1) fault at one input and stuck at 1
(s@p+1) fault at other input (b) QCA simulation of the faulty circuit………………....108
xxii
6-15 (a) QCA layout showing cell omission faults at the decoder (b) QCA simulation of
the faulty circuit………………………………………………………...........................109
6-16 (a) QCA layout showing cell displacement fault at the memory cell (b) QCA
simulation of the faulty circuit………………………………………………………….110
6-17 (a) QCA layout showing cell rotation fault at the multiplexer (b) QCA simulation of
the faulty circuit…...………………………………………………..…………………..111
6-18 (a) QCA layout showing stuck at fault at the connecting wire (b) QCA simulation of
the faulty circuit………………………………………………………...........................112
6-19 (a) QCA layout showing cell misalignment fault at the SR- flip flop (b) QCA
simulation of the faulty circuit……………………………………………………….....113
6-20 (a) QCA layout showing cell omission fault in the multiplexer (b) QCA simulation
of the faulty multiplexer…...............................................................................................114
6-21 (a) QCA layout showing cell displacement fault in the multiplexer (b) QCA
simulation of the faulty multiplexer……………………………………………...……. 115
6-22 (a) QCA layout showing cell rotation fault in the multiplexer (b) QCA simulation of
the faulty multiplexers…………………………………...………………………….. ...116
6-23 (a) QCA layout showing the stuck at polarization fault in the multiplexer (b) QCA
simulation of the faulty multiplexer…….……................................................................117
6-24 (a) QCA layout showing the cell misalignment fault in the multiplexer (b) QCA
simulation of the faulty multiplexer…………………………………………….............118
xxiii
6-25 Quadrants of the proposed CLB…………………………….……………….……120
6-26 Possible fault locations of the proposed CLB………………………….................121
6-27 Flowchart for fault detection in the proposed CLB………………………….……123
6-28 Faulty simulation of the CLB due to Stuck at Polarization Fault………….……...124
6-29 Location of stuck at zero (s@p-1) fault in the CLB………………………….…...125
6-30 Faulty simulation of the CLB due to cell omission fault…………………….……125
6-31 Location of cell omission fault in the CLB………………………….....................126
6-32 Faulty simulation of the CLB due to cell displacement fault…………….…….....127
6-33 Location of cell displacement fault in the CLB……………………….…………..128
6-34 Faulty simulation of the CLB due to cell rotation fault………………….……......128
6-35 Location of cell rotation fault in the CLB……………………………….……......129
6-36 Faulty simulation of the CLB due to cell misalignment fault…………….……....130
6-37 Location of the cell misalignment fault in the CLB……………………….…...…130
A-1 Managing Bus Layers…………………………………………………….………..144
A-2 Selection of cells to apply clocking…………………………………................…. 145
A-3 Clock Assignment for Selected Cells……………………………….…………......146
A-4 Clocked Cells……………………………………………………….……………...146
xxiv
A-5 Creating a Block………………………………………………….………………..147
A-6 Importing the blocks………………………………………….……………………148
A-7 Dialog box for Layer Management……………………………….………………..149
A-8 Ordering of the Layers…………………………………………...………….……..149
A-9 Tool Bar for Managing Layers………………………………………....……….....150
A-10 Dialog Box to Create a New Layer…………………………….…………………150
A-11 Toolbar showing other Manipulating Objects………………….…………...……151
A-12 Alternate Styles of QCA cells………………………………….…………………152
A-13 Manipulating Cell Functions………………………………………………....…..154
A-14 Exhaustive Verification Selection..........................................................................155
A-15 Vector Table…………………………………………………………….………..156
A-16 Adding Vectors to the Table…………………………………….……….…….....156
A-17 Editing the Vector Values in the Table……………………………….…………..157
A-18 Bistable Engine Options.........................................................................................158
A-19 Radius of Effect………………………………………………………………......159
xxv
Chapter 1
Introduction
In this chapter, a brief introduction is given regarding the proposed research. Section
1.1 explains the main motivation behind this research. Section 1.2 lists the objectives of
the proposed research and also details the various phases of the current research. Finally,
Section 1.3 illustrates the organization of the thesis by explaining the contents of each
chapter in the thesis.
1.1 Motivation
According to the Moore’s law, the number of transistors on a unit area doubles every
24 months [1]. Over the decades, the exponential scaling of the feature size and increase
in the processing speed has been provided by Complementary Metal Oxide
Semiconductor (CMOS) technology for implementing VLSI systems. CMOS technology
has been providing the required dimensions for implementing high speed, high density
and low power VLSI systems. Though the present generation CMOS is 22nm, many
consequences will arise due to the reduction in the feature size in the future. Few such
consequences are leakage currents, power dissipation, oxide thickness, crosstalk and
electron-migration. The downscaling of the gate oxide thickness increases the field oxide
across the gate resulting to electron tunneling from gate to substrate or from substrate to
1
gate. The resulting current is called gate oxide tunneling current and it is the major
leakage current in the nanometer CMOS. The power dissipation in CMOS involves both
static and dynamic power dissipations. The static power dissipation, caused by the
leakage currents contribute to small percentage of the total power consumption while the
dynamic power consumption results from charging and discharging of parasitic
capacitive loads of interconnects and device dominates the overall power consumption.
Due to scaling of the transistor, the electric fields in the gate oxides are expected to rise
and the reliability of thin oxides becomes a major concern. The above factors arise due to
the scaling of the CMOS technology. Due to this reduction in oxide thickness, the
transistor will not be able to provide sufficient current drive at reduced supply voltages.
Crosstalk arises when the signal transmitted on one circuit or channel of transmission
system causes an undesired effect on another circuit. Electro migration is the result of
momentum transfer from the electrons, which move in the applied electric field, to the
ions which make up the lattice of the interconnect material which cause the interconnect
failures.
The International Technology Roadmap for Semiconductors (ITRS) projects that the
scaling of the CMOS technology will continue till 2019 [2]. Many researchers have
focused on this problem due to the rising demand for denser and faster integrated circuits.
The research on alternative technologies which would supersede CMOS technology in
the future is being carried out from a considerable period of time. Few of the emerging
technologies in the nanometer era which would substitute the conventional CMOS
technology are:
2
 Quantum-dot Cellular Automata (QCA)
 Spin Transistors
 Resonant Tunneling Devices (RTD)
 Single Electron Transistors (SETs)
 Carbon Nanotube Transistors (CNTs)
 Tunneling Phase Logic (TPL)
Figure 1-1 shows the taxonomy for the emerging research information processing
devices. The architecture, representation of the data, device, material used and the
state variables representation of each technology are detailed. The red circles
represent the CMOS technology which is based on the electronic charge as a binary
computational state variable. The green circles represent the other emerging research
information processing devices.
In this thesis, research is carried on Quantum-dot Cellular Automata (QCA)
technology [3]. QCA uses arrays of coupled quantum dots to implement the Boolean
logic functions. The QCA circuits consists of the quantum cells with the quantum
dots and the information is transferred from one cell to the other cell by the moment
of the electrons inside the cells due to the columbic interactions [4]. Unlike the
conventional digital technologies which use range of voltage or current to represent
logic values, in QCA, position of the electrons represents the binary values. Small
size QCA dots, simple interconnections and low power consumption provide the high
packing density for the QCA devices. QCA not only gives a solution to nanoscale, but
it offers a new method of computation and information transformation.
3
Figure 1-1: Taxonomy for Emerging Research Information Processing Devices [2]
1.2 Research Objectives
Field Programmable Gate Arrays (FPGAs) present an attractive application for QCA
technology. Due to their homogeneous structure, FPGAs are appropriate for fabrication at
the nanoscale [5]. We anticipate that in the future, nano FPGAs will find applications in
many areas such as biomedical engineering where miniscule FPGAs embedded in
4
implants such as pacemakers and defibrillators would be remotely reprogrammed. The
other areas of nano FPGA application include telecommunication, medicine, aerospace
and industrial control.
QCA based FPGA components have been designed in the past. The Programmable
logic arrays (PLAs), Configurable Logic Blocks (CLBs), Look Up Tables (LUTs) and
Memory cells have been designed in QCA [6] [7] [8]. In this research, an entire FPGA
slice is designed, modeled and simulated in QCA. The major goal behind designing these
circuits is to take the advantage of QCA logic and concept. The designs in this research
are not the one-one implementations of the CMOS circuits. All the designs are novel,
modular, and optimal and are taking advantage of the QCA logic.
The proposed research is divided into two phases:
Phase-1: Design, Modeling and Simulation of the QCA Multiplexers, QCA
Configurable Logic Block and QCA Programmable Switch Matrix for Nano-FPGAs
In this phase of research, QCA architectures of various components of an FPGA and
the FPGA itself are proposed, designed and simulated using the QCA Designer tool [9].
A. QCA Multiplexers
The QCA cells can be used to implement the logic and the interconnection. Taking
advantage of this feature, QCA multiplexers have been designed and implemented. The
designed multiplexers are modular in design. At the beginning, a (2:1) multiplexer is
5
designed. This multiplexer is used as a building block for designing the higher order
multiplexers such as a (4:1) multiplexer and a (8:1) multiplexers. All the multiplexers are
designed and simulated using the QCA Designer tool. The proposed multiplexers are
compared with the previously designed multiplexers in terms of number of cells, area and
the computational time.
B. QCA Configurable Logic Block
A novel CLB design in QCA is proposed. In CLB, the Look up Table (LUT) contains
the main logic which is processed by the CLB. The LUT consists of address decoder,
memory elements and multiplexers. Each LUT can be configured to implement any
boolean functions. In this research, each of the components of the LUT is individually
designed and simulated and integrated together to form a complete LUT. The LUT
combined with the SR-Flip Flop forms the Configurable Logic Block.
The proposed CLB includes a feature of “Design for Testability (DFT)”. DFT design
is a design that has an ability to test itself which are important in designing an easy fault
detectable device. A detailed analysis of the DFT design of the CLB is discussed and
simulations are explained.
C. QCA Programmable Switch Matrix
The Programmable Switch Matrix forms the major routing element of an FPGA
which is used to switch the signals at the intersection of the interconnect lines. A novel
design for QCA based Switch Matrix is proposed and implemented. The proposed
designs include:
6
 QCA Programmable Switch Matrix (QPSM)
 QCA Connection Box (QCB)
The QPSM is used to switch the signals on the different wires at the intersection of
the vertical and horizontal channels of the FPGA. The (n x n) QPSMs (where n is the
number of inputs of the switch matrix) of different orders starting from n = 1 to n =4 have
been designed and simulated. The QCB is the routing element which connects the
horizontal and vertical channels of the FPGA to the different CLBs. An interconnect
layout with the QPSMs and QCBs is designed and simulated. A detailed analysis of the
proposed architectures of the switch matrices is discussed and the simulations are carried
out. Finally, the QCA Configurable Logic Block and the QCA Programmable Switch
Matrices designed are integrated to design a novel QCA based FPGA slice. All the
designs are simulated using the QCA Designer tool [9].
Phase-2: Testing and Detection of Faults in the Proposed QCA Designs
All the QCA circuits designed in Phase 1 are tested for the following possible QCA cell
faults [10]
 Cell Displacement
 Cell Misalignment
 Cell Omission
 Cell Rotation
 Stuck at Polarization
7
The above faults are inserted in the QCA circuits and the designs are tested for the
detection of the faults through simulations.
1.3 Organization of the Thesis
The thesis is organized as follows:
Chapter 1: This chapter gives the overview of the research.
Chapter 2: This chapter briefly describes the fundamentals and concepts of the QCA
technology, clocking in QCA, basic QCA logic gates and types of QCA devices.
Chapter 3: This chapter explains the design, implementation and simulation of QCA
multiplexers which takes the advantage of the QCA logic. QCA multiplexers of various
orders are designed and simulated. The designed multiplexers are compared in terms of
area, number of QCA cells and the computation time with previously designed
multiplexer circuits.
Chapter 4: In this chapter, a novel design of a Configurable Logic Block in QCA is
proposed and implemented. The various components of the LUT which forms the main
logic of the CLB are designed and simulated. The components include the address
decoder, D-Latch, and the multiplexers. The designed CLB is compared in terms of
number of cells, area occupied and latency with previously developed CLBs.
Chapter 5: This chapter illustrates the design, implementation and the simulations of the
various (n x n) QCA Programmable Switch Matrices (QPSMs). The design of the QCA
Connection Blocks (QCB) is also discussed. The QPSMs and QCBs are integrated into a
single layout consisting of the vertical and horizontal channels to form the complete
8
interconnection circuit of the FPGA. The layout is simulated by taking the inputs from
one of the CLBs and checking the outputs at the other CLBs across the various QPSMs.
A complete FPGA is designed by integrating the CLB designed in Chapter 4 and the
QPSM designed in Chapter 5.
Chapter 6: In this chapter, the QCA circuits designed in this research are tested for
possible QCA defects such as cell displacement, cell misalignment, cell omission, cell
rotation and stuck at polarization. Faults are inserted in the QCA designs and the
simulations are run and the QCA circuits are tested for the fault detection.
Chapter 7: This chapter gives the summary and contribution of the research done in this
thesis. This is followed by a discussion on the future directions.
9
Chapter 2
Quantum-dot Cellular Automata
2.1 Introduction
Introduced by Craig Lent in 1993, Quantum-dot Cellular Automata is one of the
emerging technologies likely to supersede the conventional CMOS technology [4]. QCA
uses arrays of coupled quantum dots to implement boolean logic functions. QCA is the
physical implementation of "classical" cellular automata by exploiting quantum
mechanical phenomena. Conventional digital technologies use range of voltages or
currents to represent logic values wherein in QCA technology, position of the electrons
represents the binary values [11]. The advantages of this technology are [12]:
 High Operating Speed – Range of Terahertz
 Low Power Consumption – 100 W/cm2
 High Device Density – 1012 devices/cm2
2.2 QCA Cells
A standard QCA cell has four quantum dots at the four corners of the square shaped
cell [13]. The research on implementation of six dot and eight dot QCA cells is still in the
beginning stage [14] [15]. In this research, a standard four dot QCA cell is used in
10
generating digital circuits. In these cells, the four dots are coupled by tunnel barriers. The
electrons can tunnel among the dots within the cell.
The high inter-cell potential barrier ensures that the electrons do not tunnel between
the QCA cells. Figure 2-1(a) shows a standard QCA cell with four dots at the corners.
Due to coulombic repulsions, the two electrons in the cells align across the diagonals
resulting in two stable states. These two stable state polarizations represent binary logic 0
and binary logic 1. If the two electrons align in the lower left and upper right dots, it
represents logic ‘1’ state (Figure 2-1 (b)). If the two electrons align in the upper left and
lower right dots, it represents logic ‘0’ state (Figure 2-1 (c)) [16].
(a) (b) (c)

Figure 2-1: (a) QCA cell representation (b) Cell polarization = +1 (Logic ‘1’) (c) Cell
Polarization = -1 (Logic ‘0’)
In QCA cells, the coulombic interaction between the electrons causes highly stable
switching between the two polarization states. If two QCA cells are placed close to each
other, the coulombic interactions between the electrons cause the cells to have the same
polarization. If polarization of one of the cells is changed gradually, the second cell
switches to the same polarization as it exhibits high bistable switching. In Figure 2-2,
cell1 is the driver cell whose polarization (P1) is in the range of -1 to +1. As the
polarization P1 of the cell1 is changed gradually from -1 to +1, the polarization P2 of the
11
cell 2 changes abruptly from -1 to +1. The polarization which is the measure of the
charge distribution along one of two diagonals is given by equation (2.1) [17].
( ) ( )
Polarization (P) = (2.1)
( )
In equation 2.1, ‘ρi’ indicates the charge of the electron at dot ‘i’ where i = 0, 1, 2, 3, 4.
Figure 2-2: Bistable cell polarization [17]
The tunneling junctions between the dots are provided with potential barriers which
are controlled by the local electric field [18]. Based on the position of the potential
barriers, the state of the cell is obtained. If the barriers are lowered, the electrons are free
to move into any of the dots and this state is called the Null state or un-polarized state. If
the barriers are raised up, the electrons align in either of the diagonals entering polarized
states of logic ‘0’ or logic ‘1’. In this way, computation is performed by the QCA cells by
coulombic interaction within the cells and the influence of the driver cell on the
neighboring cells. Basic operation of the QCA cells was discussed in this section and the
next section explains the clocking mechanism of QCA followed by QCA logic gates
12
(QCA wires, Majority Voter and Inverter) and the types of QCA devices (Metal,
Molecular and Magnetic).
2.3 Clocking in QCA
Timing in QCA is achieved by clocking in four distinct periodic phases [18]. It is
required in both combinational and sequential circuits. One major advantage of clocking
in QCA is that the signal lost to the environment is restored by the clock. Depending on
the way the QCA cells are switched, there are two types of switching methods associated
with the operation of QCA.
(a) Abrupt Switching: If the sudden changes in the input changes the state of the entire
circuit bringing it into excited state it is called abrupt switching. As the switching is
abrupt, the QCA circuit has to be relaxed to the ground state by dissipating energy.
The QCA circuit may enter metastable state as the relaxation is uncontrollable.
(b) Adiabatic Switching: In this type of switching, the system is always kept in the
instantaneous ground state. Clock signal is introduced to ensure the adiabatic
switching. This is the most preferred type of switching.
Clocking is an important parameter in QCA design. In QCA, the clock signals are
generated by the CMOS circuitry. The CMOS wires or Carbon Nanotubes (CNTs) buried
under the QCA circuitry produces the electric field with the metal conductor above the
QCA cell layer [18]. This electric field affects the energy levels which affect the
operation of the QCA cells. One such method of clocking proposed by K. Hennessy and
C. S. Lent [19] is shown in Figure 2-3. In this method, QCA cells are spread in the XY
plane and the conducting wires are placed across the Y plane below the layer of QCA
13
cells. Voltage is applied to the conducting wires which produce electric field. The metal
conductor placed above the QCA layer draws the electric field in Z direction. The QCA
cells are affected by the⃗⃗ component of the electric field. The ⃗ do not affect the QCA
cells and the ⃗⃗ component is zero due to symmetry. A phase shift of π/2 radians is
introduced between each of the adjacent wires by applying time variant voltages. This
way every fourth wire will have the same applied signal.
Figure 2-3: Schematic view of clocking in QCA
Information is transferred in a pipelined fashion in QCA [20] [21]. All the cells in a
particular clock zone are in same state and the cells in different clock zones are isolated.
The pipeline transfer of the information is shown in Figure 2-4. The x-axis indicates the
clock zone and the y- axis indicates the height of the potential barriers. In Figure 2-4, a
single QCA wire and the state of the array of cells of the same wire in different clock
zones is shown. The four clock zones of QCA are indicated as Clock 1: Green, Clock 2:
14
Pink, Clock 3: Blue and Clock 4: White. The order of assignment of the clock must be in
the same order to transfer the information.
When the clock is applied to a particular array of cells, all the cells in that array are in
stable state and the rest of the cells are in the ground state. The arrays of cells in the
stable state are shown by the presence of electrons and the arrays of cell in ground state
are only shown by the dots (Figure 2-4).
Figure 2-4: Information transfer in a clocked QCA binary wire
The four distant clock phases of QCA are: Switch, Hold, Release and Relax [11]. The
arrays of cells in each phase have different polarizations based on the position of the
potential barrier. Table 2.1 gives the polarization of the QCA cells for the four phases of
the clock.
15
Table 2.1: Operation of clock phases in QCA
Clock Phase Potential Barrier Polarization State of the Cells
Switch Low to High Polarized

Hold Held High Polarized
Release Lowered Unpolarized
Relax Low Unpolarized
From Table 2.1, during the ‘Switch’ phase of the clock, the un-polarized QCA cell
switches to polarized state depending on the driver cell. The same polarization is
maintained during the ‘Hold’ phase as the potential barriers are held high. In the
‘Release’ phase, the potential barriers are gradually lowered and the cells lose their
polarization. Finally in ‘relax’ phase, the cells become un-polarized as the potential
barriers are completely lowered. At this stage, the cells are ready to switch again. This
way information is transferred in QCA circuits by maintaining the ground state
polarization all the time. Figure 2-5 below illustrates the polarizations of the QCA cells in
each of the QCA clock zones.
Figure 2-5: Four phases of the QCA clock
16
2.4 QCA Logic Devices
Many logic devices can be built by arranging the QCA cells in different ways. The
major advantage of QCA technology is that the cells themselves carry the logic. So, by
arranging the QCA cells in a particular order any logic could be established. To make the
input cell drive the other cells in the array, a very thin wire or the tip of a scanning
tunneling microscope (STM) is used. Plunger Electrode is used in the semiconductor
QCA to drive the input cells [22] [23] [24]. Electrometers made from the ballistic point
contacts [25] [26], STM method [27] and SET electrometers are used to read the outputs
of the QCA circuits. The driver cell (or the input cell) influences the state of other cells in
an array and outputs are read from the electrometers.
The basic QCA logic devices are:
 Binary Wire (Standard cells)
 Inverted Wire ( 45o Rotated cells)
 Inverter
 Majority Voter
In the following sub-sections, the QCA logic gates designed using the QCA cells and the
simulations of the respective gates are illustrated.
2.4.1 Binary Wire
Based on the driver cell or the input cell, all the neighboring cells align themselves to
the particular polarization. So, by arranging the cells side-by-side any logic can be
transferred. Therefore, it could be used as a binary wire or interconnect. The QCA binary
17
wire is shown in Figure 2-6. Clocking is provided to the binary wire so that the signal
strength is not degraded after particular number of cells. Figure 2-6(a) shows the binary
wire representation in QCA, Figure 2-6(b) shows the QCA layout of the binary wire and
Figure 2-6(c) shows the simulation output of the binary wire.
(a)
(b)
(c)
Figure 2-6: (a) Binary wire representation (b) QCA layout of binary wire
(c) Binary wire simulation
2.4.2 QCA Inverted Wire
A QCA inverted wire is similar to the QCA binary wire except that the cells are
o
rotated by 45 in vertical or horizontal orientation. In this wire, every alternate cell has
the same polarization. They carry logic as 0, 1, 0, and 1…..so on. Figure 2-7 shows the
inverter chain representation, QCA layout and the simulation of QCA inverter chain. The
length of the inverter chain depends on which output to be read. If odd numbers of cells
18
are in a chain, the same output as the input is obtained and if the even numbers of cells
are in the chain, then the opposite of the input is obtained at the output.
(a)
(b)
(c)
Figure 2-7: (a) QCA inverted chain representation (b) QCA layout of inverter chain (c)
Inverter chain representation
2.4.3 Inverter Gate
A standard design of the QCA inverter is shown in Figure 2-8. The input ‘In’ is given
at one of the ends and the inverted output ‘Out’ is obtained. The position of electrons in
each cell is shown in Figure 2-8(b). There are many designs of the inverter gates in QCA
but this is the most stable inverter gate used. The input wire splits into two parallel wires
and polarizes the cell placed at the end of these wires on right hand side to the opposite
polarization due to the coulombic repulsions. Figure 2-8(c) shows the simulation result of
the inverter gate. As indicated by the green arrow, the inverter gate produced the inverted
output for a given input.
19
(a)
(b)
(c)
Figure 2-8: QCA inverter representation (b) QCA layout of an inverter gate
(c) Simulation of the inverter gate
An inverted QCA wire could also be used as an inverter. Due to the presence of 45o
rotated cells in the inverter wire, by taking a 90o (non-rotated) cell at the junction of the
input cell and its inverter cell both the original input signal and its complement could be
obtained. As shown in Figure 2-9(a) , placing the standard cell at the halfway between an
even and odd numbered rotated cells ( cell 2 and cell 3) gives the inverted value and by
placing the standard cell at the halfway of odd and even numbered cells ( cell 5 and cell
6) gives the original value. The QCA layout is shown in Figure 2-9(b). The output cells
are Out1 (same polarization as input cell), Out (same polarization of input cell) and
Inv_Out (inverted output of the input cell). Simulation results are shown in Figure 2-9(c).
20
(a)
(b)
(c)
Figure 2-9: (a) Inverted wire as a inverter gate (b) QCA layout of the inverter wire as a
inverter (c) Simulation of inverter wire with normal and inverted outputs
2.4.4 Majority Voter
A Majority Voter (MV) is one of the important logic gates in QCA. The MV gate
gives the majority logic value of its inputs. The logic function the MV implements is MV
(A, B, C) = A.B + B.C+ C.A where A, B and C are the inputs. The MV gate is
implemented using five QCA cells as shown in Figure 2-10 (a). The three input cells
21
affect the cell at the center to polarize it. Based on the majority of the inputs at the central
cell, the central cell polarizes due to coulombic interactions. The center cell is the
decision making cell. The QCA layout is shown in Figure 2-10(b). Simulation output is
shown in Figure 2-10(c). To analyze the operation output of the MV gate, the logic
values of input and output pulses are indicated (red).
(a) (b)
(c)
Figure 2-10: (a) QCA Majority Voter representation (b) QCA layout of Majority Voter
(c) Simulation of Majority Voter
22
From the Majority voter gate, the other logical gates such as AND / OR gates could
be designed. By fixing one of the inputs to 1 or 0, AND gate and OR gate are formed.
The logical function of AND gate and OR gate are:
MV (A, B, C) = A.B when C=0; AND operation
MV (A, B, C) = A+B when C=1; OR operation
Figure 2-11 shows the design, implementation and simulation of AND gate and
Figure 2-12 shows the design, implementation and simulation of OR gate.
(a) (b)
(c)
Figure 2-11: (a) QCA representation of AND Gate (b) QCA layout of AND Gate
(c) Simulation of AND Gate
23
(a) (b)
(c)
Figure 2-12: (a) QCA representation of OR Gate (b) QCA layout of OR Gate
(c) Simulation of OR Gate
2.6 Cross-Wiring in QCA
The Kink energy (Eki, j) is the energy cost of cells ‘i’ and ‘j’ having opposite
polarization. Kink energy is the essential energy required for a successful switching of
the QCA cells. Kink energy in QCA depends on the distance between the respective cells
‘D’ and the angle ‘θ’ [11] shown in Figure 2-13.
The relationship between ‘θ’ and ‘D’ is given by:
( ) ( ) (2.2)
24
Figure 2-13: Kink energy with distance D and angle θ
Kink energy is the energy required to excite the system from the ground state to
excited state. The QCA cells follow quadrupole-quadrupole interaction which decays
inversely to the fifth power of the distance between the cells. Therefore, the kink energy
will decay rapidly with distance, so every QCA cell must have an effective neighbor and
must have capacity to polarize the neighbor cell. This is called the Radius of Effect.
In QCA, there are two types of crossovers
 Coplanar Crossover
 Multi-Layer Crossover
2.6.1 Coplanar Crossover
In QCA, a binary wire crosses the inverted QCA wire without interacting when they
are properly aligned. There is a natural crossover as the energy between the standard cell
and rotated QCA cell cancels out. Therefore, the kink energy is zero. Because the Kink
energy is zero, there is no influence of one QCA cell on the other QCA cell. The QCA
layout and the simulation of the coplanar crossover are shown in Figure 2-14. Wire A is
an inverted QCA wire and wire B is the normal QCA wire. The simulation shows the
25
output from wire A (blue arrow) and the output from the wire B (green arrow) are
obtained without influencing each other due to coplanar crossing.
(a)
(b)
Figure 2-14: (a) Layout of the QCA coplanar crossover (b) Simulation of QCA coplanar
crossover
2.6.2 Multi-Layer Crossover
The Multi-Layer Crossover is considered as a reliable method of crossover in QCA.
The cells are placed in multiple layers so that signals can pass properly in multiple layers
using vertical interconnect [28]. Figure 2-15 shows the multilayer crossover of QCA [29].
Here, the crossover of binary wires A and B is shown. On the top most layers, the cells of
binary wire ‘A’ and a portion of cells of binary wire B are placed. If the binary wire ‘B’
has to cross ‘A’, at the intersection of the wires the cells of wire B must be sent to another
26
layer and transmitted horizontally. Here, the vertical interconnects are used to send the
wire B to the second layer. These vertical interconnects are stacked over each other and
the wire B can cross any number wires lying in the first layer. The ‘Via’ layers are
introduced in between the first and second layers to reduce the interaction between the
cells of the respective layers. One major advantage of this crossover is that it provides
better integration of the circuits. The cross sectional view of the multiple layers of the
multi-layer crossover is shown in Figure 2-16.
Figure 2-15: QCA layout of the Multi-Layer crossover
Figure 2-16: Cross-sectional view of multiple layers of the Multi-layer crossover
27
2.7 QCA Implementation
There are three classes of QCA implementations:
 Metal QCA
 Molecular QCA
 Magnetic QCA
In this Section, experimental implementation of each of the above methods is
discussed.
2.7.1 Metal QCA
The Metal QCA implementation is the first implementation to demonstrate the
working of QCA cells. The method consists of metallic tunnel junctions and very small
capacitors. The device consists of four aluminum islands (dots) connected through
aluminum oxide tunnel junctions and capacitors shown in Figure 2-17. The operating
temperature of the device is determined by the island capacitance which in turn depends
on the area of the tunnel junctions. Dimensions of 1 micrometer metal islands have been
implemented. Due to the large islands, metal island devices are kept at very low
temperatures to observe the quantum effects. The switching of electrons in one cell by the
position of electrons in the other cells has been confirmed through the experiments [30].
Figure 2-17: Metal dot QCA cell
28
The fabrication methods include electron beam lithography (EBL) and dual shadow
evaporation on an oxidized silicon wafer. Figure 2-18 shows the metal island
implementation of the QCA. The aluminum dots are located from ‘D1’ to ‘D4’, coupled
by tunnel junctions [31]. The ‘E1’ and ‘E2’ are single electron tunneling (SET)
electrometers for sensing the device output. The operating temperature of the device is
approximately 70MK [32].
Figure 2-18: Schematic diagram of the four dot metal QCA cell
A majority voter is designed using this implementation (Figure 2-19) by [32]. The
differential signals A, B and C are the inputs to the central cell. The signal A is between
the gates 1 and 3, B is between the gates 1 and 2, and C is between the gates 2 and 4. The
negative (positive) bias on the gate, Ф- (Ф+), mimics the presence (absence) of the
electron in the input dots. The amplitudes of Ф- and Ф+ are chosen to mimic the potential
due to the polarization of an input cell and they always remain small enough so that they
do not change the number of excess electrons in the corresponding cell [33]. The dots D1
29
and D2 are coupled to one gate electrode, voltages corresponding inputs A and B on gate
1, and the inputs B and C on gate 2 are added to mimic the effect of the two input dots.
Figure 2-19: Majority gate designed using metal dot QCA implementation
The Table 2.2 shows the setting of the voltages to attain different input configurations.
In Figure 2-20, the central cell polarizes based on the inputs. With the inputs traced as a
function of time, the electrometers E1 and E2 are used to measure the differential potential
between the dots D4 and D3 (ФD4 – ФD3) [32]. Ease of design and fabrication are the
advantages of the metal QCA devices. The metal dots are of the order of 1μm in
dimension and therefore these devices need to be cooled to low temperatures of 4K for
the observation of electron switching.
Table 2.2: Input configurations and the corresponding voltages
Input Configuration V1 V2 V3 V4
ABC = 000 2ф+ 2ф- Ф- Ф+
ABC = 111 2ф- 2 ф+ Ф+ Ф-
30
Figure 2-20: Majority gate converted into metal dot majority gate
Figure 2-21 shows the shift register implemented using the metal dot QCA
implementation [34].
Figure 2-21: Schematic and microscopic view of the clocked shift register [34]
31
2.7.2 Molecular QCA
Molecular QCA implementation has advantages over the other implementations
because it yields the greater performance and also operates at room temperatures. In
molecular QCA, the cells are structurally homogeneous down to the atomic level. Each
molecule functions as a QCA cell and the redox centers act as QCA dots [35] [36]. The
information is encoded in these dots with charge configuration and the tunneling is
provided by bridging ligands as shown in Figure 2-22 [37]. A single molecule with
charge localized in specific sites where the charge can tunnel through the sites could be
used as a QCA cell. The key strategy here is to use the nonbonding orbitals (π and d) as
the dots.
Figure 2-22: Molecular representation of QCA cell [37]
The mixed-valence compounds which exhibit a unique property of having multiple
redox centers are potentially implemented as the molecular QCA cells. Figure 2-23 gives
an example of a molecule “1, 4- diallyl butane radical cation” [37]. The molecule consists
of two allyl groups connected by the butyl bridge. In molecular cation, one allyl group is
a neutral radical and the other is cationic. The three-carbon π -system in the allyl group
has a doubly occupied bonding level and a nonbonding level which is singly occupied in
the neutral allyl radical and unoccupied in the allyl cation. The unpaired electron can
32
occupy either of the nonbonding levels at the opposite allyl end-groups with little change
to the molecular geometry. This nonbonding character makes the implementation of QCA
dots possible. If the charge is at only one end, the molecule will develop a dipole
moment, which changes sign when the electron tunnels from one end to the other. The
dipole field from one molecule cause the dipole moment of a neighboring molecule to
change its sign making the QCA logic is possible.
Figure 2-23: The Allyl end-groups which act as dots for QCA [37]
The molecules act as natural and uniformly small quantum dots with high density.
These properties make them suitable for operations at room temperature. In molecular
QCA implementation, the required quantum mechanical effects happen at room
temperatures. The molecular QCA is much improved in power, speed, and area. The
formation of mobile chargers by chemical oxidation and reduction are shown in Figure 2-
24.
33
Figure 2-24: Molecular form of QCA cell [37]
In molecular implementation, the power is only needed to drive the inputs and for
clocking mechanism which makes this implementation less power consuming. Few
challenges that this implementation faces is due to the size of the devices, driving the
inputs to a certain state and difficulty in sensing the output. The other cells could be
influenced besides the driver cell and output cells.
2.7.3 Magnetic QCA
The magnetic materials are used for the implementation of QCA devices due to their
simplicity in fabrication, robustness, low power consumption at harsh operating
conditions and their insensitivity to radiation. In magnetic QCA, the basic cell is a
nanomagnet. The magnetic cells are placed in a grid like fashion to accomplish
computing. The nanomagnets have been experimentally verified to operate at room
temperature. It is observed that if 1010 of the Nano magnets switch 108 times each second,
the magnets only dissipate 0.1W of power [38]. A clock structure which generates
external magnetic field drives the computation. Clocking removes the permanent
magnetization from the previous logical operations and allows re-using the magnets for
new logical operations.
Many magnetic thin films, such as perm alloys or cobalt display in-plane
magnetization. This means that the preferred domain orientation is parallel to the plane of
34
the film. Other carefully constructed CoPt multilayers exhibit out-of-plane magnetization.
The coupling of the magnets in these configurations could be used to implement QCA
logic. Figure 2-25 shows how those magnets align in the lower ground state (logic ‘0’)
and higher metastable state (logic ‘1’) and a wire of Nano magnets. These Nano magnets
where first investigated by Cowburn and Welland [39].
Figure 2-25: Magnetic QCA (a)Representation of Logic ‘1’ and Logic ‘0’ (b)Ground
state and Meta stable state of coupled pairs (c) QCA wire using nano Magnets
In magnetic QCA, power gain occurs by the transfer of energy from external clock to
the high internal energy state of the magnets. When magnets are in collinear alignment
with their long axis, the magnetization is in same direction. This state is called Ferro
magnetically arranged state. If the Nano magnets are arranged side by side in parallel it
will result in anti-parallel arrangement of the dipole. This is called anti-Ferro
magnetically ordered state [40]. Figure 2-26 shows the operation of the nanowire and
shows how a Nano wire has relaxed to ground state and has moved a value from one end
35
of the wire to another. The middle wire shows neutral logic where the external field turns
all the magnetic moments of the magnets in horizontal direction. This is the unstable
state. When the external field is removed, the magnets relax themselves to anti-Ferro
magnetically ordered ground state.
Figure 2-26: Operation of nano wire [40]
The magnetization of the output magnet depends on the aligment of the input
nanomagnets. A QCA majority gate can be designed by simple arrangement of five
nanomagnets. A central cell magnetizes based on the surrounding three nanomagnets.
These are called the input drivers.The central cell acts as a output driver. Figure 2-27
shows the magnetic QCA representation of the Majority voter.
Here ABC = 000 and MV(0,0,0) = O.
Figure 2-27: Magnetic QCA representation of the Majority Voter
36
Figure 2-28 shows the outputs of the majority voter for different combinations of the
inputs A, B and C.
Figure 2-28: Alignment of magnetic dipoles to demonstrate functionality of Majority

Voter
37
Chapter 3
Design, Implementation and Simulation of Multiplexers
in QCA
3.1 Introduction
In Field Programmable Gate Arrays (FPGAs), Configurable Logic Blocks (CLBs) are
important elements which can be configured in such a way that they can provide
functionality as complex as a microprocessor. CLBs can be used to implement both
combinational and sequential logic functions. Besides CLB, other major components of
an FPGA are the Input-Output (I/O) Blocks and the Interconnects [41]. The I/O blocks
are programmable and are used to interface the FPGA to the peripherals. The pins can be
programmed as either inputs or outputs. Interconnects provide wiring between the CLBs
and the I/O blocks of an FPGA.
The combinational logic parts of the CLBs are either multiplexers (MUX) or Look up
tables (LUT). The QCA based multiplexers are designed and implemented in QCA that
are novel in design and optimal compared to previous works [42] [43]. QCA multiplexers
designed in this work have the uniqueness compared to previous developed multiplexers
as these are designed with an idea to take the advantage of the QCA technology.
38
In this approach, a (2:1) multiplexer is built by three building blocks namely an
inverter block, AND block and an OR block. Further, this multiplexer is used as a basic
building block for designing the (4:1) multiplexer and the 8:1 multiplexer. The higher
order multiplexers use (n-1) (2:1) multiplexers; where ‘n’ is the number of inputs of the
multiplexer. Therefore, (4:1) multiplexer is designed using three (2:1) multiplexers and
the (8:1) multiplexer is designed using seven (2:1) multiplexers which makes the
multiplexer design modular. In Section 3.2, the proposed design of the multiplexers and
the respective simulations are illustrated. The proposed multiplexers are compared with
the previous designs [42] [43] for optimality in terms of number of cells, area occupied
and latency. The multiplexers are designed and simulated using QCA Designer tool.
3.2 Design, Modeling and Simulation of QCA Multiplexers
Recent works in the area of QCA multiplexers is described in [42] and [43]. Work
done in [42] is based on two dimensional clocking schemes and work done in [43] is
based on developing modular designs for the multiplexers. In the current research, novel
multiplexer designs that take the advantage of QCA logic [4] are developed. Some of the
advantages implemented in proposed designs are: a) Use of QCA inverted wires instead
of QCA inverter gate which requires less number of cells compared to the QCA inverter
gate, and b) Use of a single driver cell for AND/OR gates wherever possible which
reduces the number of driver cells and also the number of inputs to the QCA circuit. In
this work, these advantages could be noticed in every design.
39
3.2.1 The (2:1) Multiplexer
In the proposed research, the (2:1) multiplexer is designed in three stages: inverter
stage, AND stage and the OR stage as shown in Figure 3-1(a). In the figure, the inputs are
shown as A, B and the select line as S0. The inputs and outputs from each of the blocks
are also indicated. At stage 1, a QCA inverter wire is used which gives out the select line
output (S0) and the inverted select line output (S0’). At Stage 2, these select line outputs
are ANDed with the inputs A and B of the multiplexer. Finally, in Stage 3, the previously
ANDed outputs are ORed to get the output of the multiplexer. The QCA layout of the
(2:1) multiplexer is shown in Figure 3-1(b).
(a) (b)
Figure 3-1: (a) Block diagram of (2:1) multiplexer (b) QCA layout of (2:1)
multiplexer
40
The outputs at each stage of the multiplexer are tabulated in Table 3.1.
Table 3.1: The outputs of the (2:1) multiplexer after each stage
Stage Outputs
Inverter Stage S0 and S0’
AND Stage AS0 , BS0’
OR Stage AS0 + BS0’
The advantage of the QCA logic is taken at the first stage where the select line S0 and
the inverted select S0’ are taken from a QCA inverted wire. It is noted that by placing a
standard cell and aligning it halfway between an even and an odd numbered rotated cell
produces an inverted signal, and a standard cell placed halfway between an odd and even
numbered cell produces a buffered value. This tapping of signal from an inverted wire is
useful while implementing large circuits where crossover of wires in the same plane is
essential. Here, the use of a QCA inverter gate can be avoided which uses more cells. The
second advantage of QCA is taken at the second stage where a common fixed driver cell
with polarization -1.00 is taken for two different AND gates. This avoids using multiple
driver cells for the multiple AND gates.
The circuit is designed and tested for functional behavior using the QCA Designer
tool. The proposed design consists of 39 cells covering an area of 0.07µm2 and a grid
area of 12 x 11 grids. The simulation results of the (2:1) multiplexer are presented in
Figure 3-2. Two waveforms with different frequencies are applied at the inputs A and B,
and the multiplexer outputs the signal at A when the select signal S is low (represented by
a green arrow) and outputs the signal at B when select signal S is high (represented by a
41
blue arrow). In Figure 3-2, the dotted red circle represents the latency of the multiplexer
which is found to be one clock cycle.
Figure 3-2: Simulation of (2:1) multiplexer
The importance of using the building blocks is to maintain the uniformity in the
design. This concept eases the design process and also increases the manufacturability of
the QCA circuit. The (2:1) multiplexer designed could be used as a building block to
design multiplexers of any size which make the designs modular.
Using the (2:1) multiplexer as a building block, a (4:1) multiplexer is designed and
implemented. Figure 3-3(a) shows the design of a (4:1) multiplexer using three (2:1)
multiplexers. Here, S0 and S1 represent the select lines of the multiplexer. A, B, C and D
are the inputs of the multiplexer. The outputs at the end of each stage of the multiplexer
are also indicated. The QCA implementation of the multiplexer is shown in Figure 3-
3(b).
42
(a)
(b)
Figure 3-3: (a) Block diagram of the (4:1) multiplexer (b) QCA layout of the (4:1)
multiplexer
43
Table 3.2 shows the outputs after each stage of the (2:1) multiplexer used in
designing the (4:1) multiplexer.
Table 3.2: The outputs of the (4:1) multiplexer at each stage
Multiplexer 1 Multiplexer 2 Multiplexer 3

Stage
Output Output Output
Inverter S0 and S0’ S0 and S0’ S1 and S1’

Stage
AND Stage AS0, BS0’ CS0 , DS0’ (AS0 + BS0’) S1 , (CS0 + DS0’ )S1’
OR Stage AS0 + BS0’ CS0 + DS0’ (AS0 + BS0’) S1 + (CS0 + DS0’ )S1’
In general, the number of (2:1) multiplexers required to design any higher order
multiplexers is “n-1”, where ‘n’ is the number of inputs of the multiplexer. In this case,
we are designing a four input multiplexer and therefore, we require three (2:1)
multiplexers. According to the QCA Designer, the circuit contains 153 cells covering an
area of 0.22 µm2 and a grid area of 21 x 25 grids. The simulation result of the (4:1)
multiplexer is shown in Figure 3-4. The inputs are A, B, C, D and the selection lines are
S0 and S1. Based on the Selection inputs S0 and S1, the multiplexer produces the output
from the respective four inputs. The colored arrows represent the outputs of the different
inputs of the (4:1) multiplexer.
44
Figure 3-4: Simulation of the (4:1) multiplexer
An (8:1) multiplexer is designed using seven (2:1) multiplexers. The basic block
diagram of the (8:1) multiplexer is as shown in Figure 3-5. Here, A to H are the inputs of
the multiplexer and S0, S1 and S2 are the select lines of the multiplexer. The outputs are
also indicated at the end of each (2:1) multiplexer.
45
Figure 3-5: Block diagram of the (8:1) multiplexer
The QCA implementation of the (8:1) multiplexer is shown in Figure 3-6. The circuit
implemented consists of 387 cells covering an area of 0.59 µm2 and a grid area of 31x45
grids. Figure 3-7 shows the simulation results of the (8:1) multiplexer. The orange box
represents the simulation outputs of each input from the multiplexer. The clocking is
given based on the position of the 2 to 1 multiplexer on the inverter wires S0, S1 and S2.
Table 3.3 shows the outputs at each stage of the (2:1) multiplexer.
46
Figure 3-6: QCA layout of the (8:1) multiplexer
Table 3.3: The outputs of the (8:1) multiplexer at each stage
47
48
Figure 3-7: Simulation of the (8:1) multiplexer
3.2.4 Latency and Area comparisons with previous research
Latency is the number of clock cycles after which the circuit produces an output. In
Table 3.4, the proposed design of the (8:1) multiplexer is compared with previously
developed (8:1) multiplexers in [42] [43] in terms of the number of cells, area occupied
and the latency. The proposed design of the multiplexer occupies 387 cells which is 39%
less than the multiplexer proposed in [42] and 33% less than the multiplexer proposed in
[43]. The proposed multiplexer occupies an area of 0.59µm2 which is 12% less than the
area occupied in [42] and 28% less than the area occupied in [43]. The covered area in
grids is 29 x 45 grids or 1305 grids and is 22% less than the number of grids in [42] and
36% less than the grids occupied by [43]. In the proposed design, the latency of the
output signal related to the inputs is 4 clock cycles which is 63% less than the latency of
[42] and 55% less than the latency of [43].
Table 3.4: Comparison of the proposed multiplexer with previous designs
Designs Designs Proposed

Characteristics proposed in proposed in Design
[42] [43]
No. of cells 576 633 387
Covered Area (grids) 2052 1690 1305
Estimated area by QCA

0.82 0.67 0.59
Designer tool(µm2)
Computation time
9 11 4
(No of Clock Cycles)
49
Chapter 4
Design, Modeling and Simulation of a Novel
Configurable Logic Block in QCA
4.1 Introduction
A Field Programmable Gate Array (FPGA) consists of Configurable Logic Blocks
(CLBs), configurable input/output (I/O) blocks and interconnection networks. The CLBs
are the important elements which can be configured in such a way that they can provide
functionality as complex as that of a microprocessor. The CLBs can be used to
implement both combinational and sequential logic functions by using logic gates and
flip-flops having the configurable topology. The combinatorial logic functions are
typically implemented in look-up tables (LUTs). The multiplexers are also used to
implement logic functions and they direct signal routing within the CLB. The I/O blocks
provide bidirectional communication between the FPGA and the peripherals of the
system. The interconnection networks provide the wiring among the CLBs, I/O blocks
and other elements of an FPGA.
In the past, research has been carried out in designing QCA based Configurable Logic
Blocks of an FPGA. The CLB of the Xilinx FPGA architecture and the Altera FPGA
architecture were designed and implemented in QCA [44] [45]. Chia Chung Tung and
50
others [45] have designed a LUT-based CLB in QCA and have also implemented the
multiple CLB application. Timothy Lantz and others [47] have designed a QCA based
CLB structure with four LUTs and have simulated them successfully. In this research, a
novel CLB structure in QCA is proposed which takes advantage of the unique features of
QCA logic. The proposed CLB also includes Design for Testability (DFT) features. DFT
assures easy detection of the faults in the circuit and also reduces the cost and time
associated with test development. The proposed DFT scheme is detailed in Chapter 6.
The logic in a CLB is mapped in the Look up Table. The LUT consists of an address
decoder, memory elements, and multiplexers. Each LUT can be configured to implement
boolean functions. The basic block diagram of the proposed CLB is shown in Figure 4-1.
In the proposed research, a 4-input LUT is designed and implemented. The LUT consists
of a (4:16) address decoder at the center with four input lines A, B, C and D and
addresses sixteen memory locations. The multiplexers are used to select the contents of
one of the sixteen memory cells. The input lines are connected to the select lines of the
various multiplexers in the LUT.
51
Figure 4-1: Block Diagram of the Proposed CLB
The decoder in Figure 4-1 has four inputs and sixteen outputs. These 16 outputs from
the decoder are used to address any of the sixteen memory cells (M0-M15). Four (4:1)
multiplexers are used to select one output among the four outputs at each of the branches
of the decoder where inputs C (green wire) and D (red wire) are the select lines for these
52
multiplexers. Two (2:1) multiplexers are used at the top and the bottom to select one of
the outputs coming from the branches where input B (blue wire) is the select line for
these multiplexers. Another (2:1) multiplexer with input A (purple wire) as the select
line, is used for generating the final output of the CLB through an SR-flip flop. Each
component shown in the block of Figure 4-1 is designed and simulated individually and
finally integrated to form the CLB slice.
The next section deals with the design and simulation of various components of the
LUT in QCA followed by the design of a complete layout of the LUT.
4.1.1 Design, Modeling and Simulation of the Address Decoder
A four input address decoder is designed to enable the selection of any of the sixteen
memory locations based on the inputs of the decoder. In Figure 4-2 , a block diagram of
the decoder is shown where A, B, C and D are the input lines to the decoder and O1-O15
are the outputs of the decoder. Without one-to-one mapping from the CMOS circuit, this
decoder is designed to take the advantage of the QCA logic. To avoid QCA inverter
gates, the designs are implemented using QCA inverted wires instead. The original value
and inverted value are taken from the wire by placing the cells at half the distance
between two inverted cells. Table 4.1 represents the truth table of a (4:16) decoder where
the decoder gives sixteen unique outputs based upon the input combinations as indicated
by the orange boxes.
53
Figure 4-2: Block Diagram of the (4:16) Decoder
Table 4.1: Truth table of a (4:16) Decoder
54
The schematic diagram of the address decoder is shown in Figure 4-3. The grey lines
are the inverted QCA wires and the purple lines are the normal QCA wires. Starting with
inputs A, B, C, and D, the signals flow into the inverted QCA lines in vertically up and
vertically down directions. By using the inverted QCA lines, normal and inverted outputs
are taken from these wires. The Majority Voter gates are configured as AND gates by
fixing one of the inputs to zero. Therefore, for each combination of the input, the decoder
gives sixteen outputs (O0-O15), which are used to address sixteen memory locations of the
Look up Table. As an example, for the input combination ABCD= ‘0000’, the decoder
activates the output O0 (green digit). The rest of the outputs are inactive (red digit).
Figure 4-3: Schematic diagram of the (4:16) Decoder
55
The QCA layout of the Address Decoder is as shown in Figure 4-4. The simulation
output of the decoder is shown in Figure 4-5, where the orange box at the bottom of the
figure represents the outputs of the decoder for each input combination. The decoder
produces output after a latency of 5 clock cycles (represented by red dotted circle).
Figure 4-4: QCA Layout of the (4:16) Decoder
56
Figure 4-5: Simulation of the Address Decoder
57
4.1.2 Design, Modeling and Simulation of the Memory Array
The decoder outputs sixteen unique addresses and each address is used in addressing
a memory location of the LUT. These memory locations are used to store expected values
of the Boolean functions which describe the system. The storage elements are used to
store the value of the truth table. A D-Latch is designed as a storage element. The D-latch
has a data line, enable signal line and an output line. Table 4.2 represents the truth table
of the D-latch. The schematic diagram of the latch using the MV logic is shown in Figure
4-6. The QCA layout is shown in Figure 4-7 followed by simulation results in Figure 4-8.
Table 4.2: Truth table of the D-latch
Enable Data Q
0 X Latch
1 0 0
1 1 1
Figure 4-6: Schematic diagram of the D-latch
58
Figure 4-7: QCA layout of the D-Latch
Figure 4-8: Simulation of the D-Latch
From the simulation, it is observed that there is a delay of one clock cycle. The delay
is indicated by a red dotted circle in the figure. The red arrow indicates how the D-latch
outputs the previous value when enable input is zero and the blue arrow indicates how the
D-latch outputs the input value ‘D’ when the enable input is one.
59
4.1.3 Design, Modeling and Simulation of Multiplexers
In the proposed design of the Configurable Logic Block, the multiplexers are used to
select one of the contents of the sixteen memory cells. To avoid the use of long wires
which cause delay, the multiplexer and address decoder use common address lines. In the
designs proposed in this research the (2:1) multiplexer and (4:1) multiplexer are used at
various positions in the circuit to output the values of the memory elements depending on
the select line inputs. The QCA implementation and simulations of the multiplexers have
been discussed in Chapter 3.
4.1.4 Design, Modeling and Simulation of the SR flip flop
The SR-flip flop is used in the CLB to store the value of the output of the Look up
Table and provide a clocked output. Table 4.3 shows the truth table of the SR-flip flop.
The schematic diagram of the SR-flip flop using the Majority Voter gates is shown in
Figure 4-9 and the QCA layout is shown in Figure 4-10.
Table 4.3: Truth table of the SR-flip flop
Enable S R D Q
0 0 0 X Latch
0 1 1 X Latch
X 0 1 X 0
X 1 0 X 1
1 0 0 D D
1 1 1 D D
60
Figure 4-9: Schematic of the SR-Flip Flop
Figure 4-10: QCA layout of SR Flip-Flop
The simulation results of the SR flip flop for different combinations of the set and
reset are shown in Figures 4-11 to 4-14. The simulation results show a latency of two
clock cycles as indicated by the red dotted circle. When SR= “00”, the arrow in red
shows the output when the enable E=0, where the flip flop acts as a latch. The blue arrow
61
shows the output when enable E=1, and the data (D) is at the output. When SR= “11”, the
arrow in red shows the output when enable E=0, where the flip flop acts as a latch. The
arrow in blue indicates the output when enable E=1, where the data (D) is at the output.
When SR= “01”, the output of the flip flop is set to 1 thus verifying the set operation.
Finally, when SR=”10”, the output of the flip flop is reset to 0 verifying the reset
operation. The SR flip flop is successfully simulated and the functional operation is
verified.
Figure 4-11: Simulation of SR flip flop when SR= “00”
62
4.1.5 Design, Modeling and Simulation of the Look Up Table in QCA
The QCA function generators are implemented using a 4-input LUT. A single LUT
can implement any four literal Boolean functions. To implement any four input equation,
the truth table is programmed into the LUT. Different components of the LUT
63
implemented in the previous sections are integrated to form the LUT. Figure 4-15 shows
the block diagram of LUT with the decoder, memory cells and the multiplexer. To
incorporate Design for Testability (DFT) features, the complex large circuit is subdivided
into individual small components so that observability and controllability can be easily
achieved. The QCA layout of the LUT is as shown in Figure 4-16.
Figure 4-15: Block Diagram of the Proposed Look Up Table (LUT)
64
Figure 4-16: QCA layout of the Look Up Table (LUT)
To evaluate the functionality of the LUT, a function described by equation (4.1) is
implemented
( ) ̅̅ ̅ ̅̅ ̅ ̅ ̅̅ ̅̅ ̅ (4.1)
The truth table for the function described in equation (4.1) is shown in Table 4.4.
65
Table 4.4: Truth table of function F
A B C D F(A,B,C,D)
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
The Look up Table designed in Figure 4-16 is simulated using the QCA Designer
tool. The functionality of the LUT is verified by comparing the simulated output with the
expected results shown in the truth table of the Table 4.4. As shown in Figure 4-17, the
output is obtained after 13 clock cycles delay, i.e., the latency of the design is 13 clock
cycles which is represented by the red dotted box. The orange box at the bottom of the
figure corresponds with the output of the function in Table 4.4 thus verifying the correct
66
operation of the device. We have simulated the LUT for various other functions to
confirm the functional behavior of the LUT.
Figure 4-17: Simulation result of function ‘F’.
4.1.6 Functional verification of the Configurable Logic Block
As discussed in Section 4.1, the proposed QCA Configurable Logic Block mainly
comprises of the LUT and the SR-flip flop. The LUT is used to process logic in the CLB
and the flip flop is used to store the output. The LUT and the flip flop designed and
simulated individually in Sections 4.1.4 and 4.1.5 are integrated to form the CLB as
shown in the block diagram in Figure 4-1 previously. The physical QCA layout of the
CLB is shown in Figure 4-18.
67
Figure 4-18: QCA layout of the proposed CLB
To verify the operation of the CLB, the function described in equation (4.1) is
implemented and simulated for different combinations of the set (S) and reset (R) inputs
of the flip flops. For different combinations of the R and S, the operation of the CLB is
68
verified for the expected output of the CLB. When SR=01, the output of the CLB is high
verifying the set operation (Figure 4-19).
Figure 4-19: Simulation of the CLB when SR= “01”
When SR=10, the output of the CLB is low verifying the reset operation (Figure 4-20).
Figure 4-20: Simulation of the CLB when SR= “10”
69
When SR=00 and 11, the CLB outputs the respective output of the function F after a
latency of 14 clock cycles.
Figure 4-21: Simulation of the CLB when SR= “11”or “00”
4.2 Functional verification of multiple CLBs
Two functions F and G decribed in equation (4.2) and equation (4.3) are implemented
using the multiple blocks of the proposed CLB. In this implementation, two CLBs are
used where one gives the output of function F and the other CLB gives the output of
function G.
( ) ( )
( ) ( )
Table 4.5 shows the truth table of the functions F and G.
Table 4.5: Truth table of functions ‘F’ and ‘G’
70
A B C D F G
0 0 0 0 0 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 1
1 0 0 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 1 1
1 1 0 0 0 1
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1
The block diagram of the integration of the CLBs to implement functions F and G is
shown in Figure 4-22. Here, two CLBs take the inputs (A,B,C,D) from the center and
produces the respective outputs of the function F (F out) and the function G (G out).
Figure 4-22: Multiple CLB design.
Figure 4-23 shows the QCA layout of the multiple CLB implementations. The
proposed CLB is simulated using the QCA Designer software version 2.0.3 [23]. The
radius of effect is 65 nm. The total sample ranges from 12,800 to 25,000 depending on
71
the component of the circuit tested. The default values provided by the QCA Designer are
used for the other parameters like relative permittivity, convergence tolerance, clock
amplitude factor, layer separation and maximum iterations per sample. Simulations
confirm the working of the multiple CLBs by comparing the simulation output with the
values of the F and G from Table 4.5.
Figure 4-23: QCA layout showing multiple CLBs implementation.
The SR-flip flop is used to store the values of the output. The proposed multiple CLB
design is simulated for various combinations of set(S) and reset (R) inputs. The
simulation results show a latency of 14 clock cycles as indicated by red dotted circle.
72
When SR = ‘01’, the outputs from the CLBs are both zeros verifying the reset operation
(Figure 4-24). When SR = ‘10’, the outputs from the CLBs are high verifying the set
operation (Figure 4-25). When SR= ‘00’ or ‘11’, the outputs of the function F and
function G are obtained. In Figure 4-26, the values in the orange box below the
simulation verifies that the CLBs produce the expected output of the function F and the
green box shows that the CLBs produce the expected output of the function G as shown
in Table 4.5.
Figure 4-24: CLB simulation when SR = ‘10’
73
Figure 4-25: CLB simulation when SR = ‘01’
Figure 4-26: CLB simulation when SR = ‘00’ or ‘11’
74
4.3 Four LUT Configurable Logic Block
As the proposed CLB is modular in design, any number of CLBs could be integrated
based on the application. To compare the work done in this research with the previously
developed CLBs consisting of 4-LUTs designed [46] [47], four of the proposed LUTs
designed in Section 4.1.5 are integrated into one CLB. Figure 4-27 shows the QCA
layout of the CLB consisting of four Look up Tables.
Figure 4-27: Four LUT Configurable Logic Block
75
4.4 Design parameters and analysis of simulation results
Latency is the number of clock cycles a design takes to produce the output. Each
component in the proposed CLB contributes to the latency of the entire CLB. The latency
and the area contribution of each of the components of the CLB are shown in Figure 4-28
and Figure 4-29. The overall latency of the proposed CLB is 14 clock cycles.
Figure 4-28: Latency contribution of each components of the CLB
Figure 4-29: Area occupied by each component of the CLB
The proposed CLB in Figure 4-27 occupies 20,767 cells, and the area occupied is 36
µm2. Table 4.6 provides the latency comparisons of CLB, LUT and routing wires of the
76
proposed CLB with [46] and [47]. From Table 4.6, the latency of the proposed design is
53% less than the latency in [46]. Table 4.7 provides the area comparison of the proposed
CLB with [46] and [47]. From Table 4.7, the area occupied by the proposed CLB is 62%
less than the area occupied by the CLB in [46].
Table 4.6: Latency comparison of the proposed CLB with [46] and [47]
Latency (in Clock Cycles) LUT Routing CLB
Read Latency of [46] 11 19 30
Read Latency of [47] 9 7 16
Read Latency of Proposed CLB 10 3 14
Write Latency of [46] 30 NA 134
Write Latency of [47] 9 NA 19
Write Latency of the Proposed CLB 10 NA 14
Table 4.7: Area comparison of the proposed CLB with [46] and [47]
Number of QCA cells Area occupied by the

CLB Type
of the CLB CLB (µm2)
CLB of [46] 27,265 94.0
CLB of [47] 22,558 48.0
Proposed CLB 20,767 36.0
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The design parameters of the various sub components of the proposed CLB are
tabulated in Table 4.8.
Table 4.8: Metrics of various components of the CLB
Module Number Area Latency Contribution Contribution

of Cells (µm2) (Clock to Overall to Overall
Cycles) Area (%) Latency (%)
Decoder 1805 2.75 5 31.6 31.25
D-Latches 640 0.96 1 11.0 6.25
(2:1) Multiplexers 120 0.35 1 4.0 6.25
(4:1) Multiplexers 648 0.98 2 11.2 12.5
Flip Flops 102 0.36 1 4.1 6.25
Connecting wires 1636 3.28 6 37.7 37.5
CLB 4951 8.68 16 - -
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Chapter 5
Modeling and Design of a Novel Quantum-dot Cellular
Automata Switch for FPGA
5.1 Introduction
Field Programmable Gate Arrays are arrays of logic blocks (cells) placed in an
infrastructure of interconnections, which can be programmed at the logic cells, at the
interconnection between the cells and at the input and outputs [48]. The FPGAs are
versatile and programmable at the hardware levels which provide users wide range of
device choices and options. The major elements of an FPGA are the configurable logic
blocks (CLBs), Programmable Switch Matrix (PSM) and Input and Output blocks
(IOBs). The CLB is a basic block implementing digital logic in an FPGA. The
configurable logic blocks can be configured to perform basic logic functions on digital
systems using Look Up Tables (LUTs).
The CLBs are interconnected through Programmable switch matrices (PSM) to form
the units which can perform complex functions. The I/O blocks provide programmable
I/O connections and support for various I/O standards. Many commercially available
FPGAs use Island-style architectures (Figure 5-1) in which logic blocks are organized in
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an array separated by horizontal and vertical routing channels. The CLBs connect the
horizontal and vertical lines using a connection block (C block) and the signals are
switched at the intersection of horizontal and vertical channels by a Programmable
Switch Matrix (PSM block) [48] as shown in Figure 5-1.
Figure 5-1: Island type architecture of an FPGA
In an FPGA, the Programmable Switch Matrix is present at the intersection of
horizontal and vertical routing channels. The switch matrix establishes a communication
between all the elements of an FPGA. It also provides connection between different
CLBs and IOBs. This switch is used to make all the required connections among various
logic blocks and required connections to the inputs and outputs. In this research, novel
QCA based PSM of various sizes (n x n) and the connection blocks of different
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alignments (horizontal/vertical) have been designed and simulated using the QCA
Designer tool.
5.2 Design of QCA Programmable Switch Matrix (QPSM)
In the past, Niemer and others [49] have proposed the design for FPGA logic block
and interconnects in QCA. Niemer explained that there is no possibility to create
equivalent pass transistors using the QCA devices. They have defined un-clocked zones
where the cells remain un-polarized and the cells could remain un-clocked by fixing their
barrier potential to a certain value or by keeping them in the release phase. Niemer
designed routing elements of various sizes using the un-clocking concept. Based on a
similar idea, Andrej and others have proposed a basic universal crossing element in QCA
[50] which can be used as a substitute for the PSM in the FPGA structure. They have
designed the circuits by keeping a single cell or a specific region of cells un-clocked.
Using the concept of setting the cells of a particular region in the release phase of the
clock so that they remain un-polarized, a novel design for a Programmable Switch Matrix
of an FPGA is proposed in this work and simulations are carried out using the QCA
Designer tool [9]. The QCA programmable switch matrices (QPSM) of different sizes
starting from (1x1) QPSM to (4x4) QPSM have been designed and simulated
successfully. Size of the switch matrix is defined by the number inputs and outputs of the
switch matrix.
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5.2.1 Design and Simulation of a (1x1) QCA Programmable Switch Matrix (1-
QPSM)
The routing in the switch matrix is accomplished by using the clock by selectively
turning off a group of cells or by keeping them in the release phase. As the QCA
Designer tool does not support unclocking, the proposed switch matrices are designed by
keeping the cells in the release phase. The (1 x 1) QCA programmable switch matrix (1
– QPSM) can take one input from each side. In the proposed switch matrix, the vertical
wire is the QCA inverted wire and the horizontal is a normal QCA wire. There is a
crossover at the junction of the wires. These two wires are connected by placing a normal
cell at half way of the rotated cells of the vertical wire and connecting it to the normal
QCA cell horizontal wire. This connection wire is named the QCA Connector. For the
signals to flow on the respective individual wires, the connector cells must be in the
release phase so that they do not affect either of the wires. For the signals to flow from
one wire to the other, respective clocking must be given to the QCA connector. In Figure
5-2, the connector is in the release state so that the inputs In1 and In2 appear at the
outputs Out1 and Out2 respectively.
Figure 5-2: 1x1 QCA Programmable Switch Matrix (1- QPSM)
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The simulation results of the 1-QPSM are shown in Figure 5-3. From the simulation,
it can be seen that In1 is outputted at the output Out1(blue arrow) and In2 is outputted at
the output Out2 (green arrow).
Figure 5-3: Simulation of 1-QPSM

Similarly, by changing the clock phases of the QCA Connector the signals can be
transferred in various directions. The direction of the signal can be switched in different
directions through the 1-QPSM by selectively changing the clock phase of the QCA
Connector as shown in Figure 5-4. Here, the green color represents the switch phase, red
represents the hold phase, blue represents the release phase and the grey represents the
relax phase of the clock.
(a) (b)
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Figure 5-4: Flow of the signals through 1-QPSM by varying the clock
(b) (d)
(e) (f)
Figure 5-4 (cont.): Flow of the signals through 1-QPSM by varying the clock
QPSM)
Based on the 1-QPSM, a two input QCA Programmable Switch Matrix (2 –QPSM)
can be built. The 2- QPSM is shown in Figure 5-5(a). The simulation results are shown in
Figure 5-5(b). Here, the cells labeled In1-In4 are the input cells and the cells labeled
Out1-Out4 are the respective outputs. The QCA Connectors are in the release phase, so
the crossover occurs at the intersection of vertical and horizontal wires.
84
(a)
(b)
Figure 5-5: (a) QCA layout of 2-QPSM (b) Simulation of 2-QPSM
85
By setting the state of the QCA Connector to different clock phases the signal can be
transferred in various directions as shown in Figure 5-6.
Figure 5-6: Flow of the signals through the 2-QPSM by varying the clock
QPSM)
A three input QCA Programmable Switch Matrix (3-QPSM) is shown in Figure 5-
7(a). The simulation results are shown in Figure 5-7(b). Here, the input cells are In1-In3
and Out1-Out3, Out11-Out33, Out111-Out333 are the respective outputs in the vertically
down, vertically up and horizontal directions. The QCA Connectors shown in blue are in
the release state and the other connectors are clocked accordingly for the signal to move
in vertically up and down directions.
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The signal starting at input In1 flows to the vertical channel through the QCA
connector to give Out11 and clocking is provided in such a way that the signal flows in
the vertically down direction giving out Out1. At the same time, the signal flows in the
horizontal direction giving out Out111 without affecting the other vertical lines by
keeping the other QCA connectors in the release phase of the clock.
(a) (b)
Figure 5-7: (a) QCA layout of the 3-QPSM (b) Simulation of 3-QPSM
QPSM)
A four input QCA Programmable Switch Matrix (4-QPSM) is shown in Figure 5-
8(a). The input cells are In1-In4 and Out1-Out4, Out11-Out44, Out111-Out444 are the
respective outputs in the vertically down, vertically up and horizontal directions. The
QCA connectors shown in blue are in the release state and the other connectors are
clocked so that the signals can move in either up and down directions. Figure 5-8(b)
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shows the simulation results of the 4-QPSM where arrows represent outputs of the switch
matrix for the respective inputs.
(a) (b)
Figure 5-8: (a) QCA layout of the 4-QPSM (b) Simulation of 4-QPSM
It should be noted that the QPSM proposed in this work are modular in design which
means the same 1-QPSM can be used as a building block for the higher order QPSMs of
any size.
5.2.5 Design and Simulation of QCA Connection Box (QCB)
In an FPGA, the connection box connects the horizontal and vertical channels to the
configurable logic blocks. The signals from the vertical and horizontal channels are
transferred to and from the CLBs through the connection box. These connection boxes
also connect the channel wires to the input and output pins of the CLB. In this chapter,
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two types of QCBs are designed where one connects the vertical channels of an FPGA to
the CLB (vertical QCB) and the other connects the horizontal channels of an FPGA to the
CLB (horizontal QCB). The QCA layout of the vertical QCB is shown in Figure 5-9(a).
The simulation result of the vertical QCB is shown in Figure 5-9 (b).
(a)
(b)
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Figure 5-9: (a) QCA layout of the Vertical QCB (b) Simulation of Vertical QCB
By horizontally aligning the vertical QCB, the horizontal QCB can be obtained. The
QCA layout of the horizontal QCB is shown in Figure 5-10(a). The simulation result of
the horizontal QCB is shown in Figure 5-10 (b).
(a)
(b)
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Figure 5-10: (a) QCA layout of the Horizontal QCB (b) Simulation of Horizontal QCB
The signals can be transferred from the vertical channels or horizontal channels to the
configurable logic blocks though the QCBs by clocking the QCA connector of the
respective wire and the rest of the QCA connectors could be left un-clocked by setting
the connector cells in the release state of the clock. The QCBs of various sizes can be
designed and implemented. The above designs are for the four way QCA connection box.
A layout consisting of the designed QCA Programmable Switch Matrices and the
QCA connection boxes has been designed and simulated. Figure 5-11 shows the
complete layout of the routing structure of the Island type FPGA in QCA. In the layout,
PSM1-PSM4 represents the four input QCA programmable switch matrix (4-QPSM) and
C1-C4 represent the QCA connection boxes (4- QCB). In this layout, the input signals
from CLB0 are transferred through the connection boxes and the switch matrices in
various directions. The outputs are taken after each of the connection boxes and switch
matrices in the layout and simulated.
91
Figure 5-11: Layout showing the proposed QCA Programmable Switch Matrices
(Blue arrows – Inputs and Orange arrows – Outputs)
92
The flow of signal through each of the blocks of the layout is listed in Table 5.1. The
simulation result of the layout is shown in Figure 5-12.
Table 5.1: Flow of signals in each block of the QCA layout
Figure 5-12: Simulation of the QCA layout with Switch Matrices
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5.3 Analysis of the Design Parameters of the QPSM
In this chapter, a QPSM of any size ‘n’, the number of cells occupied by the switch
matrix and the area occupied are enumerated. The number of cells occupied by the
QPSM and the area occupied by the QPSM are given by equations (5.1) and (5.2),
respectively.
Number of QCA cells occupied by n-QPSM = 4n (3n +1) cells (5.1)
n(n+1)-1
Area occupied by n-QPSM = (µm2) (5.2)
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Table 5.2: Number of QCA cells and Area occupied by (n x n) Switch Matrices
Size of the Number of QCA ( 1)-1

Switch Matrix cells Area = (µm2)
100
(n) = 4 n(3n+1) cells
1 16 0.01
2 56 0.06
3 120 0.11
4 208 0.19
5 320 0.29
6 456 0.41
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5.4 The QCA Field Programmable Gate Array
In this section, the designs of the Configurable Logic Block (CLB) and the
Programmable Switch Matrix (PSM) are integrated to form an FPGA. Figure 5-13 shows
the Island type architecture of an FPGA. In this figure, the CLB represents the
Configurable Logic Block and the PSM represents the Programmable Switch Matrix. As
the CLB designed in the proposed research is a 4 input CLB, the (4x4) PSM is used as
interconnect. The inputs are given from the I/O blocks to the PSM. If the same inputs are
to be given to two different CLBs, the routing of the inputs to the CLBs using the PSMs
is shown in Figure 5-13. Figure 5-14 shows the QCA layout of an FPGA and Figure 5-15
shows the QCA layout of an FPGA with four LUT based Configurable Logic Block.
Figure 5-13: Island Type FPGA
95
96
Figure 5-14: QCA layout of Field Programmable Gate Array
97
Figure 5-15: QCA layout of Field Programmable Gate Array with four LUT based CLBs
Figure 5-16:
Chapter 6
Testing and Fault Modeling in QCA
6.1 Introduction
In QCA, the logic states are represented by the position of electrons in QCA cells.
The electrons in a particular cell align themselves based on the driver cell (input cell) and
the neighboring cells take the polarization of the driver cell. A misalignment in the
positions of the cells can introduce faults in the QCA circuit. Hence, the QCA cells
should be aligned precisely at nanoscales for proper functioning of the device.
While improvising fault models for QCA circuits, manufacturing defects and
fabrication errors should be investigated for the proper working of the QCA circuits.
Testing techniques for testing QCA circuits are needed to eliminate defective QCA
circuits.
This chapter discusses the possible QCA faults that may occur in QCA cells and the
effects of these faults on the QCA circuits. Section 6.2 discusses the possible QCA faults.
Section 6.3 deals with the effect of these faults on the various QCA circuits designed in
this research. The behaviors of the CLB and multiplexers due to these faults are analyzed
in Section 6.4. Section 6.5 details the Design for Testability feature of the configurable
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logic block designed in the Chapter 5. A pseudo code is written and a flowchart is
proposed for the location and detection of the faults.
6.2 Faults in QCA
The manufacturing of the QCA circuits consists of two phases- synthesis phase and
the deposition phase. In the synthesis phase, the defects may be caused due to imperfect
cells. These imperfect cells may have missing electrons, cells with extra dots and cells
that have electrons fixed in one configuration. The defects are more likely to occur in the
deposition part than in synthesis part which will result in cell misplacement [10].
The QCA Majority Voter (MV) is taken as an example and various faults are inserted
in this circuit to check how each fault effects the operation of the QCA circuits. Figure 6-
1 shows the fault free QCA Majority Voter and its simulation. The red dotted circle in the
figure indicates the one clock cycle delay of the Majority Voter.
(a) (b)
Figure 6-1: QCA layout of a Fault-Free MV gate (b) QCA simulation
6.2.1 Cell Displacement
A cell displacement fault occurs when a defective cell is displaced from its original
position. The radius of effect is the maximum distance between two QCA cells where
each cell can have an effect on each other. This parameter is set to 65nm in our
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simulations. If the displaced cell is within the 65nm radius, the MV works as a fault free
gate. In Figure 6-2 (a), an input cell C is displaced by 42nm. The corresponding
simulations are shown in Figure 6-2(b) and are found to be functionally correct. If the cell
is displaced by 72nm, which is beyond the radius of effect, the gate no longer functions
as a MV gate as shown in Figure 6-3.
(a) (b)
Figure 6-2: (a) QCA layout of a MV gate with a cell displaced by 42nm (b) QCA
simulation of the faulty circuit
(a) (b)
Figure 6-3: (a) QCA layout of a MV gate with a cell displaced by 72nm (b) QCA
6.2.2 Cell Misalignment
The cell misalignment fault occurs when the direction of the defective cell is
misplaced from its original direction. If a cell is misaligned from its original position by
9nm, the misalignment has no effect on the gate output as shown in Figure 6-4. Similarly,
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if a cell is misaligned by 18nm, it shows the similar output as a fault free majority voter
as shown in Figure 6-5. If the driver cell itself is misplaced by 18nm from its original
position, the input gets inverted and faulty output is obtained. As shown in Figure 6-6, as
the input A is misaligned the inversion of the input A reaches the central cell and the
majority of B, C and inverted A is obtained at the output.
(a) (b)
Figure 6-4: (a) QCA layout of a MV gate with a cell misaligned by 9nm (b) QCA
(a) (b)
Figure 6-5: (a) QCA layout of a MV gate with a cell misaligned by 18nm (b) QCA
101
(a) (b)
Figure 6-6: (a) QCA layout of a MV gate with input cell misaligned by 18nm (b)
QCA simulation of the faulty circuit
6.2.3 Cell Omission
The cell omission fault is a fault where the particular cell is missing in the design. In
Figure 6-7(a), if the decision making cell which is the cell at the intersection of the three
inputs of the majority gate is missing, the logic function of the majority voter which is
supposed to be Z (A, B, C) = A. B + B.C + C. A changes to Z (A, B, C) = A.C’ + A. B’
considering A has a stronger polarization compared to the other two inputs. This is
verified from the simulation shown in Figure 6-7(b).
(a) (b)
Figure 6-7: (a) QCA layout of a MV gate with the missing central cell (b) QCA
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A case where multiple cells are missing in the MV gate is shown in Figure 6-8(a).
The gate has three cells missing after the central cell and the output cell is outside the
radius of effect of the central cell. Therefore, the output obtained has a zero polarization.
The simulation is as shown in Figure 6-8(b).
(a) (b)
Figure 6-8: (a) QCA layout of a MV gate with group of missing cells (b) QCA
If cell is omitted in a binary wire in the configuration shown in Figure 6-9(a), the
signal gets inverted at the intersection and the output obtained is the inversion of the
input. The simulation result is shown in Figure 6-9(b).
103
(a) (b)
Figure 6-9: (a) QCA layout of a binary wire with a missing cell (b) QCA simulation
of the faulty circuit
6.2.4 Cell Rotation
In the QCA inverter wire, the QCA cells are rotated by 450. A cell rotation faults is
likely to occur as a manufacturing defect if at least one of the cells in a binary wire or an
inverted wire is rotated by 450. In Figure 6-10(a), the central cell where the computation
occurs in the MV is rotated by 450 which gives the logic function of the Majority Voter
which is supposed to be Z (A, B, C) = A. B + B.C + C. A as Z (A, B, C) = A.C’ + A. B’,
considering A has a stronger polarization compared to the other two inputs. It is observed
that the output is same as the output when the central cell is missing.
104
(a) (b)
Figure 6-10: (a) QCA layout of a MV gate with a rotated central cell (b) QCA
In a majority voter gate, if the cells at two of the inputs are rotated by 450, the
output is same as the third input which has no cell rotation fault. As shown in Figure 6-
11, the output is Z=C.
(a)
(b)
Figure 6-11: (a) QCA layout with rotated cells at inputs of a MV gate (b) QCA
6.2.5 Stuck at Polarization
The manufacturing process of the QCA cells is still in its development stages. It is
necessary to consider possible defects that might occur in the QCA cells. In QCA, the
alignment of the electrons in the QCA cells represents the logic 0 and logic 1. If the cell
105
has a polarization of -1, it represents logic 0 state and if the cell has a polarization +1, it
represents logic 1 state. The polarization of a particular cell depends on the polarization
of the driver/ input cell or its neighboring cell. The manufacturing faults might lead to the
state where the cells polarization does not change with respect to its neighboring cell or
its driver cell. We call this fault as the stuck at polarization (s@p) fault. A particular cell
could be stuck at polarization -1 (s@p-1) or stuck at polarization +1 (s@p+1). If one of
the inputs is stuck at a polarization (s@p-1), the Majority Voter behaves as an AND gate
as shown in Figure 6-12.
Similarly, if one of the inputs is stuck at polarization +1 (s@p+1), then the Majority
Voter behaves as an OR gate.
(a) (b)
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Figure 6-12: (a) QCA layout of a MV gate with stuck at zero (s@p-1) fault (b) QCA
If any two inputs of the majority voter are stuck at the polarization -1 (s@p-1), then
the output of the majority gate is always majority of the inputs which is logic 0. The
design and simulation are shown in Figure 6-13. Similarly, if any two inputs are s@p+1,
then the output of the MV gate is always logic 1.
(a) (b)
Figure 6-13: (a) QCA layout of a MV gate with multiple stuck at zero (s@p-1) faults
(b) QCA simulation of the faulty circuit
If any two inputs of the MV gate are s@p-1 and s@p+1, then the output is the third
input of the MV gate. The QCA layout and the simulations are shown in Figure 6-14.
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(a)
(b)
Figure 6-14: (a) Majority Voter with stuck at zero (s@p-1) fault at one input and
stuck at 1 (s@p+1) fault at other input (b) QCA simulation of the faulty circuit
6.3 Effect of QCA faults on the proposed CLB
The various QCA faults discussed in Section 6.2 are inserted in the proposed CLB
and simulated to study the effect of these faults on the CLB output. The Configurable
Logic Block designed in this research has the feature of Design for Testability (DFT).
DFT design of the circuit means that the circuit includes testability features within the
circuit itself. This avoids the need for extra test circuit within the design. The DFT design
makes the fault detection easier and faster. The DFT feature is discussed in Section 6.5.
In the proposed design of the CLB, the faults are likely to occur at five places: 1)
Decoder, 2) Memory Cell, 3) Multiplexer, 4) Connecting Wires and 5) SR Flip-Flop.
Each of the five different QCA faults discussed in the previous section is inserted at these
five different positions of the CLB.
6.3.1 Cell Omission at the Decoder
In the proposed CLB, to study the effect of the missing cells on the circuit output few
of the cells are omitted in the decoder as shown in Figure 6-15(a). Due to missing cells,
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the signals from the input A do not reach the top branches of the decoder. The simulation
is carried out and Figure 6-15(b) shows the result of the simulation. The fault in the
simulation is represented by the red dotted box. The function as discussed in Chapter 5 is
implemented on the CLB. Due to the cell omission fault, the CLB gives a faulty output.
The fault can be detected at the top part of the decoder because of the incorrect output in
the dotted red box.
(a)
(b)
Figure 6-15: (a) QCA layout showing cell omission faults at the decoder (b) QCA
6.3.2 Cell Displacement at the Memory cell
A cell in the proposed CLB is displaced at the memory cell as shown in Figure 6-
16(a). Due to this fault, the CLB gives an incorrect output. The simulation result is
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shown in Figure 6-16(b). The faulty output is represented by the dotted red box. The
fault can be diagnosed at memory cell (M0) because the simulations show a faulty
output at the first bit which is written by memory cell M0. Similarly, faults at other
memory cells can be detected by observing the simulation output.
(a)
(b)
Figure 6-16: (a) QCA layout showing cell displacement fault at the memory cell (b)
6.3.3 Cell Rotation Fault at the Multiplexer
The proposed CLB has four (4:1) multiplexers at the four branches. If a fault occurs
at any of the four multiplexers, a faulty output is obtained at the output of the multiplexer.
110
To check how the cell rotation faults effect the CLB, a cell rotation faults is inserted at
the select line of the top right multiplexer of the proposed CLB as shown in Figure 6-
17(a). The dotted red circle in Figure 6-17(a) shows the cell rotation fault where the two
cells in the QCA inverted wire remain as normal QCA cells. As a result, the select lines
become faulty causing the multiplexer output to be faulty. In the simulation, the red
dotted box shows the faulty output (Figure 6-17(b)). It can be concluded that the faulty
output lies in the top part of the CLB and in the right multiplexer.
(a)
(b)
Figure 6-17: (a) QCA layout showing cell rotation fault at the multiplexer (b) QCA
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6.3.4 Stuck at Polarization Fault at the Connecting wire
A stuck at polarization fault is inserted at one of the connecting wires of the proposed
CLB. As shown in Figure 6-18(a), a stuck at zero (s@p-1) fault is inserted at the select
lines of the upper (2:1) multiplexer. The select line outputs one of its inputs twice as the
select line is stuck at one of the polarizations. From the simulation results shown in
Figure 6-18(b), the same output is repeated twice (red dotted box) due to the fault in the
select lines of the upper (2:1) multiplexer. If the output is repeated twice, then the fault
can be detected as a fault in the select lines of the multiplexer.
(a)
(b)
Figure 6-18: (a) QCA layout showing stuck at fault at the connecting wire (b) QCA
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6.3.5 Cell Misalignment at the SR-flip flop
In the SR-flip flop of the proposed CLB, a cell misalignment fault is inserted at the
input cell R. The input cell is misaligned as shown in Figure 6-19(a). As a result of this,
the output of the flip flop gives an incorrect output. If SR=11, the CLB outputs the output
from the Look Up Table. Due the fault at the R input, the flip flop sets to one as shown in
Figure 6-19(b). Due to the unexpected set operation, the fault could be detected at the
SR-flip flop.
(a)
(b)
Figure 6-19: (a) QCA layout showing cell misalignment fault at the SR- flip flop (b)
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6.4 Effect of the QCA faults associated with the Multiplexers
This section describes how the proposed (4:1) multiplexer is tested inserting different
faults mentioned in Section 6.2.
6.4.1 Cell Omission Faults
Figure 6-20(a) shows a (4:1) multiplexer where some of the cells are omitted. The
dotted red circle shows the missing cells. In the simulation results shown in Figure 6-
20(b), incorrect outputs are represented by the red dotted box. The expected outputs are
the inputs A followed by B. But due to the missing cells, the multiplexer outputs a zero.
The incorrect outputs are followed by the correct outputs of C and D (green lines). From
the simulation, the faults can be detected.
(a)
(b)
Figure 6-20: (a) QCA layout showing cell omission fault in the multiplexer (b) QCA
simulation of the faulty multiplexer
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6.4.2 Cell Displacement Faults
If a cell is displaced as shown in Figure 6-21(a) (dotted red circle) in the (4:1)
multiplexer, the outputs from the inputs A and B become inverted. Figure 6-21(b) shows
the simulation output. The inverted outputs of A and B are shown in the simulations
represented by green lines. This type of fault can be detected by observing the simulation
output which gives inverted outputs.
(a)
(b)
Figure 6-21: (a) QCA layout showing cell displacement fault in the multiplexer (b)
QCA simulation of the faulty multiplexer
115
6.4.3 Cell Rotation Faults
If some of the cells in the inverted QCA chain remain as normal cells, the cell
rotation fault occurs. The cell rotation fault is inserted at the select line S1 as shown in
Figure 6-22(a). From the simulation results shown in Figure 6-22(b), select line S1 holds
a single value and the same output is repeated twice (red dotted box) indicating the fault
at the select line of the multiplexer. Due to this fault, the multiplexer outputs C and D
values (green lines) twice.
(a)
(b)
Figure 6-22: (a) QCA layout showing cell rotation fault in the multiplexer (b) QCA
simulation of the faulty multiplexers
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6.4.4 Stuck At Polarization Faults
If a stuck at zero (s@p-1) fault is inserted at the select line of the multiplexer as
shown in Figure 6-23(a), the multiplexer outputs one of the inputs twice as the select line
holds a single value. Due to s@p-1, the inputs C and D are repeated twice at the output
(Figure 6-23(b)). Similarly, if a stuck at one (s@p+1) fault occurs at the select lines of the
multiplexer, the inputs A and B are outputted twice detecting the s@p+1 fault.
(a)
(b)
Figure 6-23: (a) QCA layout showing the stuck at polarization fault in the multiplexer
(b) QCA simulation of the faulty multiplexer
117
6.4.5 Cell Misalignment Faults
The input cell S1 is misaligned from its original position leading to the cell
misalignment fault. Figure 6-24(a) shows the cell misalignment in the multiplexer and the
simulation results are shown in Figure 6-24(b).
(a)
(b)
Figure 6-24: (a) QCA layout showing the cell misalignment fault in the multiplexer
(b) QCA simulation of the faulty multiplexer
118
6.5 Design For Testability CLB Architecture
The CLB architecture proposed in this research is a Design for Testability (DFT)
architecture. The DFT feature is the ability of the circuit to include the testing circuit
within itself [51]. This avoids the need for extra test circuit in the design. Testability
requires that the circuit should be both controllable and observable. DFT assures easy
detection of the faults in the circuit and also reduces the cost and time associated with test
development.
The CLB design has the following advantages:
 Simple
 Ease to Design
 Modular
 Feature of Design For Testability
To explain the DFT feature of the proposed CLB, the entire CLB is divided into four
quadrants as shown in Figure 6-25. The cause of the faulty output could be due to the
fault in any of these quadrants. The CLB is designed in such a way that any fault is easily
detectable.
119
Figure 6-25: Quadrants of the proposed CLB
If the CLB outputs a faulty output, the incorrect output is either from the upper
quadrants (Q1 and Q2) or from the lower quadrants (Q3 and Q4). By observation, if the
fault is from the upper quadrants, the area to check for the fault is reduced by two
quadrants. Now, if the fault is proved to be from the upper quadrants, then by checking
the inputs of the upper (2:1) multiplexer, the test could be reduced by one more quadrant.
Finally, one quadrant is left to check for the fault which makes the fault detection easy
and faster.
This concept is explained from the QCA layout shown in Figure 6-26. If the CLB
gives a faulty output (black cross), it is either due to the fault from the upper quadrants
120
(green cross), bottom quadrants (Red Cross), or the select line (orange cross). From
Figure 6-26, it is seen that if the fault lies in the upper quadrants, the green crosses show
the possible position of the faults in the layout in the upper quadrants. Similarly, the red
crosses show the possible position of the faults in the layout in the lower quadrants.
Figure 6-26: Possible fault locations of the proposed CLB
6.6 Detection and Location of the Faults
This section deals with the location and detection of the faults in the proposed CLB
design. A pseudo code is written for the detection of the fault in Section 6.6.1 and Section
6.6.2 illustrates the flowchart for the detection of the faults. In Section 6.6.3, the faults in
the proposed CLB are detected following the steps in the flowchart.
121
6.6.1 Pseudo Code for Fault detection in the Proposed CLB
Initialize Expected Output, Actual Output, Fault, Faultcause;

Actual Output = Output of the CLB; //Simulate the Configurable Logic Block
If (Actual Output ≠ Expected Output)
{
Then Fault exists; //The output of the CLB is coming from the central (2:1) Multiplexer
If (Fault = Central Mux) // At Central (2:1) Multiplexer

{
Fault exists in three wires;
Switch (Fault)
{
Case (Fault = “Sc”): Central select line is faulty; // Sc is select of central
Case (Fault = ‘Ac”): Upper quadrants are faulty; //Ac upper input central
Case (Fault = “Bc”): Lower quadrants are faulty; //Bc lower input of central
}
}
If (Faultcause = Ac) // At Upper (2:1) Multiplexer

{
Then Fault exists in three wires;
Switch (Fault)
{
Case (Fault = “Su”): Upper select line is faulty; // Su is select of upper mux
Case (Fault = “Au”): Quadrant 1 is faulty; //Au right input of upper mux
Case (Fault = “Bu”): Quadrant 2 is faulty; //Bu left input of upper mux
}
Else If (Faultcause = Bc) // At Lower (2:1) Multiplexer

{
Then Fault exists in three wires;
Switch (Fault)
{
Case (Fault = “Sl”): Lower select line is faulty; // Sl is select of lower mux
Case (Fault = ‘Al”): Quadrant 3 is faulty; //Al right side input of lower mux
Case (Fault = “Bl”): Quadrant 4 is faulty; //Bl lower side input of lower mux
}
}
Else
{
No fault exists;
}
}
122
6.6.2 Flowchart for the Fault Detection in the proposed CLB
Figure 6-27 shows the flowchart for the fault detection in the proposed CLB.
Figure 6-27: Flowchart for fault detection in the proposed CLB
123
6.6.3 Detection of Faults in the Proposed CLB
a) Detection of the Stuck at Polarization Fault
Stuck at Polarization faults can be detected by checking the simulation output as
shown in Figure 6-28. In the figure, the orange box shows the expected outputs, and the
black box shows the actual outputs. The red digits in the black box represent the faulty
outputs.
Figure 6-28: Faulty simulation of the CLB due to Stuck at Polarization Fault
The faulty output from the simulation is noticed (red dotted box) which are in red
color in the black box. It is concluded that the faulty output is from the top two quadrants
because the first eight outputs are faulty. At this stage, it is sure that the faulty output is
from top two branches reducing the area of testing to half. Now, the (2:1) multiplexer is
checked for the output. The fault can be on the input wires to the multiplexer or the select
line input. From the simulation, the first four bits are fault free. The fault is either on the
quadrant 2 or the select line. At this point, the detection for the fault is almost reduced to
one quadrant. By observation, the output of the first quadrant is repeating twice. This can
happen if the select line holds a single value and do not switch. The multiplexer outputs
the signal from quadrant 1 if the select line is zero and it outputs the signals from
124
quadrant 2 if the select line is one. In this case, it outputs only signals from branch one
twice and do not switch to one. Hence, stuck at zero fault (s@p-1) is detected at the select
line as shown in Figure 6-29.
Figure 6-29: Location of stuck at zero (s@p-1) fault in the CLB

b) Detection of Cell Omission Faults
A cell omission fault is detected by checking the simulation output shown in Figure
6-30. The orange box shows the expected outputs and the black box shows the actual
outputs.
Figure 6-30: Faulty simulation of the CLB due to cell omission fault
125
color in the black box. It can be concluded that the faulty output is from the upper
quadrants because the second four bits are faulty. At this stage, it is sure that the faulty
output is from top two quadrants reducing the area of testing to almost half. The upper
(2:1) multiplexer is checked for the output. The fault can be on the input wires to the
multiplexer or the select line input. From the simulation, the fault is not on the select line,
as the multiplexer do not give the same input as the output twice. The fault is also not in
the quadrant 1.The fault is in the quadrant 2. As the first bit of the quadrant 2 is faulty,
the multiplexer, memory cell, and decoder are checked. The fault is due the missing cells
of the decoder in the quadrant 2 as shown in Figure 6-31.
Figure 6-31: Location of cell omission fault in the CLB
126
c) Detection of Cell Displacement Faults
The cell displacement fault is detected by checking the simulation output shown in
Figure 6-32. The orange box shows the expected outputs and the black box shows the
actual outputs.
Figure 6-32: Faulty simulation of the CLB due to cell displacement fault
color in the black box. It is concluded that the faulty output is from the upper quadrants
because the first output bit is faulty. At this stage, it is sure that the faulty output is from
top two quadrants reducing the area of testing to almost half. The upper (2:1) multiplexer
is checked for the output. As the faulty output is due to the first bit, the fault is in the
quadrant 1. The multiplexer, memory cell and decoder are checked. The fault is due the
displacement in the cells of the memory in the quadrant 1 as shown in Figure 6-33.
127
Figure 6-33: Location of cell displacement fault in the CLB
d) Detection of Cell Rotation Faults
The cell rotation fault is detected by checking the simulation output shown in Figure
6-34. The orange box shows the expected outputs and the black box shows the obtained
outputs.
Figure 6-34: Faulty simulation of the CLB due to cell rotation fault
128
color in the black box. It is concluded that the faulty output is from the upper quadrants
because the first four output bits are faulty. At this stage, it is sure that the faulty output
quadrant 1. The multiplexer is checked. As the first two output bits are faulty, there is a
possibility of the fault being on the select line of the multiplexer. The fault is detected as
the cell rotation fault on the select line of the (4:1) multiplexer in the quadrant 1 as shown
in Figure 6-35.
Figure 6-35: Location of cell rotation fault in the CLB
129
e) Detection of Cell Misalignment Faults
The cell misalignment fault is detected by checking the simulation output shown in
Figure 6-36.
Figure 6-36: Faulty simulation of the CLB due to cell misalignment fault
From the simulation, it can be noticed the all the output bits are set to 1. So, the fault
could be at the SR-Flip Flop of the proposed CLB. The SR- Flip Flop has performed the
set operation without setting the SR to 01. So, the fault could be on the input wires R and
S. The fault is detected as due to cell misalignment of the input cell R as shown in Figure
6-37.
Figure 6-37: Location of the cell misalignment fault in the CLB
130
Chapter 7
Summary and Conclusion
This chapter details the summary and contributions of the proposed research.
7.1 Summary of the research
In this work, QCA circuits are designed taking advantage of the QCA logic. The
QCA based designs of multiplexers, Configurable Logic Blocks (CLB), Programmable
Switch Matrix (PSM), and Field Programmable Gate Arrays (FPGAs) are proposed,
designed, and simulated. All the designs are novel, modular, and optimal compared to the
previous work in this area.
In general, FPGAs can be programmed by reconfiguring the programmable logic and
the programmable interconnects. In this work, the QCA based PSMs which form the
programmable interconnects of the FPGA and the QCA based CLBs which form the
programmable logic part of the FPGA are first designed and simulated individually. The
proposed CLBs and the PSMs are then integrated together to form a complete FPGA
layout.
The optimality of the proposed circuits is measured by comparing the number of
cells, area occupied, and the latency with earlier research in this area. It is found that the
131
proposed multiplexer (8:1) contains 39% less number of cells compared to multiplexer
proposed by [42] and 32% less number of cells compared to [43]. The proposed
multiplexer occupies 12% less area compared to [42] and 28% less area compared to
[43]. The latency of the proposed multiplexer is 63% less than the latency in [42] and
53% less than the latency in [43]. The designed CLB contains 24% less number of cells
compared to [46] and 8% less number of cells compared to [47]. The proposed CLB
occupies 62% less area than [46] and also occupies 25% less area than [47]. The latency
of the proposed CLB is 53% less than the latency in [46] and 27% less than the latency in
[47].
In the final phase of the research, the designs of the proposed research are tested for
various QCA defects and faults. Different faults are inserted in the circuits and the
simulations are run to study the variation in output of the circuit due to a particular fault.
Design For Testability (DFT) features are introduced in the CLB circuit. DFT design is a
design which makes the circuit easily testable. The CLB is tested for various faults to
confirm the DFT feature.
7.2 Contributions
The contributions made in the proposed research are listed below:
 Successfully designed, implemented and simulated optimized QCA based
multiplexers.
 Proposed, designed and simulated novel QCA based Programmable Switch
Matrices which are the major routing elements of an FPGA.
132
 Modeled, designed and simulated a QCA based Configurable Logic Block which
includes a feature for Design For Testability (DFT).
 Successfully modeled, designed and simulated a first QCA based FPGA slice by
integrating the proposed Programmable Switch Matrices and Configurable Logic
Blocks.
 Compared the proposed circuits with the existing QCA circuits. The proposed
designs have better optimization with respect to number of QCA cells used, area
occupied, and the latency.
 Introduced modularity in all QCA designs. The Multiplexers, Programmable
Switch Matrices and the CLBs are all modular in design which means that if one
single block is designed, it could be replicated to form higher order designs.
 Tested the proposed designs for different QCA defects such as cell displacement,
cell misalignment, cell omission, cell rotation, and stuck at polarization faults.
7.3 Future Work
The circuits designed in this research can be implemented using metal dot QCA
implementation. However, it is well known that metal dot QCA devices can operate only
at cryogenic temperatures [34]. Recent research, however, has shown that these circuits
can operate at room temperature if the dimensions are slightly increased. Also, molecular
and magnetic QCA circuits can operate at room temperatures. Future work can be done to
modify the proposed circuits for molecular and magnetic QCA implementation.
The tool currently being used in the design and simulations of QCA circuits is the
QCA Designer tool. This tool has many limitations. Research is needed to develop other
133
tools which will give the user better control in the design, layout, and simulation of QCA
circuits. A tool which takes the actual fabrication constraints such as temperature, power,
and cell alignment into consideration will be useful.
134
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Appendix A
QCA Designer Manual
Source: http://www.mina.ubc.ca/qcadesigner_manual
QCA Designer is the product from Walus Group at the University of British
Columbia. It is a design and simulation tool for Quantum Dot Cellular Automata. The
QCA Designer tool facilitates rapid design, layout and simulation of QCA circuits by
providing powerful CAD features available in more complex circuit design tools. This
Appendix covers the procedure for designing QCA circuits using the QCA Designer.
A.1 Adding Objects to the Layout
A.1.1 Creating Cells
There are two ways to add cells to your design. To add an individual cell to your design,
click the button, then click in the design area and a cell will be created at the
click point. To add an entire QCA wire at a time, you may use the array tool. Click the
button then click and drag in the design area. When you release the left
mouse button, the array of cells will be created.
143
Note: QCA Designer does not allow cells to overlap on the same. If you create an array
that overlaps in some points, only those cells that do not overlap will be created.
A.1.2 Adding Labels
To add labels to the objects of the design, click on and click at the
position in the design where you want to the label to appear. By double clicking on the
label, the label can be edited.
A.2 Bus Layout
When there are more number of inputs and outputs in the design, the design becomes
more complex. To simply the design, bus is created which has the collection of inputs or
the collection of outputs. When the designing is complete, we create a bus by clicking on
in the toolbar of the designer or by clicking on Tools  Bus Layout. The inputs in
the design are grouped as a bus and named Inputs and the outputs are grouped as a bus
and named Outputs as shown in Figure A-1.
Figure A-1: Managing Bus Layers
144
To create the bus, first select the inputs and click ‘Create Bus’, hold control (Ctrl) key
select multiple inputs. The position of the buses can be moved and the cells can be made
less significant or more significant by clicking on the respective window. The same of
order of simulation will be displayed as per the position of the bus in the bus layout
window.
A.3 Clocking
The four clocking zones of QCA are represented by four different colors in the QCA
Designer. They are Clock 0 – Green, Clock 1 – Pink, Clock 2 – Blue and Clock 3 –
White. When the cells or array of placed in the designs by default all the cells are in
Clock 0. Now, to select a cell or an array cells in a different clock, click on select and
select the cells or array you need to change the clock and click in the toolbar
and select the required clock. Three steps to be followed to apply the clocking to the cells
are:
Step 1: Select the cells to be clocked
Figure A-2: Selection of cells to apply clocking
Step 2: Choose the type of the clock
145
Figure A-3: Clock Assignment for Selected Cells
Step 3: Release the selection
Figure A-4: Clocked Cells
A default clocking zone can be set instead of Clock 0 by choosing the type of clock in the
layer properties dialog box.
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A.4 Creating and Importing Blocks
The QCA Designer provides with the features such as importing and creating the blocks
of cells.
 Import Block: Importing of blocks of cells from some other designs into the
current design
 Creating block: Creating a block of cells in the current design.
A.4.1 Create Block
To create a block of cells, select the particular cell or an array of cells and in the select
‘Create Block’ in the Tools menu as shown in Figure A-5. A dialog box appears where
the name of the block is entered and saved. If multiple cells in the design have to include
in a single block, the use Shift key to select the multiple cells or arrays.
Figure A-5: Creating a Block
A.4.2 Import Block
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Clicking on Tools  Import Block, one can import a block of any design into the current
design one is working on. After click on the import box, a dialog box appears where we
need to select which block should be imported into the current design. Then, we must
specify to which layer of the current design the block should me imported into as shown
in Figure A-6.
Figure A-6: Importing the blocks
Based on the selection, the new block is imported on the layer where we wish to place to
import it.
A.5 Managing Layers
When the designs are built in multiple layers, one has to make sure the cells in one layer
do not affect the cells in the other layers. So, managing layers feature which most
important for multiple layer designs is provided by the QCA Designer tool. As shown in
Figure A-7, there are three layers. The number of layers in the current design is displayed
by this icon. Now, if the visible box is checked the layer is displayed along with the
148
other layers and if the active box is checked, then the user can manipulate the cells of that
layer. If the layer in not visible, it not active either.
Figure A-7: Dialog box for Layer Management

A.5.1 Layer Ordering
When there are multiple layers in a design, the order in which the layers are matters
because each layer has a physical relation to one another. The reorder layers button
from the tool bar is clicked to reorder the layers. Once this button is clicked the layer
order dialog box appears as shown in Figure A-8. If one need to move the New Layer in
figure after via layer, click on the new layer and drag it after via layer.
Figure A-8: Ordering of the Layers
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A.5.2 Creating New Layer
To create new layer, click on '+' button on the tool bar. To delete a particular layer, click
on the – button on the tool bar as shown in Figure A-9.
Figure A-9: Tool Bar for Managing Layers
The layer properties tool bar pops up when clicked on the create layer button as shown in
Figure A-10. In this dialog you can set the layer status, the layer description (which is the
layer name), as well as the default properties for objects in that particular layer. When
satisfied with the new layer, click OK.
Figure A-10: Dialog Box to Create a New Layer
150
A.6 Other Manipulating Objects
Figure A-11: Toolbar showing other Manipulating Objects
A.6.1 Rotate
 By clicking on this button, one can rotate the dots inside the cell by 45o.
 It is used to create inverted cell.
 Used while designing inverted QCA wire.
 Procedure: Select a cell or array of cells and then click on Rotate. To get back the
normal cells, re-select the cells or array of cells and click on the rotate button
again.
A.6.2 Alt Style
 This button provides with alternate style for the cells.
151
 The cell does not change the functionality but only the representation of the cell
changes.
 There are three types of alternate style: Crossover - represents the crossover cells
of the wire, Normal – represent the normal cell and the Vertical – represent the
vertical interconnect cell which connect different layers during the multi-layer
crossover.
Figure A-12: Alternate Styles of QCA cells
 Select a cell or array of cells and then click on style of the cell. To remove the
alternate style, reselect the cell and click the style you wish to represent the cell.
A.6.3 Copy
 Used to copy a single cell or the array of cells
 Procedure: Select the cell to be copied and click on the copy button.
A.6.4 Translate
 Translate lets the user move the cell in horizontal and vertical direction.
 For example, to design an inverter using inverted QCA wire, we use the QVA
inverter wire and place a normal QCA cell at the half way of two inverted cells,
to place it at the half way we use the Translate option.
152
 Procedure: Select the cell  Click Translate  Select the values for the cell to
move in horizontal and vertical direction.
A.6.5 Mirror
 Gives the mirror image of the circuit.
 Mirror image in both horizontal and vertical direction can be obtained.
 Procedure: Select the circuit for which you need a mirror image and click on the
Mirror button in the tool bar.
A.6.6 Pan
 To move around in QCA Designer usually mouse is used. To scroll your design
vertically, simply turn the mouse wheel. To scroll your design horizontally, hold
down Ctrl while turning the mouse wheel.
 To scroll your design such that a specific QCA cells appears in a specific
location, click "Pan" and simply "grab" the design by that cell.
 To pan large distances quickly, like to the right pan from near the right edge of
the workspace to near the left edge. Pan is faster than using a mouse.
Most of the QCA Designer objects have associated properties. By double clicking on the
object we can modify them.
A.7 Cell Functions
Function of the cell can be modified my double clicking on the cell. When we double
click on any of the cells, cell function dialog will pop up as shown in Figure A-13.
153
Figure A-13: Manipulating Cell Functions
Any cell in QCA can have three cell functions
 Normal Cell: A normal cell do not have any function, it just switches based on the
neighbor cell.
 Fixed Polarization: Using this function, the polarization of the cell can be fixed
either to +1 or -1. The cell will remain at the chosen polarization regardless of the
effect of neighboring cells or clocks.
 Input Cell: Input cells will have a polarization that is determined by the
simulation engine. The input values will be set according to the Simulation Type.
The user can simulate all possible input combinations by choosing the Exhaustive
Verification or select input vectors manually using a Vector Table.
 Output Cell: Output cells act just like normal cells in that they are directly
affected by their neighbors.
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A.8 Exhaustive Verification
The exhaustive verification simulation type simulates all possible combinations of the
input vectors. If you have n inputs, then this will create and simulate all 2n possible
vectors in increasing order. To select the exhaustive simulation click Simulation Type
Setup in simulation tool bar, click on exhaustive simulation and click OK.
Figure A-14: Exhaustive Verification Selection.
A.9 Vector Table
The vector table simulation type allows you to specify the input vectors, as well as the
order in which they are applied to the inputs of your circuit. The vector table simulation
is only available if you already have cells designated as inputs in your circuit. For each
available input you can specify a binary value in each vector. To select the Vector Table
simulation click Simulation Type Setup in simulation tool bar, and make sure that Vector
Table is selected as shown Figure A-15. You will notice that all the inputs in your design
are indicated with their associated names, and they are grouped into the buses you created
for them. Each of the inputs is Active by default. You can make any input Inactive by
toggling the Active checkbox as shown in Figure A.16. When an input is Inactive it is
simulated as if it were just a regular cell in the design; i.e. it is allowed to switch with the
influence of its neighbors. To append vectors to the end, click the button. You can
155
also insert a new vector in front of an existing one by clicking on the column header of
the existing one and clicking on the button:
Figure A-15: Vector Table
Figure A-16: Adding Vectors to the Table
Now, to specify the value of a vector, you can either specify the value of each bus, or you
can check the box next to each input to set individual bits high or low as shown in Figure
A-17.
156
Figure A-17: Editing the Vector Values in the Table
To delete a vector, click on its column header and click the button. When you have
completed your vector table you may save it using the button. You can also
open and use a previously saved vector table. If the other vector table contains fewer
inputs than your design then each extra input not loaded from the vector table will be
padded with 0s.
On the other hand, if the vector table contains more inputs, it will be truncated. Click the
button to use the vector table. The next simulation you perform will be based
on the chosen vectors. Note: if you add or remove inputs to your design, make sure to go
back and edit your vector table.
A.10 Engine Options
The bistable engine options are shown in Figure. A-18
157
Figure A-18: Bistable Engine Options.
A.10.1 Number of Samples
The total simulation is divided by the number of samples. For each sample, the
simulation engine looks at each cell and calculates its polarization based on the
polarization of its effective neighbors (determined by the radius of effect). The larger this
number the longer the simulation will take to complete. However, if you choose too small
a number you may not get the expected results, because there will not be sufficient
samples during input transitions. If you suspect that your results should be something
other than what they are, it is recommend that you try to increase this number.
TIP: If other parameters are default, try setting the number of samples to 1000 times the
number of vectors you are simulating. For exhaustive simulation set to 2000 times 2n,
where n is the total number of inputs in your design.
158
A.10.2 Convergence Tolerance
During each sample, each cell is converged by the simulation engine. The sample
will complete when the polarization of each cell has changed by less than this number;
i.e. loop while any design cell has (old polarization - new polarization) > convergence
tolerance.
A.10.3 Radius of Effect
Because the interaction effect of one cell onto another decays inversely with the
fifth power of the distance between cells, we do not need to consider each cell as
affecting every other cell. This number determines how far each cell will look to find its
neighbors. Make sure that at least the next-to-nearest neighbors are included in this
radius. If you only allow for the nearest neighbor then do not expect designs with
coplanar crossovers to work. Figure A.19 should help clear this up.
Figure A-19: Radius of Effect
159
Note that with multilayer capability the radius of effect is extended into the third
dimension. Therefore in order to include cells in adjacent layers, make sure that the layer
separation is less than the radius of effect.
A.10.4 Relative Permittivity
The relative permittivity of the material system you want to simulate. For
GaAs/AlGaAs it is roughly 12.9 which is the default value. This is only used in
calculating the kink energy.
160

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The University of Toledo

The University of Toledo Digital Repository

Design, implementation, and test of novel

Follow this and additional works at: http://utdr.utoledo.edu/theses-dissertations

Design, Implementation, and Test of Novel Quantum-dot Cellular Automata FPGAs

for the beyond CMOS Era

Master of Science Degree in Electrical Engineering

Dr. Mohammed Y Niamat, Committee Chair

Dr. Mansoor Alam, Committee Member

Dr. Junghwan Kim, Committee Member

Dr. Patricia R. Komuniecki, Dean

The University of Toledo

Design, Implementation, and Test of Novel Quantum-dot Cellular Automata FPGAs

for the beyond CMOS Era

Submitted to the Graduate Faculty as partial fulfillment of the requirements for

The University of Toledo

leakage. In the past, researchers have focused on investigating alternative technologies at

emerging technologies including Single Electron Transistors (SETs), Spin Transistors,

Cellular Automata (QCA) are being investigated as potential candidates to replace

conventional CMOS technology.

omission, cell rotation and stuck at polarization faults.

Designer software tool.

serving as my committee members.

ability and encouraging me throughout my Masters. I would like to thank my cousins

Abstract ............................................................................................................................. iii

List of Tables ................................................................................................................... xiv

List of Figures .................................................................................................................. xvi

1.1 Motivation ................................................................................................................. 1

1.2 Research Objectives .................................................................................................. 4

1.3 Organization of the Thesis ........................................................................................ 8

2. Quantum-dot Cellular Automata .............................................................................. 10

2.1 Introduction ............................................................................................................. 10

2.2 QCA Cells ............................................................................................................... 10

2.3 Clocking in QCA .................................................................................................... 13

2.4 QCA Logic Devices ................................................................................................ 17

2.4.1 Binary Wire ...................................................................................................... 17

2.4.2 QCA Inverted Wire .......................................................................................... 18

2.4.4 Majority Voter ................................................................................................. 21

2.6 Cross-Wiring in QCA ............................................................................................. 24

2.6.1 Coplanar Crossover .......................................................................................... 25

2.6.2 Multi-Layer Crossover ..................................................................................... 26

2.7 QCA Implementation .............................................................................................. 28

2.7.1 Metal QCA ....................................................................................................... 28

2.7.2 Molecular QCA ................................................................................................ 32

2.7.3 Magnetic QCA ................................................................................................. 34

3. Design, Implementation and Simulation of Multiplexers in QCA ......................... 38

3.1 Introduction ............................................................................................................. 38

3.2 Design, Modeling and Simulation of QCA Multiplexers ....................................... 39

3.2.1 The (2:1) Multiplexer ....................................................................................... 40

3.2.2 The (4:1) Multiplexer ....................................................................................... 42

3.2.3 The (8:1) Multiplexer ....................................................................................... 45

3.2.4 Latency and Area comparisons with previous research ................................... 49

4. Design, Modeling and Simulation of a Novel Configurable Logic Block in QCA 50

4.1 Introduction ............................................................................................................. 50

4.1.1 Design, Modeling and Simulation of the Address Decoder ............................ 53

4.1.3 Design, Modeling and Simulation of Multiplexers.......................................... 60

4.1.4 Design, Modeling and Simulation of the SR flip flop ..................................... 60

4.1.6 Functional verification of the Configurable Logic Block ................................ 67

4.2 Functional verification of multiple CLBs ............................................................... 70

4.3 Four LUT Configurable Logic Block ..................................................................... 75

4.4 Design parameters and analysis of simulation results ............................................ 76

5. Modeling and Design of a Novel Quantum-dot Cellular Automata Switch for

5.1 Introduction ............................................................................................................. 79