256-Channel ADSL
This model shows part of the asymmetric digital subscriber line
(ADSL) technology for transmitting data and multimedia This example also uses:
information over telephone lines. It illustrates a downstream path Simulink
from the central office to the end user. It incorporates the discrete
multitone (DMT) signaling modulation technique.
Open Model
The DMT modulator and demodulator subsystems in the model
have been updated to allow code reuse when generating code.
These subsystems now generate only 10 unique reusable
functions compared to the 256 chunks of code for each modulator/demodulator block generated earlier. This
leads to shorter compile times and smaller executable sizes.
Transmitting Data
The transmitter portion of the model, shaded in blue at the top of the model, contains two parallel paths. One
path (the fast buffer) processes the first 776 bits of each 1552-bit data frame, while the other path (the
interleaved buffer) processes the last 776 bits of each data frame. Each path appends eight cyclic redundancy
check (CRC) bits to its 776-bit frame, scrambles the bits, and encodes them using a shortened Reed-Solomon
code. The scrambling and encoding operations interpret the bits as integers between 0 and 127. In the second
path but not the first, a Convolutional Interleaver block interleaves the encoded data. This interleaving operation
increases the second path's resistance to burst errors but also its latency. Finally, the data from the two routes
is concatenated and modulated. Data from the fast buffer is modulated to the low frequency subcarriers, while
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data from the interleaved buffer is modulated to the high frequency subcarriers, according to the bit allocation
vector b. This example assumes that the bit allocation vector is known and uses the vector to calculate the
channel. Enter get_param('commadsl', 'preLoadFcn')to see the calculations involved.
Aligning Frames to Account for Delays. One subtle point in the receiver portion is the Integer Delay block
that follows the Convolutional Deinterleaver block. This Integer Delay block delays the deinterleaved data by 800
samples. Because the delay between the original and restored sequences is 40 samples (five shift registers
times a maximum delay of 2*(5-1) samples among all shift registers), the extra 800-sample delay ensures that
bits are properly aligned in the 840-bit frame.
In each of the display icons, the error statistics consist of the bit error rate, the number of bit errors, and the
total number of bits processed.
Selected Bibliography
[1] Bingham, John A.C., ADSL, VDSL, and Multicarrier Modulation, New York, Wiley, 2000.
[2] ITU-T Recommendation G.992.1 Asymmetric Digital Subscriber Line (ADSL) Transceivers, Geneva,
Telecommunication Standardization Sector of International Telecommunication Union, 1999.
[3] Maxwell, Kim, "Asymmetric Digital Subscriber Line: Interim Technology for the Next Forty Years," IEEE
Communications Magazine, October 1996, pp. 100-106.
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