DAC - ADC
EIM Chap 2 – Digital to analog converter . Analog to digital converter
2
EIM Chap 2– Digital to analog converter
Binary representation n 2
N = ∑ bk 2k ; bk ∈ {0,1} ;
of numbers (n1+n2+1 bits): k =− n 1
4
EIM Chap 2– Digital to analog converter
Unipolar Codes
N (natural) Fraction ( subunitar nr) NB BCD Gray
0 0 0000 0000 0000
1 1/16 0001 0001 0001
2 2/16 0010 0010 0011
3 3/16 0011 0011 0010
4 4/16 0100 0100 0110
5 5/16 0101 0101 0111
6 6/16 0110 0110 0101
7 7/16 0111 0111 0100
8 8/16 1000 1000 1100
9 9/16 1001 1001 1101
10 10/16 1010 - 1111
11 11/16 1011 - 1110
12 12/16 1100 - 1010
13 13/16 1101 - 1011
14 14/16 1110 - 1001
15 15/16 1111 - 1000
5
EIM Chap 2– Digital to analog converter
Bipolar Codes
N Fraction SM C1 C2 OB* OB
+3 +3/8 011 011 011 111 000
+2 +2/8 010 010 010 110 001
+1 +1/8 001 001 001 101 010
+0 +0 000 000 000 100 011
-0 -0 100 111 - - -
-1 -1/8 101 101 111 011 100
-2 -2/8 110 101 110 010 101
-3 -3/8 111 100 101 001 110
-4 -4/8 - - 100 000 111
6
EIM Chap 2– Digital to analog converter
7
EIM Chap 2– Digital to analog converter
8
EIM Chap 2– Digital to analog converter
⎛ n ⎞
U ( N ) = U R ⋅ ⎜ ∑ bk 2− k − 2−1 ⎟
⎝ k =1 ⎠ V LSB
U max = U R ⋅ ( 2 − 2 )
N
000
LSB 001
010
011
MSB 100
101
110
Nmax+1
Nmax 111
−1
U min = −U R ⋅ 2 −1 −n
9
EIM Chap 2– Digital to analog converter
Non-ideality errors
Static errors
Offset error - analog output response to an input code
corresponding to output zero;
Gain error – difference between slope of actual and ideal
transfer function;
Full-Scale error - difference between the actual and the ideal
output maximum value (offset error + gain error) ;
Integrated nonlinearity error (INL) - deviation of an actual
transfer function from a straight line (after nullifying offset and
gain errors);
Differential nonlinearity error (DNL) - difference between the
ideal and the measured output responses for successive
DAC codes;
Dynamic error: overshoot, undershoot (during settling time)
10
EIM Chap 2– Digital to analog converter
tsw ts tsettling t
INL error DNL error Settling time
11
EIM Chap 2– Digital to analog converter
⎛ Ts ⎞ ∞
Ysh ( f ) =sinc⎜ 2π f ⋅ ⎟⋅ ∑ Yk ( f −nf s )
⎝ 2 ⎠ n=−∞
13
EIM Chap 2– Digital to analog converter
Types of DAC’s
• Binary Weighted Resistor Network
• R-2R Ladder Network
• Stochastic
• Multiplying DAC
14
EIM Chap 2– Digital to analog converter
⎛n 1 1 ⎞ n
bi
Vg ( N )⋅⎜ ∑ i + n ⎟=VR ∑ i bi ∈{0,1} 0 .....
⎝ i=1 2 R 2 R ⎠ i=1 2 R
8R
n b3
0
RT=2nR
After source passivization:
n
1 = 1 + 1 = 1 ⇒ R N =R
∑
R( N ) i=1 2 R 2 R R
i n ( )
15
EIM Chap 2– Digital to analog converter
V0 ( s ) =Vg ( s )⋅ 1 ⋅1 =V ( s )⋅⎛1 − 1 ⎞
g ⎜ ⎟
sRC p +1 s ⎝ s s +1/τ ⎠
⎛ −t ⎞ 1
V0 (t ) =Vg ⋅⎜1− e τ ⎟⋅σ (t ) , τ= current command
⎜
⎝
⎟
⎠ R( N )C p R(N)
1 ⎛ − n−1 VR ⎞ V0(t)
V0 (ts ) −Vg ( N ) ≤ δ V ⇒ ts ≥ τ ⋅ln ⎜ 2 ⎟⎟
2 ⎜
⎝ Vg ( N ) ⎠ Vg(N) σ(t)
Cp
16
EIM Chap 2– Digital to analog converter
Disadvantages:
• Resistance Values Require Great Accuracy:
e.g. Tolerance of R must be < 1/2n
• Often limited to 4-Bit conversions because of the limited current
range possible with resistors;
• Hardware difficult realization for large bits number (due the weight
inaccuracy for the large range);
17
EIM Chap 2– Digital to analog converter
I1 I2
VR 2R 2R ..... 2R 2R RT=2R
Ik = 2 R ⋅ I = 2 − k VR = 2 − k I
k −1 R
2R + 2R
b1 b2 bn-1 bn
R 0 1
Rr
0 1
[B]
V0 ( N ) =− Rr I ( N ) V0(N)
Convertor I - U
n n
Rr n
I ( N ) = ∑ I k = 1 VR ∑bk 2 − k ⇒ V0 ( N ) = − VR ∑bk 2 − k
k =1 R k =1 R k =1
Rr
V0_ max ( N = 0...0h ) = 0V V0_ min ( N = F ...F h ) = − ⋅VR ⋅(1− 2 − n )
R
Rr
δV =V0 ( N = 0...1h ) = − ⋅VR ⋅2 − n
R
18
EIM Chap 2– Digital to analog converter
19
EIM Chap 2– Digital to analog converter
∞
C y out ( t ) = A0 + ∑ Ak cos⎛⎜ k 2π t +φk ⎞⎟
n
R
Cy out
k =1 ⎝ T ⎠ SUM
C
V(N)
out
T = ( 2n − 1) TCK
n unused
(nefolosit)
n
N
η=Ν/2n
Cy out
ηT
1 1 1 1
H(f) = = fT = <<
1 + j 2π fRC ⎛ f ⎞
2
2π RC T t
1+ ⎜ ⎟
⎝ fT ⎠ T nTn
= (2
T=2 -1)TCK
CK
τN1 2n E n
V ( N ) = A0 = E = n N = VR ∑ bk 2− k
Cy out(ω)
E= n LPF
T 2 −1 2 −1 k =1 A0 A1
A2
Multiplying DAC
U out ( t )
• slow time varying external U Ref
U Ref = U in ( t ) t
U out ( t )
dU in ( t ) δUo
<<
dt max
2 ⋅ tconv t
DAC applications
• Digital Audio
e.g. CD player;
• Digital Communications
e.g. digital telephone and video systems;
Ik = 2-k· I
n
V n
I '0 ( N ) = ∑ I ' k = R ∑ k
(1− b ) 2 −k
k =1 Rref k =1
n
V n
I 0 ( N ) = ∑I k = R ∑b 2 k
−k
k =1 Rref k =1
VR VR − 8
I '0_ min ( N = FFh ) = 0 I '0_ max ( N = 00h ) =
Rref
(1− 2 −8 ) δ I '0 = −
Rref
⋅2
V V
I '0_ min ( N = 00h ) = 0 I '0_ max ( N = FFh ) = R (1− 2 −8 ) δ I '0 = + R ⋅2 − 8
Rref Rref
23
EIM Chap 2 – Digital to analog converter
I _
DAC - 08 +
vout =− RI ( N )
u(t)
IN Vout
I
N
n
vout (t ) =−uin ( t )⋅ R ⋅∑bk 2 − k = Au ( N )⋅uin ( t )
Rref k =1
n
Au ( N ) =− R ⋅∑bk 2 − k
Rref k =1
24
EIM Chap 2 – Analog to digital converter
s(t) {n}
Analog to Digital Converter ADC
25
EIM Chap 2 – Analog to digital converter
s(t) {n}
Analog to Digital Converter ADC
26
EIM Chap 2 – Analog to digital converter
Parameters (cont’d)
Converter Throughput Rate - the number of times the input signal can be
sampled maintaining full accuracy
- Inverse of the total time required for one
successful conversion
- Inverse of Conversion time if no S/H
(Sample and Hold) circuit is used
ADC Interface Signals :
Data: Digital I/O pins the ADC uses to supply data
Parallel output – n+1 pins (fast transmission, short distances)
Serial output – 2 pins (for long distances, need a internal shift-register)
Start: Pulse high to start conversion (input)
EOC (End of Conversion): Typically active low → low level of pulse
indicate complete conversion (output value can be read);
Clock: Clock used for conversion (for synchronising ADC sub-blocks, for
internal FSM);
27
EIM Chap 2 – Analog to digital converter
X SH ( f ) XQ ( f )
f f f f
28
EIM Chap 2 – Analog to digital converter
Ideal sampling
x(t ) → xs (t ) = x[n] = x(nTs )∈R
+∞
xs (t ) = ∑ x(t )⋅δ (t −nTS ) = x(t )⋅δ TS (t )
n =−∞
+∞ 2π
jn t
δ T (t ) = 1 ∑e TS
S
TS n =−∞
+∞
⎛ n ⎞
{ }
X S ( f ) = F x(t )⋅δ TS (t ) = X ( f ) ⊗ 1
∑ ⎜ T ⎟
δ
TS n=−∞ ⎝
f −
-fm fm
S ⎠
|XS( f )|
1
+∞
⎛ n ⎞ +∞
= ∑ X ⎜ f − ⎟ = f S ⋅ ∑ X ( f −n⋅ f S )
TS n=−∞ ⎝ TS ⎠ n=−∞
-fS -fm fm fS
29
EIM Chap 2 – Analog to digital converter
n =−∞
2π nTS + TS /2 2π n
−j −j t
Pn =e 2TS
⋅ 1 ∫ pTS (t )⋅e TS
dt
Ts −TS /2 -fm fm
⎛
+∞
⎞
{ } n
X S ( f ) = F x(t )⋅ pTS (t ) = ∑ Pn ⋅ X ⎜ f − ⎟
n =−∞ ⎝ TS ⎠ -fS -fm fm fS
30
EIM Chap 2 – Analog to digital converter
+∞
⎛ ⎞
X S ( f ) =⋅e − jπ fTS
⋅sinc(π f TS )⋅ ∑ X ⎜ f − n ⎟ -fm fm
n=−∞ ⎝ TS ⎠
31
EIM Chap 2 – Analog to digital converter
Quantizing process
- analog signal approximation to the nearest discrete value:
x [ n ] → x q [n ] = q k ⇒ k , k ∈ 1, M , qk ∈QM
aM xq(t)
qM → M qM → M
Quant. ak Quantized
thresholds qk → k qk → k
values
ak-1
q2 → 2 q2 → 2
a1
q1 → 1 q1 → 1
a0
2 1 2 k M +δ/2
nq(t) t
t -δ/2
Quantization of non-sampled signal (continuous)
32
EIM Chap 2 – Analog to digital converter
ak
qk → k
ak-1
Quantization qk-1 → k-1 Quantized
thresholds values
a2
q2 → 2
a1
q1 → 1
a0
nsq(t)
Quantization ½ δ
noise -½ δ t
Analog signal
Sampled signal (sample & hold)
Quantized signal
33
EIM Chap 2 – Analog to digital converter
Quantization
Truncating quantization qk = ak −1
n n
U qt = U ref ∑ 2 bi = δ U ∑ 2n −i bi = N t δ U
−i
i =1 i =1
12 12 Ideal characteristic
34
EIM Chap 2 – Analog to digital converter
Quantization (cont’d)
ak +ak +1
Rounding quantization qk +1 =
2
⎛ −n n
⎞
U qr = δ U ⋅ bn +1 + U qt = U ref ⎜ 2 bn +1 + ∑ 2− i bi ⎟
⎝ i =1 ⎠
= ( N t + bn +1 )δ U = N r δ U , bn +1 ∈{0,1}
Quantization noise
n
nqt =U −U qt =U ref (− 2 − ( n +1)
bn+1 + ∑ 2 − i bi )
i =n+ 2
p(nq)
δ2 2−2 n 2
Noise variance (power) σ 2
qr = E{nqr } − [ E{nqr }] =
2 2
= U ref
12 12
35
EIM Chap 2 – Analog to digital converter
Quantization (cont’d)
Round-ceiling quantization qk = ak
∞
U qm = δ U + U qt = U ref (2 −n
+ ∑ 2− i bi )
i =1
= ( N t + 1)δ U = N m δ U
Quantization noise
∞
nqm =U −U qm =U ref (− 2 + ∑ 2 − i bi )
−n
i = n +1
36
EIM Chap 2 – Analog to digital converter
Quantization (cont’d)
Noise value as: voltage (rms, p-p), LSB (rms, p-p), SNR;
Signal to quantization noise ratio (SNR)
Considering a periodic signal at input, with period T, having power:
T
1
Px = ∫ x 2 ( t ) dt = U x2_ ef
T 0
⎛P ⎞ ⎛ U x2_ ef ⎞ ⎛ 12 ⋅ U x2_ ef ⎞ ⎛ 2 n 12 ⋅ U x2_ ef ⎞
SNR ( n ) = 10 ⋅ log ⎜ x ⎟ = 10 ⋅ log ⎜ 2 ⎟⎟ = 10 ⋅ log ⎜⎜ ⎟⎟ = 10 ⋅ log ⎜⎜ 2 ⋅ ⎟⎟
⎜ Pn ⎟ ⎜ σ
⎝ δ
2 2
⎝ q ⎠ ⎝ q ⎠ ⎠ ⎝ U ref ⎠
⎛ U x _ ef ⎞
= 6, 02 ⋅ n + 10,8 + 20 ⋅ log ⎜
⎜ U ⎟⎟
[dB]
⎝ ref ⎠
Total SNR after quantization process:
For analog noisy signal, the total noise power is σ T = σ a + σ q
2 2 2
U x2_ ef ⎛ σ a2 ⎞
effective bit number : nef = log 4 = n − log 4 ⎜1 + 2 ⎟⎟
σ T2 ⎜ σ
⎝ q ⎠
37
EIM Chap 2 – Analog to digital converter
Quantization (cont’d)
U ref
Example: a full range sine wave input x ( t ) = A sin (ωt ) A≅
2
2
1 2
T
A 2 U
Px = ∫ x ( t ) dt =
ref
Signal power and rms value: = U x _ ef =
2
T 0 2 8
⎛P ⎞ ⎛ A 2 ⎞
⎛ 6 A 2
⎞ ⎛ 3 ⋅ U 2
⎞
SNRq ( n ) = 10 ⋅ log ⎜ x ⎟ = 10 ⋅ log ⎜ 2 ⎟ = 10 ⋅ log ⎜ 2 ⎟ = 10 ⋅ log ⎜
ref
⎜ 2σ ⎟ ⎜ ⎟⎟
⎜ Pn ⎟ ⎝ δ ⎠ 2 ⋅ 2 −2 n
U 2
⎝ q⎠ ⎝ q⎠ ⎝ ref ⎠
SNRq ( n ) = 6.02 ⋅ n + 1.76 dB (for sinwave quantization)
Smax
Dynamic range: DR = 20 ⋅ lg = 6, 02 ⋅ n + 1.76 dB=SNRq
S min
ENOB = ( DR − 1, 76 dB ) / 6.02
Example: S N R q (1 0 b it ) = 6 2 d B
A2 1 ⎛ σ a2 ⎞
total effective bit number: nef = log 4 2 + log 4 = n − log 4 ⎜ 1 + 2 ⎟⎟
σT 3 ⎜ σ
⎝ q ⎠
38
EIM Chap 2 – Analog to digital converter
Non-ideality errors
Static errors
Offset error (linear error);
Gain error (linear error);
Full-Scale error (offset error + gain error) ;
Integrated nonlinearity error (INL);
Differential nonlinearity error (DNL);
Dynamic error:
Aperture error (due to the delay between
the clock signal of S/H block and the effective holding time)
d x(t )
EA = TA < δ V ⇒ TA = n 1
dt 2 2 πf
39
EIM Chap 2 – Analog to digital converter
Offset error
Gain error
Factor scale error
40
EIM Chap 2 – Analog to digital converter
.
An ideal three-bit quantizer, with INL An ideal three-bit quantizer, with
error caused by important DNL error INL error and small DNL error
41
EIM Chap 2 – Analog to digital converter
fS fS
OSR = =
f S min 2⋅ f sig
42
EIM Chap 2 – Analog to digital converter
43
SFDR is an important specification in communications systems because it
EIM Chap 2 – Analog to digital converter
Input Tone
input tone
harmonics
Quantization Noise
• Harmonics
• intermodulation products
44
EIM Chap 2 – Analog to digital converter
45
EIM Chap 2 – Analog to digital converter
Flash ADC
• bank of 2n -1 parallel comparators (high complexity);
• very fast - GHz sampling rates (limited only by
delays of comparators and logic network);
• references – resistor ladder
Digital
• few bits of resolution (4 – 8 bits, rarely 10 bits)
• high input capacitance Input DOUT
• expensive power / area (in IC)
backend
• are prone to produce glitches (clock skew –
comparators sample the inputs at different instants)
• high cost
• applications: video, wideband communications,
optical storage
clock
46
EIM Chap 2 – Analog to digital converter
Flash ADC
Improving technique – track / hold
• T/H for good dynamic performance
• Offset correction in comparators
Input
Track / Hold
DOUT
Example: AD9066 Dual 6-bit, 60MSPS
Flash ADC
Key specifications:
• Input Range: 500mV p-p
• Input Impedance: 50kΩ || 10pF
• ENOB: 5.7 bits @15.5MHz Input Offset
correction
• On-Chip Reference
• Power Supply: Single +5V
• Package: 28-pin SOIC
• Ideal for Quadrature Demodulation
47
EIM Chap 2 – Analog to digital converter
48
EIM Chap 2 – Analog to digital converter
49
EIM Chap 2 – Analog to digital converter
50
EIM Chap 2 – Analog to digital converter
STAGE 1 STAGE 2
51
EIM Chap 2 – Analog to digital converter
52
EIM Chap 2 – Analog to digital converter
53
EIM Chap 2 – Analog to digital converter
54
EIM Chap 2 – Analog to digital converter
Bit 2 = 0
Bit 4 = 0
Bit 3 = 1
VDAC
Bit 1 = 1
Tconv = nT
⋅ CK
Slower than Flash, but far fewer comparators
4 Bit SAC
– allows for higher accuracy
55
EIM Chap 2 – Analog to digital converter
DAC
CNA
• use a feedback to adjust the counter;
I(N) IR
• very wide range and high resolution;
• conversion time is dependent of the input signal level (has a guaranteed value
for the worst case);
• introduces granular noise for constant and very low frequency signals;
• can expect overflow error for rapid variable signal;
Granular
noise Overflow
56
EIM Chap 2 – Analog to digital converter
Ux
• When the comparison voltage matches +
_
CMP NUM
57
EIM Chap 2 – Analog to digital converter
Sigma-delta ADC
• the output is in the form of a 1 bit serial
bit stream;
• analog input variation proportional to
the duty of the output digital signal;
• Oversampling (sampling freq 16 – 512
times greater than Nyquist rate);
Sigma-delta ADC of the first order
• low complexity;
• presents “granular” noise for constants
and possible overflow error for fast
analog input;
• applications: typical low bandwidth
digital transmission 22KHz(voice in digital
telephone network); recently - ADSL
network access, 1-2MHz (multi-bit ADC
and multi-bit feedback DAC ); digital
audio equipment (16-24 bit resolution,
48kS/s);
Oversampling ADC (Σ-Δ ADC)
58
EIM Chap 2 – Analog to digital converter
Sigma-delta ADC
• Quantization noise is
pushed out of the signal
band;
• digital filter eliminates
out of band noise ;
• very high SNR
Signal Quant. Noise
spectrum spectrum
59
EIM Chap 2 – Analog to digital converter
Sigma-delta ADC
• better performances for high order
Σ-Δ ADC (second, third, etc.);
• changing LPF (integrator) →BPF we can
reduce the noise mDSP (N0) in band of interest; Second order Σ-Δ ADC
60
EIM Chap 2 – Analog to digital converter
61
EIM Chap 2 – Analog to digital converter
U x (t ) t n
= x = Nn' ⇒ U x (t ) =VR ⋅∑bi 2 − i =VR ⋅N
VR T1 2 i =1
62
EIM Chap 2 – Analog to digital converter
Phase:
• Phase 1 – auto zero
(K1=0, K2=0)
•Phase 2 – unknown
voltage integrating (K1=1,
K2=1)
•Phase 3 - reference
voltage integrating (K1=2,
K2=2)
63
EIM Chap 2 – Analog to digital converter
UX
64
EIM Chap 2 – Analog to digital converter
UX
65
EIM Chap 2 – Analog to digital converter
VP =V0 − 1 ∫U x (t )dt
R1C T2
V0 =Vp + 1 ∫U GI dt − 1 ∫U x (t )dt
R2C T1 R1C T1
V0
R
U x = 1 ⋅ 1 ⋅U GI ⋅T1 = K ⋅ f out
T1 +T2 R2
66
EIM Chap 2 – Analog to digital converter
UX
Vin RS 1
f out = ⋅ ⋅
2.09V RL Rt Ct
67
EIM Chap 2 – Analog to digital converter
linie lunga
(transmisie la distanta)
Remote transmission
Ux U-f f-U Ux
Vin R RL
f out = ⋅ S⋅ 1 Vout = f in ⋅2.09 ⋅ ⋅ Rt Ct
2.09V RL Rt Ct Tx Tx to
Catre f-metru
f-metru RS
68
EIM Chap 2 – Analog to digital converter
Ultra-fast ADC
Pure electronic ADC: CCD-ADC;
Optical ADC : Time-stretch ADC.
• CCDs - ADC
Charged-Coupled device (CCD) - sampled analog clocked delay line that
memories the input voltage at the clock impulse (analogical memory);
Typically size – 512 stages (samples) and 100MS/s;
An slower ADC quantizes these analogical values;
For greater effective sample rate (400MS/s) are necessary several CCDs
in parallel with staggered clock drive.
Application – digital video signal capturing
69
EIM Chap 2 – Analog to digital converter
Ultra-fast ADC
CCD matrix scheme
70
EIM Chap 2 – Analog to digital converter
71
EIM Chap 2 – Analog to digital converter
72
EIM Chap 2 – Analog to digital converter
73
EIM Chap 2 – Analog to digital converter
• Improvements:
• Effective sampling rate increased by M ;
• Effective Input bandwidth increased by M ;
• Reduce jitter noise ;
• Eliminates the need for samples interleaving ;
• Ideal for time-limited signals or fast time-varying signals ;
74
EIM Chap 2 – Analog to digital converter
Δλ1 x4 Digitizer
WDM
T
Δλ2
PRISM
Digitizer
x4
Δλ3 Digitizer
Time/ wavelength
Time x4
Δλ4
Δλ3
Δλ2 Δλ4 Digitizer
Δλ1 x4
T TI-ADCs
Time Stretch 4T
T
75
EIM Chap 2 – Analog to digital converter
Stretched Signal
Wavelength
Input RF
Signal
Stretch Factor = 1 + L2 / L1
Time Aperture = D x Δλ x L1
Baseband BW* = 1 /(8πβ 2 L1 )
Time BW Product* = Δf op / 2Δf RF
76
EIM Chap 2 – Analog to digital converter
∑ bm exp(− j
2πkm ⎤
)⎥ × L ⋅ exp⎡− j πk ( N − 1) ⎤
⎢
L ⎣ m =0 M ⎦ πk ⎢ L ⎥
sin ⎣ ⎦
L
Gain
2π L −1
kωs
Mismatch S (ω ) =
Ts
∑ Fk ×δ (ω − ωo −
k =0 L
)
Clock 1 ∞
kω s
Skew S (ω ) =
Ts
∑
k = −∞
Fk × δ (ω − ω0 −
L
)
πkN
sin
1⎡ M −1
2πkm ⎤ L × exp ⎡− j πk ( N − 1) ⎤
Fk = ⎢ ∑
L ⎣ m=0
exp(− jω0 rmTs ) exp(− j )⎥ ×
M ⎦ sin πk ⎢
⎣ L ⎥
⎦
L
L=MxN: the period of distortion pattern
77
EIM Chap 2 – Analog to digital converter
signal signal
spurs fs/(MxN)
78
EIM Chap 2 – Analog to digital converter
• Conclusions:
• Signal is reconstructed based on segments, instead of the individual
samples;
• In each segment, the sampling is above the Nyquist sampling rate;
• Subject to the similar mismatch as the sample-interleaved counterpart;
79
EIM Chap 2 – Analog to digital converter
Bibliography
S. Ciochina, Masurari electrice si electronice, 1999 ;
ham.elcom.pub.ro/iem;
Application notes - National Instruments;
J.G. Webster, Electrical Measurement, Signal Processing and Displays,
2004;
80