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ENCS333

Homework 3

Due October 31ST

1. What are the basic steps for CMOS IC fabrication?

A. Si Substrate: Start with p-type substrate


B. Oxidation: Exposing to high-purity oxygen and hydrogen at approx. 1000oC in
oxidation furnace
C. Photoresist coating: Photoresist is a light-sensitive organic polymer Softens when
exposed to light
D. Masking: Expose photoresist through n-well mask
E. Acid etching: SiO2 is selectively removed from areas of wafer that are not covered by
photoresist by using hydrofluoric acid
F. Removal of Photoresist: Photoresist are removed by treating the wafer with acidic or
basic solution.
G. Formation of N-well: n-well is formed with diffusion or ion implantation
H. Removal of SIO2: Strip off the remaining oxide using HF
I. Polysillicion deposition: Deposit very thin layer of gate oxide using Chemical Vapor
Deposition (CVD) process
J. N-diffusion: N-diffusion forms nMOS source, drain, and n-well contac
K. P diffusion: Dopants were diffused or ion implantated
L. Contact cuts: The devices are to be wired together Cover chip with thick field oxide
Etch oxide where contact cuts are needed
M. Metalization: Sputter on aluminum over whole wafer Pattern to remove excess metal,
leaving wires
2. IC design is a set of files by which one can manufacture and test the designed IC. List 5
of these files
A process design kit (PDK) is a set of files used within the semiconductor industry to model
a fabrication process for the design tools used to design an integrated circuit. The PDK is
created by the foundry defining a certain technology variation for their processes. It is then
passed to their customers to use in the design process

A. primitive device library

 Symbols
 Device parameters
 Pcells

B. Verification decks

 Design Rule Check


 Logic VS Schematic
 Physical Extraction
C. Technology data
 Layers, layer names, layer/purpose pairs
 Colors, fills and display attributes
 Process constraints
 Electrical rules
D. Rule files
 LEF
 Tool dependent rule formats
E. Simulation models of primitive devices (SPICE or SPICE derivatives)
 Transistors (typically SPICE)
 Capacitors
 Resistors
 Inductors

3. What do we mean by we can Automat the design ?


It means that we can use software tools for designing electronic systems such as integrated circuits and
printed circuit boards. The tools work together in a design flow that chip designers use to design and
analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of
components, EDA tools are essential for their design.

4. There are 5 Design Levels, what are they ? Explain?

5. What does Verification is used for? List Verification Methods


6. • Formal Verification This method mathematically proves that same design at different design
levels has fully equivalent function
Static Timing Analysis Path delay is calculated by summing delays of elements without
simulation
Simulation The behavior of object in time and space is reproduced
Emulation using device, which works as the system to be verified, submits test vectors, output
signal checks
• Prototyping Building of hardware implementation of design and its testing

7. How to evaluate performance of a digital circuit (gate, block, …)?

• Area/Cost
• Reliability
• Scalability
• Speed (delay, operating frequency)
• Power dissipation
• Energy to perform a function

8. List four Reliability Issues in CMOS DEVICES ?

9. Explain N-channel hot-e degradation? How to reduce the hot-e degradation?


When a MOS transistor is in saturation, the electric field across the pinch-off region may be high enough
that carriers gain there enough energy to excite electron-hole pairs. 1V / 0.01um = 106 V/cm, huge
electrons (holes) acceleration • The e-h pairs become components of the drain and substrate currents.
• The holes (electrons) usually flow towards the p-substrate (n-well) in an n-ch (p-ch) device, increasing
the substrate currents (bad for latch-up!). • The excited electrons (holes) that reach the drain cause an
increase in Ids (weak avalanche). • However, the reliability concern is that part of the hot-e can
penetrate the gate oxide !!! • P-ch transistors are usually less susceptible to hot-e degradation due to
the holes lower mobility (higher effective mass).

Hot-e degradation (cont’d)

• Electrons that penetrated the gate oxide remain trapped there (in normal operating conditions). The
hot-e effect is accumulative ! • The negative trapped charge in the oxide (near the drain) of an NMOS
cause an increase in Vt. • The hot-e effect result is a degradation in the NMOS Ids (due to the higher
effective Vt). Meaning: circuits slow down! • Note! the hot-e degradation has a negative feedback
behaviour. • Hot-e degradation is a long term reliability concern. The device life time that Intel
guarantees is 7 years of constant operation at the worst case conditions (within the spec). Meaning:
When a device frequency is tested after fabrication, the hot-e degradation with time must be taken into
account

10. What is the difference between simulation and modeling in IC design ?

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