Analysis and Design of Analog Integrated Circuits

Lecture 17

Basic Two Stage CMOS Opamp

Michael H. Perrott
April 4, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Opamps Are Basic Analog Building Blocks
Analog Filters Current References Switched Capacitor Circuits
C1 C2
Iref
R1
Vin Vref Vin
Vout Vout
Vref C1 Vref

Rref

 Enable active filters

- Can achieve arbitrary pole/zero placement using only
capacitor/resistor networks around the opamp
 Allow accurate voltage to current translation
 Provide accurate charge transfer between capacitors
- Extremely useful for switched capacitor circuits used in
analog-to-digital converters and discrete-time analog
filters
M.H. Perrott 2
 Key Specifications of Opamps (Open Loop)
Rhuge
For Open Loop Characterization
Chuge Vdd
Set Rhuge >> |Zout|
Vout
and 1/(RhugeChuge) << wdom
Vss CL
Vin Zout
20log(K)

Vdd 20log Vout/Vin

Vout 0dB
Vss CL
Vin w (rad/s)
wdom w0 wp

 DC small signal gain: K

 Unity gain frequency: w0
 Dominant pole frequency: wdom
 Parasitic pole frequencies: wp (and higher order poles)
 Output swing (max output range for DC gain > Kmin) 3
M.H. Perrott
 Key Specifications of Opamps (Closed Loop)

Vdd
Voffset Vout

Vss CL
Vin

 Offset voltage
 Settling time (closed loop bandwidth)
 Input common mode range
 Equivalent Input-Referred Noise
 Common-Mode Rejection Ratio (CMRR)
à !−1
δVoffset
CMRR =
δVin
 Power Supply Rejection Ratio (PSRR)
à !−1 à !−1
+ δVoffset − δVoffset
PSRR = PSRR =
δVdd δVss
M.H. Perrott 4
 Slew Rate Issues for Opamps

Vdd Vin

Vout
ideal
Vss CL
Vin Vout
slew-rate limited

 Output currents of practical opamps have max limits

- Impacts maximum rate of charging or discharging load
capacitance, C L
- For large step response, this leads to the output lagging
behind the ideal response based on linear modeling
 We refer to this condition as being slew-rate limited
 Where slew-rate is of concern, the output stage of the
opamp can be designed to help mitigate this issue
- Will lead to extra complexity and perhaps other issues
M.H. Perrott 5
 Basic Two Stage CMOS Op Amp

M8 M7
M5

Iref Vin- Vin+ Vout

M1 M2
CL

Rc Cc

M3 M4 M6

 This is a common “workhorse” opamp for medium

performance applications
 Provides a nice starting point to discuss various
CMOS opamp design issues
 Starting assumptions: W1/L1 = W2/L2, W3/L3 = W4/L4

M.H. Perrott 6
 First Stage Analysis

M5 Ibias1
First Stage Two-Port Model
-vid/2 vid/2
M1 M2
Rout1 vid V1 Zin Gm1V1 Rout1 Zin2 vout1

vout1

M3 M4

 Derive two port model assuming differential input:

1 1
Zin1 = =
s(Cgs1/2) s(Cgs2/2)
Gm1 = gm1 = gm2

Rout1 = ro2 ||ro4

M.H. Perrott 7
 Derivation of Rout1 (Incorrect Approach)

ro5

-vid/2 vid/2
M1 M2

ro2 (1+gm2 1 ) 2ro2

gm1
ro4
1
gm3 M4

 Application of Thevenin analysis seems to imply that

Rout1 = 2ro2||ro4

- Why is this incorrect?

M.H. Perrott 8
 Derivation of Rout1 (Correct Approach)

ro5

i1
M1 M2
vtest itest = i1 + i2
i 1= 2ro2
i1 2ro2
i2 ro4
vtest
1
gm3 M4

vtest
i2 i1 + r
o4

 Correct approach includes the impact of the current

mirror feedback
vtest vtest vtest
itest = i1 + i2 = i1 + i1 + =2 +
ro4 2ro2 ro4
⇒ Rout1 = ro2||ro4
M.H. Perrott 9
 Derivation of Gm1
incremental ground

-vid/2 vid/2
M1 M2
i1 i2 iout = i1 + i2

i1
1
gm3 M4

 For differential input, we can approximate the source

of M1 and M2 as being at incremental ground
gm1
i1 = −gm1(−vid /2) = vid
2
gm2 gm1
i2 = gm2(vid/2) = vid = vid
2 2
⇒ iout = gm1vid ⇒ Gm1 = gm1 = gm2
M.H. Perrott 10
 Derivation of Zin
incremental ground
Cgs1 Cgs2

-vid/2 M1 M2 vid/2 -vid/2 vid/2

Cgs1 Cgs2

-vid/2 vid/2
1
gm3 M4 Cgs1 Cgs2

 For differential input, we can -vid/2 vid/2

simplify the input capacitance Cgs1/2
calculation through the steps
shown at the right
vid
1 1 Cgs1/2
⇒ Zin1 = =
sCgs1/2 sCgs2/2
M.H. Perrott 11
 Second Stage Analysis

M7
Second Stage Two-Port Model
Ibias2

Vout
vin2 V2 Zin2 Gm2V2 Rout2 CL vout
CL

Vin2
M6

 Two port model derivation is straightforward

- This is a common source amplifier
1
Zin2 =
sCgs6
Gm2 = gm6
Rout2 = ro6 ||ro7
M.H. Perrott 12
 Overall Opamp Model
First Stage Two-Port Model Second Stage Two-Port Model

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

 Overall transfer function

vout (s) K
H(s) = =
vid(s) (1 + s/wp1)(1 + s/wp2)
- DC gain
K = gm1(ro2||ro4 )gm6(ro6||ro7 )
- Poles
1 1
wp1 = wp2 =
(ro2||ro4 )Cgs6 (ro6||ro7 )CL
 In general, wp2 << wp1 since CL >> Cgs6
M.H. Perrott 13
 Consider The Dominant Pole To Be wp2

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB

w (rad/s)
1 w0
wp2 =
(ro6||ro7)CL

K gm1(ro2||ro4 )gm6(ro6||ro7 )
H(s) = =
1 + s/wp2 1 + s(ro6||ro7 )CL
 At frequencies >> wp2
gm1(ro2||ro4 )gm6 gm1(ro2||ro4 )gm6
H(s) ≈ ⇒ wo ≈
sCL CL

We want wp1 > w0 for good phase margin with unity gain feedback
M.H. Perrott 14
 Key Issue for Achieving Adequate Phase Margin

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB

w (rad/s)
1 w0 1
wp2 = wp1 =
(ro6||ro7)CL (ro2||ro4)Cgs6

gm1(ro2||ro4 )gm6
wo ≈
CL
 To achieve wp1 > w0
1
wp1 = > wo ⇒ CL > gm1gm6(ro2 ||ro4 )2Cgs6
(ro2||ro4 )Cgs6
- We need a very large value of C relative to Cgs6
L
 This will generally be impractical!
M.H. Perrott 15
 Pole Splitting Using a Compensation Capacitor
CM Cc

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

 Consider placing capacitor Cc across the second stage

- Load capacitance seen by stage 1 becomes roughly
CM = (1 + gm6(ro6||ro7 ))Cc ≈ gm6(ro6||ro7 )Cc

 This large Miller capacitance now causes wp1 to become

dramatically lower such that it forms the dominant pole
1 1
wp1 ≈ ≈
(ro2 ||ro4 )CM (ro2||ro4 )gm6(ro6||ro7 )Cc
 We will see that wp2 actually increases in frequency!
M.H. Perrott 16
 Pole Splitting Using a Compensation Capacitor (Part 2)
CM Cc Rth_C
L

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

 Assuming wp1 forms the dominant pole, we can

approximate Cc as a short when calculating wp2
1
Rth CL ≈
gm6
1 gm6
⇒ wp2 ≈ =
(1/gm6)(Cgs6 + CL) Cgs6 + CL
- Note: we must have C c >> Cgs6 for this to be accurate
 The inclusion of capacitor Cc has led to wp2
increasing in frequency
M.H. Perrott 17
 Impact of Pole Splitting using Compensation Cap

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

w (rad/s)

1 gm6
wp1 = wp2 =
(ro2||ro4)gm6(ro6||ro7)Cc Cgs6+CL
1 1
wp2 = wp1 =
(ro6||ro7)CL (ro2||ro4)Cgs6

 Pole splitting allows the dominant pole frequency to

be dramatically decreased and the main parasitic pole
to be dramatically increased
- We can achieve higher unity gain frequency with
improved phase margin and with reasonable area
M.H. Perrott 18
 Unity Gain Frequency with Compensation Cap

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB
w (rad/s)
1 w0 gm6
wp1 = wp2 =
(ro2||ro4)gm6(ro6||ro7)Cc Cgs6+CL

K gm1(ro2 ||ro4 )gm6(ro6 ||ro7 )

H(s) = =
1 + s/wp1 1 + s(ro2||ro4)gm6(ro6||ro7 )Cc
 At frequencies >> wp1
gm1(ro2||ro4 )gm6(ro6||ro7 ) gm1
H(s) ≈ ⇒ wo ≈
s(ro2 ||ro4)gm6(ro6||ro7 )Cc Cc

We want wp2 > w0 for good phase margin with unity gain feedback
M.H. Perrott 19
 Key Constraints for Achieving Adequate Phase Margin

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB
w (rad/s)
1 w0 gm6
wp1 = wp2 =
(ro2||ro4)gm6(ro6||ro7)Cc Cgs6+CL

gm1
wo ≈
Cc
 To achieve wp2 > w0
gm6 gm1
wp2 = > wo ⇒ Cc > (Cgs6 + CL)
Cgs6 + CL gm6
- Note: we must have C c >> Cgs6 for this to be accurate
M.H. Perrott 20
 More Accurate Calculations Related to Phase Margin

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB
w (rad/s)
1 w0 gm6Cc
wp1 = wp2 =
(ro2||ro4)gm6(ro6||ro7)Cc Cgs6CL+Cc(Cgs6+CL)

gm1
wo ≈
Cc
 To achieve wp2 > w0
à !
gm1 Cgs6CL
wp2 > wo ⇒ Cc > + Cgs6 + CL
gm6 Cc

M.H. Perrott 21
 A More Accurate Transfer Function Model
Cc

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

vout (s) K(1 + s/wz )

H(s) = =
vid(s) (1 + s/wp1)(1 + s/wp2)
K = gm1(ro2||ro4 )gm6(ro6||ro7 )
1
wp1 =
(ro2||ro4 )gm6(ro6||ro7 )Cc
gm6Cc
wp2 =
Cgs6CL + Cc(Cgs6 + CL)
µ ¶
wz = −
gm6  Right half plane (RHP) zero
Cc causes potential stability issues 22
M.H. Perrott
 Plotting the Magnitude of a RHP Zero

 Plot the magnitude response of right half plane wz

20 log |Az (w)| = 20 log |1 − jw/wz |

- For w << |w |: z 20 log |Az (w)| ≈ 20 log |1| = 0

- For w >> |w |: z 20 log |Az (w)| ≈ 20 log |w/wz |

20log|Az(ω)|

20 dB/decade

0 dB ω
ωz

Magnitude response is the same as for left half plane zero

M.H. Perrott 23
 Plotting the Phase of a RHP Zero

 Plot the phase response of right half plane wz

6 Az (w) = 6 (1 − jw/wz ) = arctan (−w/wz )

- For w << |w |: z
6 Az (w) ≈ arctan (0) = 0◦

- For w = |w |:z
6 Az (w) ≈ arctan (−1) = −45◦

- For w >> |w |: z
6 Az (w) ≈ arctan (−∞) = −90◦
ωz/10 ωz ωz∗10
0o ω

Az(ω) -45o

o
-90

Phase response is negative rather than positive (similar to pole)

M.H. Perrott 24
 Phase Margin Degradation Due to RHP Zero

20log Vout/Vid

0dB
w (rad/s)
gm1 gm6
w0 = |wz| =
Cc Cc
gm6
wp2 =
Cgs6+CL
 Since the RHP zero adds negative phase (similar to
pole), it reduces phase margin
- We want: |wz | À wo ⇒ gm6 À gm1
 This is not a desirable constraint
M.H. Perrott 25
 Adding a Compensation Resistor
Rc Cc

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

vout (s) K(1 + s/wz )

H(s) = =
vid(s) (1 + s/wp1)(1 + s/wp2)
K = gm1(ro2||ro4 )gm6(ro6||ro7 )
 RHP zero effectively
1
wp1 = removed if Rc = 1/gm6
(ro2||ro4 )gm6(ro6||ro7 )Cc
 Improved phase
gm6Cc margin possible with
wp2 =
Cgs6CL + Cc(Cgs6 + CL) Rc > 1/gm6

wz = −
gm6
µ
1
¶
- See Johns&Martin,
Cc 1 − gm6Rc pp. 242-244
M.H. Perrott 26
 Implementing Rc with a Triode Device

M8 M7
M5

Iref Vin- Vin+ Vout

M1 M2
CL
M9
Cc

M3 M4 M6

 More compact implementation than a poly resistor

 Triode channel resistance can somewhat track 1/gm6
across process and temperature variations
 Key issue: supply sensitivity
- See pp. 246-248 of Johns&Martin for solutions to this issue
M.H. Perrott 27
 Calculations for Triode Compensation Resistor
Vdd

M9
Cc

M4 M6

 Triode resistance calculated as

1
Rc =
μnCox(W9/L9)(Vgs9 − VT H )
1
=
μn Cox(W9/L9)(Vdd − Vgs6 − VT H )
 Assuming square law, 1/gm6 is calculated as
1 1
=
gm6 μnCox(W6/L6)(Vgs6 − VT H )

Depending on Vdd, Rc can track 1/gm6 across process/temp

M.H. Perrott 28
 Summary

 Basic two-stage CMOS opamp is a workhorse for many

moderate performance analog applications
- Relatively simple structure with reasonable performance
 Key issue: two-stages lead to two poles that are
relatively close to each other
- This leads to very poor phase margin unless very large
CL is used
 Inclusion of a compensation capacitor across the
second stage leads to pole splitting such that stable
performance can be achieved with reasonable area
- A compensation resistor is also desirable to help
eliminate the impact of a RHP zero that occurs due to
compensation

We will use the basic two stage CMOS opamp structure

to explore various opamp specifications in the next lecture
M.H. Perrott 29