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1396 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.

5, MAY 2011

Hysteresis Modulation of Multilevel Inverters


Anshuman Shukla, Member, IEEE, Arindam Ghosh, Fellow, IEEE, and Avinash Joshi

Abstract—The hysteresis modulation for power electronic con-


verters is attractive in many different applications because of its
unmatched dynamic response and wide command-tracking band-
width. Its application and benefits for two-level converters are well
understood, but the extension of this strategy to multilevel convert-
ers is still under development. This paper summarizes and reviews
the various hysteresis modulation approaches available in the liter-
ature for multilevel converters. The pros and cons of various tech-
niques are described and compared for tracking the reference sig-
nal in order to attain an adequate switching optimization, excellent
dynamic responses and high accuracy in steady-state operation. By
using the recently developed multilevel hysteresis modulation ap-
proaches, the advantages of using several accessible dc potentials Fig. 1. (a) Two-level half-bridge inverter. (b) Two-level hysteresis control.
in a multilevel inverter have been fully exploited. All of these hys-
teresis modulation approaches are tested for tracking a current
the dc link of inverter and their common point (n, neutral point)
reference when applied to a five-level inverter. The relevant simu-
lation and experimental results are also presented. This study will is grounded. The net controllable output voltage of the inverter
provide a useful framework and point of reference for the future is uVdc /2, where u is defined as the control input and represents
development of hysteresis modulation for multilevel converters. the switching logic of inverter. It assumes the values +1 and
Index Terms—Hysteresis modulation, multiband (MB), multi- −1 for the two-level inverter of Fig. 1(a). The inverter output
offset band (MOB), multilevel converter, time-based (TB). voltage van can be represented as follows:
uVdc dia
van = = Ria + L + vback (1)
2 dt
I. INTRODUCTION
where ia is the load current, vback is the back EMF voltage, and
HE hysteresis modulation for power electronic converters
T are preferred for applications, where performance require-
ments are more demanding such as to achieve good dynamic
L and R are the load inductance and resistance, respectively
[see Fig. 1(a)]. As vback increases or as larger reference current
slopes are required, larger average values of van need to be
response, unconditional stability, and wide command-tracking used. Since the voltage across the load resistance is often small,
bandwidth [1], [2]. In this approach, the controlled system vari- this value can often be neglected. Introducing a term diref /dt,
able is compared against hysteresis band(s) to create the switch- where iref is the current reference to be tracked, (1) becomes as
ing commands for the converter. This control has been widely follows:
used to control the conventional two-level converter, showing
d(ia − iref ) uVdc /2 − vback diref
its robustness and simplicity in a lot of applications [3]–[13]. A ≈ − . (2)
dt L dt
brief description of the standard two-level hysteresis control for
output current regulation is presented in the following. It is evident from (2) that the current error (ce = ia − iref ) can
The objective of standard two-level hysteresis current con- be reduced by increasing or decreasing van , depending on the
trol is to switch the converter transistors in such a manner that polarity of ce . Fig. 1(b) represents the implementation logic for
the converter load current tracks a reference within a specified this correct voltage-level selection for a two-level inverter using
hysteresis band. Consider a single-phase half-bridge inverter, as hysteresis control. It can be seen that as the measured current
shown in Fig. 1(a) for two-level hysteresis current control. In (ia ) becomes greater than its reference (iref ) by the hysteresis
Fig. 1, two dc sources of magnitudes Vdc /2 are considered at band “h,” the inverter output voltage (uVdc /2) is switched to its
lowest level (−Vdc /2, u = −1) in order to decrease the current
[according to (1)]. Likewise, when ia becomes less than iref by
“h”, uVdc /2 is switched to its highest level (Vdc /2, u = +1)
Manuscript received March 2, 2010; revised July 28, 2010; accepted in order to increase the current. For the inverter of Fig. 1(a), u
September 9, 2010. Date of current version June 22, 2011. Recommended assumes the value +1 for the switching logic S1 = 1, S2 = 0
for Publication by Associate Editor Leon M. Tolbert.
A. Shukla is with Power Technology, ABB Corporate Research, and −1 for S1 = 0 and S2 = 1. A three-phase system can also
Vasteras 72178, Sweden (e-mail: anshuman.shukla@se.abb.com, anshukla@ be simply implemented using three independent single-phase
gmail.com). hysteresis current regulators.
A. Ghosh is with School of Engineering Systems, Queensland University of
Technology, Brisbane 4001, Australia (e-mail: a.ghosh@qut.edu.au). Based on the two-level hysteresis control logic described ear-
A. Joshi is with Department of Electrical Engineering, Indian Institute of lier, the control input u can be defined as follows:
Technology Kanpur, Kanpur 208016, India (e-mail: ajoshi@iitk.ac.in).
Color versions of one or more of the figures in this paper are available online if (ce (t) ≥ +h) , then u(t) = −1
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2010.2082001 else if (ce (t) ≤ −h) , then u(t) = +1. (3)

0885-8993/$26.00 © 2011 IEEE


SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1397

Fig. 2. (a) Five-level cascaded H-bridge inverter. (b) Five-level diode-clamped


inverter. (c) Five-level flying capacitor inverter.

Fig. 3. MB five-level hysteresis current control.

It should be noted that h is a suitable hysteresis band, whose To implement the logic for correct voltage-level selection,
size is determined by the maximum allowable switching fre- various schemes available in the literature have been described
quency of the switching devices, as well as the maximum per- in the following sections on the basis of a single-phase five-level
mitted level of current distortion. A low value of h may lead to inverter. In Section II, the multiband (MB) MHM scheme is
increased switching actions, henceforth, larger switching losses, presented, which has the feature of floating voltage levels at the
while a large value of h may result in increased distortion in the boundaries of the band with symmetric inner bands placement.
controlled current. Therefore, a tradeoff is always required in In Section III, the multioffset-band (MOB) approach is pre-
designing the hysteresis band size. sented, which allots fixed voltage levels at the band boundaries
As only two dc voltage levels are available, the two-level hys- and needs to check the slope as well as the band region of the
teresis control is relatively straightforward with each hysteresis current error. A modification to this approach is also presented,
boundary being mapped essentially to one converter-phase-leg so that it can be easily extended for higher level inverter systems
switched state. However, for multilevel converters, as a larger and tracks the reference more efficiently. Further, a time-based
number of output voltage levels are available, the task is to select (TB) approach for MHM is presented in Section IV, which can
a particular voltage-level output to force the control variable to be used to put a limit on maximum switching frequency as well
zero on an instantaneous basis once it exceeds certain bound- as to achieve improved performances. The detailed simulation
ing limits. Therefore, a multilevel hysteresis modulator (MHM) and experimental results for all these schemes have been pre-
requires additional logic to select the appropriate voltage level sented to validate their functioning. Furthermore, a comparative
at any time instant so as to confine the control signal within a evaluation of these schemes has been also presented.
specified hysteresis band.
The starting point toward the design of an adequate MHM
could be the following: according to the instantaneous value II. MB HYSTERESIS MODULATION
of the controlled system variable (uc ), the controller should The MB hysteresis modulation scheme for the multilevel con-
suggest what is the most suitable voltage level required. At any verters uses symmetrical hysteresis bands to control the switch-
instant, when uc exceeds a hysteresis limit, the next higher (or ing so that the inner band causes switching between adjacent
lower) voltage level should be selected in an attempt to force it levels, while the outer band causes an additional switching level
within the specified limits. However, this new converter voltage change whenever necessary. The process, first proposed in [15]
level may not be adequate to return uc to the specified limits. and later used in [22], [26], [31], [32], is shown in Fig. 3 in the
When this happens, the converter should switch to the next form of current regulation. Whenever the current error crosses
higher (or lower as appropriate) voltage level, and the process the inner boundary B, the inverter output is decreased or in-
should cease only when the correct voltage level is selected creased by one level (depending on which hysteresis boundary
that reverses the direction of uc . To exemplify it further, one has just been crossed). Generally, this voltage change will cause
of the standard multilevel inverter topologies, the single-phase- the current error to reverse its direction without reaching the
leg five-level configurations of which are shown in Fig. 2, can next outer band. However, if the error does not reverse, it will
be considered [14]. For a five-level inverter, van in (1) may be continue through the boundary of B to the next outer boundary
defined as van = nVdc , where n = 1/2, 1/4, 0, −1/4, and −1/2, (placed at ΔB out of B). At this point, next higher or lower level
as a five-level inverter may select between voltage levels Vdc /2, voltage will be switched. This process continues as discussed
Vdc /4, 0, −Vdc /4, and −Vdc /2 for the net dc-link voltage of earlier until the current error direction reverses. It is important
Vdc . Then, in a similar manner as described earlier, ce can be to note that if the voltage level applied at a boundary crossing of
kept limited to a specified band by selecting a higher or lower the current error is insufficient to force the error back, no next
voltage level than its present output depending on the polarity voltage level is applied as the error again crosses this boundary
of ce [15]–[34]. next time after the previous voltage level change with the same
1398 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

Fig. 4. MB five-level hysteresis modulation. (a) Current error and hysteresis


band plots. (b) Inverter output voltage.

slope. The error in that case is allowed to go until the next volt-
age level change at next higher or lower boundary crossing of
the error to force it back as is evident from Fig. 3. Fig. 5. Transient performance of MB scheme. (a) Current error and hysteresis
band plots. (b) Reference and measured load current. (c) Inverter output voltage.
To further illustrate the principle of MB scheme, simulation
studies are performed on a five-level inverter, supplying an RL
load of R = 35 Ω and L = 30 mH with the dc-link voltage of
80 V. The back EMF voltage (vback ) is taken as zero and the
inverter devices are assumed nearly ideal. The output current
of inverter (ia ) is controlled using the MB hysteresis scheme
(see Fig. 3) to follow a sinusoidal reference having peak-to-
peak values of ±1.0 A. Corresponding to Fig. 3, the hysteresis
band sizes are taken to be B = 0.04 A and B1 = B2 = 0.02 A.
These values are taken for simplicity by following the consid-
erations presented in [16]. All the simulation results presented
in this paper for hysteresis modulation have been obtained by
using the same set of parameters for a five-level inverter. Fig. 4
shows the simulation results obtained with the MB scheme. It
is evident that the error is contained within the allotted bands
by the corresponding voltage levels appearing at the output of
the inverter. The error trajectory can be similarly followed by
referring it from Fig. 3.
Fig. 5 shows the simulation results obtained under the same
load conditions as earlier, but imposing a current reference of Fig. 6. Overall structure of the experimental setup.
halved amplitude at 45 ms in the simulation run, and thus,
testing it for a transient condition. If the rms value of the current
transient response of the current regulator can be appreciated
required is lower (the load being the same), the rms value of the
from the results shown in Fig. 5(b).
voltage must be lower. Fig. 5 shows that the control technique
is self-adapting in an automatic and natural way; therefore, the
A. Experimental Setup
converter feeds the load by using the lower voltages levels only
[±Vdc /4 and 0, Fig. 5(c)]. It is also seen from Fig. 5(c) that An experimental setup is used to test the MHM schemes dis-
as soon as the step reference change occurs, the corresponding cussed in this paper. A prototype of a single-phase five-level
extreme voltage level (−Vdc /2) appears at output of the inverter insulated gate bipolar transistor (IGBT)-based diode-clamped
to rapidly force the current error back within the specified bands. inverter is built in the laboratory. The overall structure of the
It should be noted that if the change in reference is not that large, experimental setup is shown in Fig. 6. The main power cir-
following a step change in the demanded current, the controller cuits consist of a single-phase five-level voltage source diode-
will remain in the corresponding switching state required to clamped inverter, load, and dc-link circuit. The inverter dc bus is
follow the reference as closely as possible until the current supported by a separately controllable dc supply obtained from
error reaches the hysteresis band. Hence, the advantages of a a single-phase transformer and diode rectifier circuit. The dc-
multilevel topology are fully exploited by this scheme. The fast- link voltage and load parameters of the inverter are kept same as
SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1399

considered earlier in the simulation studies, i.e., Vdc = 80 V and


R = 35 Ω, L = 30 mH, respectively. In Fig. 6, HV2–HV5 de-
notes the Hall effect voltage transducers for sensing the dc-link
capacitor voltages and HC1 represents the Hall effect current
transducer sensing the inverter load current (ia ). Each semi-
conductor switch shown in Fig. 6 consists of an IGBT with
an antiparallel diode. The IGBT modules used is Mitsubishi
CM75DY-24 H. This is a 1200 V/75 A IGBT with two IGBTs/
diodes in each module. For simplicity, the same IGBT modules
are also used as clamping diodes with a shorted gate in the in- Fig. 7. Experimental results showing the MB hysteresis modulation perfor-
mance. (a) Inverter output voltage and current error. (b) Inverter output voltage
verter, as shown in Fig. 6. The presence of back EMF would and controlled load current.
serve to create more variation in switching frequency, but with-
out affecting the nature of the current error trajectory. Therefore,
for simplicity, back EMF voltage source has not been used. with the output voltage. By comparing the experimental results
In the experimental setup, a chopper circuit for the dc capaci- with those of the simulation results presented earlier, it can be
tor voltages equalization has also been used, as shown in Fig. 6. said that the experimental results match closely with the simu-
Its working principles and operational features can be referred lation results, as expected.
from [35]. Without any dedicated control or additional hardware, An advantage of this MB hysteresis control is that the (n − 1)
the dc-link capacitor voltages tend to unbalance under most of bands used here for an n-level inverter center about the zero-
the operating conditions in a diode-clamped inverter [35], [36]. error axis. In this case, the average value of the current error
This chopper circuit of Fig. 6 keeps the dc-link capacitor volt- approaches zero even when current ripple periods are consid-
ages balanced so that the inverter is able to generate five different ered [15]. Therefore, no dc-tracking error is introduced into
and correct voltage levels. It is also important to mention here the output current (no analog offset compensation circuitry
that the chopper action is unaffected by the different hysteresis required).
modulation methods used in this paper. The dc-link capacitors
are Cd1 = Cd2 = Cd3 = Cd4 = 220 μF and the chopper circuit III. MOB HYSTERESIS MODULATION
parameters are R1 = R2 = 2.0 Ω and L1 = L2 = 20 mH. Fur- As opposed to the MB scheme, which uses symmetrically
ther structural and operational details of the chopper are not placed hysteresis bands for current error regulation, the MOB
given here as these are not in the context of this paper. scheme uses the bands placed with an offset around the zero-
In Fig. 6, the block diagram for PC interfacing and other current error line. The advantage of using the offsets is that
controllers are also shown. The low-voltage signals from the different bands can be easily implemented. Also, the corre-
transducers connected to the power circuits are used as inputs sponding logic can also be easily programmed/implemented in
to various controllers. The inverter load current signal is ac- a way that if the voltage appearing at the boundary of a band
quired by a PC (P−1 V, 2.4 GHz) through AD converter (ADC) is insufficient to force the error back, it is allowed to move to
channels of a standard data acquisition card (NIDAQmx PCI- the other band. As opposed to the previously presented scheme,
6259) [37]. A sinusoidal reference input (iref ) is also fed through fixed voltage levels are applied in MOB scheme as the current
the ADC channels. Based on these quantities, a program writ- error crosses a boundary of the band with a certain slope. In this
ten in Borland C++ is implemented for the control tasks. The section, first the conventional MOB scheme is presented, and
corresponding switching decision signals are generated at the then, its modified version is presented, which offers improved
digital-output port of the DAQ and are passed to the IGBT performances.
driver circuits after introducing a lockout delay using blanking
circuits. IGBTs require gate voltage signal in order to estab-
lish collector to emitter conduction or nonconduction. A single- A. Conventional MOB Hysteresis Modulation
phase five-level inverter topology associated with the chopper A MOB scheme was proposed in [17] and [26] on the basis
circuit of Fig. 6 needs 12 gate drivers. Mitsubishi M57959 L of a three-level inverter. In this scheme, the current can be con-
hybrid IGBT driver modules are chosen to perform this task. trolled using n − 1 offest bands for an n-level inverter. Fixed
This is a high-speed component that is endowed with a voltage voltage levels are switched at each of the offset boundaries when
logic-level input and insulated by a high-speed optocoupler that the current error crosses the boundary of an offset band in a di-
protects against the event of a short circuit [38]. rection, away from the zero error line. A possible two-offset
For the MB scheme described earlier, the current refer- band arrangement (B1 , B2 ) for controlling a three-level inverter
ence and hysteresis band sizes are considered same (1.0 A, is shown in Fig. 8. It is shown in the figure that as the error
B = 0.04 A, and B1 = B2 = 0.02 A) as considered earlier in (Ce ) touches the corresponding boundaries of B1 and B2 , fixed
the simulation studies presented. Fig. 7(a) shows the perfor- output voltage levels are switched. The switching takes place
mance of the MB hysteresis current controller. As expected when sign of the error and its slope at the boundary of a band
and described earlier corresponding to the simulation results in are same, and the previous switching had not taken place at the
Fig. 4, the controller is able to keep the current error in the same boundary of the same band. For example, positive error
defined hysteresis band. Fig. 7(b) shows the load current along and positive slope at p1 and negative error and negative slope
1400 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

Fig. 8. Three-level MOB hysteresis modulation.


Fig. 10. MOB five-level hysteresis current control with fixed voltage applied
at the band crossings of the current error. (a) Current error trajectory along with
the allotted bands. (b) Inverter switched output voltage.

To get a further insight into operational performance of the


five-level hysteresis control of Fig. 9, a simulation study is
performed using this scheme with the same inverter parameters,
load parameters, reference current value as considered in the
previous section and the hysteresis band sizes of B1 = B2 =
0.06 A and B3 = B4 = 0.08 A. Fig. 10 shows the simulation
results under this case, where it is evident that this control results
in a poor quality voltage waveform. To justify this observation,
let us first focus on the current error trajectory in Fig. 10(a).
As suggested earlier, between the points ta and tb , the error
Fig. 9. Five-level MOB hysteresis modulation. variation outputs the voltages 0 and +Vdc /4. As the error moves
away from tb , it touches the lower boundary of B1 (see Fig. 10)
at tc . By definition, at tc , 0 voltage level is switched. However,
before tc , the output voltage was +Vdc /4 and at tc , the error
at p2 cause the switching (see Fig. 8). It can be followed that 0 is moving away from the zero line in the negative direction.
voltage level is switched at the inner limits of B1 , B2 , −Vdc /2 Therefore, +Vdc /2 was required to force the error in opposite
at the upper limit of B1 , and +Vdc /2 at the lower limit of B2 . It direction. But due to the logical sequence of control, 0 voltage
can also be seen from Fig. 8 that the selection of voltage levels level is applied at tc , resulting in further increase in the negative
for limiting the current error occurs from lower to higher value slope of the current error away from the zero line. The error then
through a step and without skipping any intermediate level. This touches the lower boundary of B2 , and then, B4 . This results
confirms an optimized use of the available voltage levels. in consecutive switching of +Vdc /4 and +Vdc /2, respectively.
The MOB scheme seems to work well for a three-level in- This operation is repeated in the consecutive switching cycles
verter, as it utilizes all the available voltage states in an optimized and the voltage waveform is degraded. It is also evident that in
manner to confine the current error within the limits defined by this process, the intermediate level +Vdc /4 is skipped as the
the outer boundaries (B1 and B2 in Fig. 8). However, if the same current error travels from tf to the upper boundary of B2 .
scheme with the same logic sequence is applied to any higher It should be noted that since the current error remains in the
level inverter, its optimization is lost [16]. To exemplify it, let allotted bands, the controlled current follows its reference. It is
us consider a five-level multioffset hysteresis current regulation the voltage waveform, which is degraded. However, as is evident
with Fig. 9 showing a possible current error trajectory along from Fig. 10, the error is bounded within a smaller band (B1
with the offset-band arrangements and corresponding switched or B2 ) in the region when switching the voltage levels 0 and
output voltage levels. By following the scheme of [17], it re- ±Vdc /4, while due to the control actions of this scheme, the
quires four bands (B1 − B4 ) and as the current error touches error is bounded within a larger band (B3 or B4 ) in the region
the corresponding boundaries of B1 − B4 , fixed output voltage when it is required to output one of the two extreme voltage
levels are switched. It can be followed that 0 V is switched at the levels (±Vdc /2). This results in variable-tracking performance
lower limits of B1 , B3 and upper limits of B2 , B4 , −Vdc /4 at the in a single cycle of the current waveform itself.
upper limit of B1 , +Vdc /4 at the lower limit of B2 , −Vdc /2 at
the upper limit of B3 and +Vdc /2 at the lower limit of B4 . The
limitation, when using this scheme for a higher level inverter B. Modified MOB Hysteresis Modulation
can be seen by looking at the current error path from F to G. To overcome the drawbacks of the multilevel control of Fig. 9,
It is evident that a voltage-level transition from −Vdc /2 to 0 V a modified MOB (MMOB) hysteresis control is presented [16].
occurs at G, thereby, skipping the level −Vdc /4. This results in The band placement and functioning of MMOB scheme for a
inverter output voltage with large steps and large voltage stress five-level inverter is shown in Fig. 11. In this scheme, the current
across the devices at the switching instants. error is required to be bounded mainly between the bands B1
SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1401

Fig. 12. MMOB five-level hysteresis modulation. (a) Current error and the
hysteresis band plots. (b) Inverter output voltage.

Fig. 11. MMOB five-level hysteresis modulation.

and B2 , which are displaced by a small offset ΔB. Further, two


additional offsets of the same width ΔB are placed out of B1
and B2 to provide a reliable and robust control. In general, a total
number of n − 2 offsets are required for an n-level inverter in
both the positive- and negative-current-error regions. It differs
from the MOB method in the decision logic of output voltage
levels at the crossing points of current error and corresponding
boundaries of the hysteresis bands and also in the total number
of bands required.
In the MMOB approach, the applied output voltage at the band
crossing points of current error is not fixed, but depends on the
previous voltage level, i.e., just before the crossing point. In this
Fig. 13. Transient performance of MMOB modulation. (a) Current error and
scheme, the next voltage level is applied if a positive/negative hysteresis band plots. (b) Reference and measured currents. (c) Inverter output
boundary of B1 or B2 or ΔB is crossed with positive/negative voltage.
slope for the first time. If this action is insufficient, the error will
cross the same boundary second time. In such a situation, no ac-
tion is taken until the next higher or lower boundary of another waveforms using the control scheme of Fig. 11. A compari-
band is reached. This reduces the number of switching. If the cur- son of Fig. 12 with Fig. 10 shows that in the new scheme, the
rent error crosses the positive boundary of a band with positive switching always occurs between adjacent levels and no voltage
slope, next lower (than the previous) voltage level is switched level is skipped. Also, as opposed to MOB scheme, the current-
(e.g., at A in Fig. 11). Similarly, if the error crosses the nega- tracking performance remains uniform throughout a complete
tive boundary of a band with negative slope, next higher (than load current cycle in MMOB scheme (see Fig. 12), as the cur-
the previous) voltage level is switched (e.g., at M in Fig. 11), rent error is mostly bounded within the hysteresis bands of same
with the earlier stated constraints applied. The advantage of width. It should be noted that, in Fig. 10, the controller acts as
MMOB method of Fig. 11 over the MOB method is evident in desired when switching between +Vdc /4, 0, and −Vdc /4 and
the manner that with MMOB method, output voltage quality is degrades when higher voltage levels (±Vdc /2) are needed to
improved and the current follows its reference with minimum be switched. This indicates that fixed voltage-level switching as
change in voltage levels needed. This guarantees that there is in [17] works fine for the three-level inverter and needs modifi-
no skipping of the intermediate voltage levels. It should also be cation (as in Fig. 11) for higher level inverters.
noted that in this scheme, the number of offset bands is decided Fig. 13 shows the simulation results, obtained under the same
by the number of steps needed to switch the voltage from one transient condition, as considered in the previous sections. It is
extreme (+Vdc /2 or −Vdc /2) to another extreme (−Vdc /2 or evident from Fig. 13 that the control technique is self-adapting
+Vdc /2, respectively) as the error travels from positive (nega- in an automatic and natural way in the same manner as discussed
tive) to negative (positive) region. This can be further understood earlier. Hence, the advantages of a multilevel topology are fully
by following the error trajectory from M to Q in Fig. 11. exploited by this scheme as well. The fast-transient response of
Another simulation study is performed using the MMOB the current regulator can be appreciated from the results shown
scheme with the same inverter parameters as considered ear- in Fig. 13(b). As the band sizes are small, it is difficult to dis-
lier and hysteresis band sizes as B1 = B2 = 0.06 A and ΔB = tinguish between the load current and the alternating reference
0.02 A. Fig. 12 shows the results. Similar current error trajec- [dashed line in Fig. 13(b)], which also confirms that the tracking
tory analysis can be performed in Fig. 12 to justify the better is exact.
1402 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

Fig. 15. TB five-level hysteresis current control.

gible phase lag between the load current and its reference may
occur [15]. To counteract this dc offset, an offset compensation
strategy to ensure zero average current error within each switch-
Fig. 14. Experimental results showing the MOB hysteresis modulation per- ing period is required for improved performance. Usually, this is
formances. (a) Inverter output voltage and current error with the MOB method.
(b) Inverter output voltage and current error with the MMOB method. (c) Load achieved by adding a compensating factor of half the hysteresis
current with the MMOB method. (d) Inverter output voltage and load current band offset magnitude to the load current reference [15], [17].
with halved hysteresis band sizes and with the MMOB method. This technique is robust, but has the general limitation of requir-
ing increasingly complex analog circuitry for implementing the
multiple hysteresis bands and offset compensation as the num-
The experimental investigations are carried out to validate the ber of voltage level increases. Therefore, the MOB hysteresis
MOB and MMOB schemes with the same experimental setup method has not found wide applications.
as discussed in the previous section. The system parameters are
same as considered in the simulation studies presented earlier. IV. TB HYSTERESIS MODULATION
Fig. 14(a) shows the performance of MOB modulation. As ex-
As discussed earlier, although the MOB schemes are easy
pected and described earlier corresponding to the simulation
to implement [15], it requires offset compensation signals to
results in Fig. 10, though the controller is able to keep the cur-
be added to the controlled system variable, since the bands are
rent error in the defined hysteresis bands, it suffers from poor
not symmetric about zero. The MB scheme, presented earlier
inverter output voltage due to skipping of the intermediate volt-
in Section II, does not suffer from this steady-state-tracking
age levels. Fig. 14(b) and (c) shows the performance of MMOB
error problem, but may still not have evenly symmetric current
modulator with the same parameters. In Fig. 14(d), the results
error waveform, especially for nonsinusoidal current references.
show the performance of MMOB modulator with halved values
In the following, a TB MHM is first described, which works
of B and ΔB. Its better performance can be appreciated from
on the principle of controlling the system variable within a
the results shown and can be justified from the discussions pre-
single band so that any type of current offset can be avoided.
sented earlier. It should be noted that the load current shown
Then, a modified TB approach for MHM is discussed, which
in Fig. 14(c) is almost same with both the MOB and MMOB
shows much better performances in terms of tracking as well as
methods as both are able to limit the error within the specified
can be used with a limit on the maximum allowable switching
bands. The experimental results confirm the correctness of sim-
frequency.
ulation and validate the similar behaviors described previously
in the simulated cases. It should also be noted that since in both
A. TB Multilevel Hysteresis Modulation
the conditions, the current error is bounded between the allotted
limits, the controlled current waveform in all the cases resem- A TB multilevel hysteresis control scheme was proposed
bles with the one presented in Fig. 14(c). Further, the tracking in [15] to use only one hysteresis band to detect an out-of-
of the reference load current in the two cases can be confirmed bounds current error. Digital logic is used to select the “correct”
by looking at the current errors presented in Fig. 14(a) and (b). voltage level in response. Upon detecting the error exceeding the
As can be seen from Figs. 8–14, one disadvantage of this upper (or lower) hysteresis limit, the inverter output is switched
scheme is that the offset placements of the hysteresis bands about down (or up) one voltage level so as to return the error back to
zero error introduce a steady-state tracking error. In steady state, zero, as earlier. But if the new inverter switched state is inad-
the average value of the current error in Fig. 12(a) approaches equate to reverse the error back to zero, the output is switched
zero only if the fundamental periods are considered. It does further down (or up) until the current-error direction reverses. A
not increase the total harmonic distortion (THD) value of the possible current error trajectory and inverter switched output for
current, but causes a decrease in the fundamental harmonic com- a five-level inverter are shown in Fig. 15. Referring to Fig. 15,
ponent. This problem may become a severe one if more than the objective of this method is to force the current error in a
five voltage levels are to be employed in which case a nonnegli- manner so that it remains within band B. It is evident that the
SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1403

Fig. 16. TB five-level hysteresis modulation. (a) Current error and the hys-
teresis band plots. (b) Inverter output voltage.

inverter output is switched one level up or down as the current


error touches the boundary of B. If this changed output is insuf- Fig. 17. Control details of the TB hysteresis modulation. (a) Current error
ficient to force the error back toward zero (as at W ), next higher and hysteresis band plots. (b) Inverter output voltage. (c) Time interval between
consecutive switching instants (in microsecond).
or lower voltage level is switched at the next crossing point of
the error and the band limit (as at X). From Fig. 15, it is obvious
that the technique does not create the steady-state tracking error
of the MOB approach. switched to provide extra force on the error to return back [e.g.,
To improve the performance and robustness of this technique, −Vdc /2 is switched at tn in Fig. 17 (c)]. In this way, the TB
a current error slope detection algorithm was used in [18] to control is operative to control the current using the n number
switch the voltage levels. An outer band was also placed to allow of available voltage levels for an n-level inverter. Now, at to ,
switching to the extreme voltage levels for rapid current error when a relatively larger change in reference magnitude is im-
reduction during transient conditions (at ΔB out of B, Fig. 15). posed, the current error comes out of the defined outer band at
An additional band placement was also introduced in [19] for tp [see Fig. 17 (a)]. As stated earlier, this outer boundary at ΔB
higher level inverters. Further, a lockout delay (TB control) was below B is placed to allow switching to the extreme voltage
proposed to be added (in [20]) in the switching process for a fixed levels for rapid current error reduction during transient condi-
duration (say, t1 ) immediately after an inverter state changes to tions. Therefore, as can be seen from Fig. 17 (b), the extreme
compensate for short delay between the generation of gating positive voltage level (+Vdc /2) is switched at tp to rapidly force
signals and sensing of the current error and its derivative. This the error back within B. The resulting error trajectory can be
TB approach can be seen in Fig. 15 between the instants Y and similarly analyzed as detailed earlier.
Z. It is evident that as the error keeps on increasing even if Although the technique of [15] with the improvements of
a voltage level change has occurred at Y , after a certain time [18]–[20] offers good performance, it needs to be further modi-
delay (t1 , between the instants Y and Z), another voltage level fied for better performance under all loading conditions and for
change at Z forces the error in the opposite direction. very narrow hysteresis band sizes. Under certain loading condi-
To further illustrate the principle and functioning of the tions and/or for very narrow hysteresis band sizes, the current
scheme of Fig. 15, simulation studies are performed using this error variations are rapid. In these cases, the error may not re-
scheme with the same system conditions as considered earlier verse suddenly at the boundaries of B (if it has to), but may
and B = 0.04 A and ΔB = 0.02 A. Fig. 16 shows the results take some finite time (say, t2 ) depending on the applied volt-
obtained. With the system parameters under consideration, it age level, hysteresis band size, and the load parameters. This
is evident that the current error is confined within band B by type of phenomena may also occur under synchronous detuning
selecting the voltage levels one after another in the manner dis- problem, which may occur in hysteresis control operation [21].
cussed earlier. For these cases, let us suppose t3 be the time interval for which
To look into detail, the functioning of this scheme and ob- the current error slope is positive (or negative). Now, if t3 is
serving the TB control, another simulation study is performed more than the fixed delay t1 (defined earlier), the next higher or
with the same parameters and two small-step changes in the lower voltage level is switched after t1 according to the switch-
reference current magnitude at instants 14.013 ms (tk , Fig. 17) ing logic of [20]. This means that unnecessary voltage-level
and at 14.23 ms (to , Fig. 17) in the simulation run. The value transition has taken place as the voltage level appearing just at
of fixed delay t1 (defined earlier) is taken 0.2 ms. The corre- the boundary of B was sufficient enough to force the current
sponding results are shown in Fig. 17. It can be seen that at tm , error direction (though, after t2 ). Therefore, it can be said that
when the current error crosses the boundary of B, the inverter the current error slope detection with TB control may affect the
switched output voltage (−Vdc /4) is insufficient to force it back hysteresis controller performance depending on various factors.
within B, and therefore, the error keeps on increasing. How- A possible solution is to set a value of fixed delay t1 , which is
ever, when the time period for which the error remains outside large enough for any t3 . This means that the switching process is
B with positive slope exceeds t1 , next lower voltage level is ceased for a large t1 , each time after the inverter output voltage is
1404 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

error reaches at S so that a change in voltage level causes its


reversal. Therefore, in effect, this method replaces the current
error derivative detection control by a number of fixed-width
bands.
Defining the modified scheme of Fig. 18 with respect to the
method of Fig. 15, it can be said that, the modified method re-
places the combined monitoring of the vertical movement of the
current error and horizontal movement of the time (of [20]) by
only the single monitoring of the vertical movement of the cur-
rent error in deciding to switch the next voltage level out of B.
This replacement is logical as the main aim of all the hysteresis
control remains to check the vertical movement of the error (i.e.,
away from the zero current error line). The switching decisions
are taken only at the boundaries of the bands when the current
Fig. 18. Modified TB five-level hysteresis current control.
error moves away from the zero line. At each such crossing, the
inverter output is changed by one step (e.g., from 0 to +Vdc /4,
or to −Vdc /4, etc.). In the lower boundary regions, the out-
switched. However, the value of t1 is required to be tuned based put voltage state changes from lower to higher (i.e., −Vdc /2 to
on the parameters of the selected sensing device and differentia- −Vdc /4, −Vdc /4 to 0, 0 to +Vdc /4, and +Vdc /4 to +Vdc /2) and
tor logic [20]. Further, it has to be sufficiently small considering in the upper boundary regions, from higher to lower (i.e., Vdc /2
the size of ΔB (e.g., for the case when the error moves from the to Vdc /4, Vdc /4 to 0, 0 to −Vdc /4, and −Vdc /4 to −Vdc /2).
boundary of B toward outer boundaries at ΔB, Fig. 15). These At the outermost boundaries, the corresponding extreme output
considerations result in a very small value of t1 . Therefore, for voltage levels (+Vdc /2 and −Vdc /2) are applied for rapid cur-
varying load and under high-switching frequency operation, this rent error reduction during transient conditions. These voltage-
is not a reliable solution. Another limitation of this scheme is level transitions ensure that the controlled current follows its
that the two processes: 1) ceasing of the switching process for reference with minimum control force needed. The switching
t1 after a voltage level change at B and 2) switching the voltage strategy can be further understood from Fig. 18. At point M , the
level if the current error slope is still positive (negative) after t1 current error crosses the lower boundary of B. Before this point,
from a voltage level change at B, are locked through t1 . Since t1 the output voltage state was −Vdc /2. Therefore, the next higher
is mostly dependent upon sensor parameters (which are fixed) voltage level (−Vdc /4) is applied at M . The current error then
and the current error slope is mostly load dependent (which can follows the path as shown, and at the crossing points shown in
vary), the approach certainly lacks robustness. Further, since the figure (i.e., N , etc.), voltage state transition takes place as
this approach needs to measure the derivative of the current mentioned earlier. A total number of (n − 1) bands required for
error, noise amplification may occur at the sensing end of the an n-level inverter in this scheme can be justified by following
controller, which needs extra hardware to filter it out [20]. the current error trajectory in Fig. 18 and the discussions pre-
sented in the earlier presented schemes. It is also clear that it
can efficiently work under varying load conditions as well.
B. Modified TB Hysteresis Modulation Based on the earlier discussion, the switching decisions under
To counter the limitations of the aforementioned TB scheme, this scheme can be defined with respect to Fig. 18 for an n-level
an efficient modified TB multilevel hysteresis control scheme inverter as follows:
was proposed in [16] and is shown in Fig. 18. This approach  
dCe 1
requires (n − 2) outer bands at ΔB from their inner ones for an if Ce ≥ 0 and > 0 , then u(tk ) = u(tk −1 ) +
dt n−1
n-level inverter. Further, the current error slope-detection-based  
control (of [20]) is replaced by the algorithm of detection of dCe 1
else if Ce < 0 and < 0 , then u(tk ) = u(tk −1 ) − .
only sign of the current error slope. The use of extra bands in the dt n−1
modified scheme implies that, for example, if the current error (4)
crosses B with a certain voltage switched at the boundary of B,
the next voltage level will not be switched until the error touches In (4), u(tk ) is the current value of the switching decision,
the outer band at ΔB from B. By doing so, the situation like while u(tk −1 ) is its immediate past value. This can be justified
that discussed in the earlier paragraph can be clearly avoided for from Fig. 18 in which, tk −1 , tk , etc., shown on the horizontal
a sufficient width of ΔB. The TB control, however, is retained axis are the time instants at which Ce crosses the earlier defined
in the control process, though, for a different purpose. This is boundaries of the bands. It can be seen that depending on the sign
for the case when the two consecutive crossings of the current of Ce and dCe /dt, the output voltage level is either increased
error and the band limits are too small timewise. For example, or decreased by Vdc /4, at the crossing points. Note that, the
as shown in Fig. 18, the time interval between the instants P inverter holds its output voltage level until tk , which it attained
and Q is considered smaller than t1 , and therefore, another at tk −1 . It is also to be noted that with Ce > 0, dCe /dt < 0,
voltage level change does not occur at Q. Subsequently, the and with Ce < 0, dCe /dt > 0, no voltage transition takes place
SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1405

Fig. 19. Modified TB five-level hysteresis current control. (a) Current error
and hysteresis band plots. (b) Inverter switched output voltage.

Fig. 20. Control details of modified TB scheme. (a) Current error and hystere-
at the crossing points. This is because, in these regions, the sis band plots. (b) Inverter output voltages. (c) Time interval between consecutive
control signal is heading toward zero line, which implies that switching instants (in microsecond).
the error between the controlled current and its reference value is
reducing with the present output voltage level. Hence, no voltage
transition is required for this. Another point to be noted is that, no applied to have a TB control. Further, the tuning of t1 along with
exact evaluation is needed for the current error slope, as only the B and ΔB should be properly done to have a good harmonic
sign of the current error slope is needed at its crossing points with spectrum of the controlled current and voltage, while also taking
the band limits. At each sampling instant in the measurement into consideration the maximum allowable switching frequency.
process, the current value of the error is compared with its This TB control applied to control the current in this scheme
previous value. A positive value of this difference indicates a can also be applied to the other schemes discussed in previous
positive slope, while the negative value indicates a negative sections.
slope [16]. Therefore, this scheme does not suffer from noise To look into detail, the functioning of this scheme and observe
amplification problem as in [20]. its operation under a transient condition, another simulation
To get further insight into the modified TB scheme of Fig. 18 study is performed with the same parameters and a small-step
and exemplify its working, simulation studies are performed on change in the reference current magnitude at instant 8.4 ms. (say,
a five-level inverter with the current reference and inverter, and tt ) in the simulation run. The value of t1 is taken 40 μs. The
load parameters being the same as considered earlier and with corresponding results are shown in Fig. 20. It can be seen that
hysteresis band sizes of B = 0.04 A and ΔB = 0.02 A. The as the current error comes out of the outermost boundary fol-
value t1 (delay in the TB control) is taken to be 200 μs. This value lowing a step change in reference magnitude, the corresponding
of t1 is purposely taken to be almost equal to the minimum time extreme voltage level −Vdc /2 is switched to rapidly force the
interval between two consecutive switching decisions under the error within the band limits. However, the next higher voltage
given system conditions to have a better viewing of the controller level −Vdc /4 switched at tu is insufficient to force the error
performance. The simulated waveforms are shown in Fig. 19. back. Therefore, it keeps on increasing and crosses the next
The current error variation across the hysteresis bands can be boundary at tv . However, no other voltage-level switching takes
followed from the discussions presented earlier corresponding place at tv as the time interval between tu and tv is less that
to Fig. 18. It is evident that at tq , the error touches the upper t1 = 40 μs [see Fig. 20(c)]. Therefore, the error keeps on in-
boundary of B and the voltage level +Vdc /4 is switched at the creasing and even the next higher voltage level 0, switched at
output of inverter to force the error in the opposite direction. tw , is insufficient to force the error back toward B. As a result,
However, at tr , when the error crosses the lower boundary of the error touches the next allotted boundary at tx and here, the
B, the next higher voltage level is not switched as the time switched voltage +Vdc /2 forces it back toward B. After this,
interval between the instants tq and tr is less than t1 = 200 μs. the consecutive control actions are processed as detailed earlier.
Therefore, the error crosses B at tr and is forced back in the In this way, the n number of output voltage levels control the
opposite direction at ts , i.e., at ΔB from the lower boundary current to track its reference using the allotted hysteresis band
of B, where voltage level +Vdc /2 is switched. In this way, the regions. It should again be noted that the relatively larger val-
current is controlled to follow its reference by using the four ues of t1 in these simulation studies are correspondingly taken
bands for a five-level inverter and a five-level output voltage to highlight the TB control. In practice, its minimum possible
waveform is obtained [see Fig. 19(b)] for a sinusoidal reference value is limited only by the factors discussed earlier.
current. Fig. 21 shows the simulation results, obtained under the same
It is evident from Fig. 19(a) that the TB control is also oper- transient condition, as considered in the previous sections with
ative in this scheme, e.g., between tq and tr . It should be noted the same inverter and load parameters. It is again evident from
that in this scheme, the time differences between two consecu- Fig. 21 that the control technique is self-adapting in an automatic
tive switching is checked each time before a next voltage level is and natural way in the same manner as discussed earlier. Hence,
1406 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

Fig. 21. Transient performance of modified TB scheme. (a) Current error and
the hysteresis band plots. (b) Reference and measured load current. (c) Inverter
output voltage.
Fig. 23. Experimental results of TB five-level hysteresis modulation with
larger band sizes. (a) Inverter output voltage and current error. (b) Inverter
output voltage and load current. (c) Inverter output voltage and time interval
between consecutive switchings.

than t1 . Hence, the error had to cross B and next voltage level
change takes place at pZ , i.e., at ΔB from the lower boundary
of B. The corresponding time intervals between consecutive
switching instants are shown in Figs. 22(c) and 23(c). As detailed
earlier, this value is checked each time before a next voltage level
is applied to have a TB control. By comparing the experimental
results of Fig. 22 with those of the simulation results presented in
the previous section, it can be said that the experimental results
matches closely with the simulation results as expected.

V. COMPARISON OF THE MHM SCHEMES


In the previous sections, various methods for hysteresis mod-
Fig. 22. Experimental results of TB five-level hysteresis modulation with ulation of multilevel converters have been described. As dis-
smaller band sizes. (a) Inverter output voltage and current error. (b) Inverter cussed earlier, though the implementation of MOB method is
output voltage and load current. (c) Inverter output voltage and time interval easier, it introduces a steady-state tracking error due to the offset
between consecutive switchings.
placements of the hysteresis bands. This limitation is particu-
larly more severe in the higher level inverters. To counteract
the advantages of a multilevel topology are fully exploited by this dc offset, an offset compensation strategy to ensure zero
this scheme as well. average current error within each switching period is required
The experimental investigations are carried out to validate for improved performance [15]. The MOB technique is robust,
the TB modulation schemes with the same experimental setup but has the general limitation of requiring increasingly com-
as detailed in the previous sections. The system parameters are plex analog circuitry for implementing the multiple hysteresis
same as considered in the simulation studies corresponding to bands and offset compensation as the number of voltage level
Figs. 19 and 20. In Fig. 22, the experimental results correspond increases [15]. Further, the conventional MOB method has the
to the hysteresis band sizes of B = 0.04 A and ΔB = 0.02 A limitation of skipping of the intermediate voltage level between
as considered earlier, while in Fig. 23, the results correspond to two successive switching for higher level inverter. The MMOB
B = 0.06 A and ΔB = 0.03 A. The results have been obtained method, however, does not suffer from this limitation and can
with two different band sizes to generalize the performance be applied to higher level inverter system as well. However, due
evaluation. It is evident from the figures that the current control is to its main limitation of introducing the steady-state tracking
achieved by using the five voltage levels in the manner discussed error, the MOB method has not found wide applications.
earlier. The value of t1 = 200 μs is taken to be the same as used The MB scheme uses symmetric bands to control the control
in the simulation studies. It can be seen from Fig. 23(a) that variable and has the advantage that it does not create any dc-
the TB control is also operative as the time interval between tracking error, and therefore, no analog offset compensation
the band crossing of the current error at pX and pY is less circuitry is required as opposed to the MOB scheme. However,
SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1407

it may require a more complex digital circuitry to select a voltage TABLE I


ADVANTAGES AND LIMITATIONS OF THE VARIOUS MHM SCHEMES
level when a change is required [15]. This is because it needs
to classify the previous crossing point of the current error with
the boundary of the allotted band, each time at such crossing
points. For example, by referring to Figs. 14 and 15, it can
be seen that when the current error reaches a boundary of the
allotted band with the previous crossing point being on the same
boundary, no voltage-level switching takes place. In this case,
the error travels to another higher or lower boundary placed at
ΔB from the boundary in question to change the output voltage
level. However, if the previous crossing point had occurred at
a different boundary, the voltage-level switching takes place.
Therefore, this method is required to store the information of
previous crossing point, which may require additional logical
circuitry. However, with the various advanced logical device
available, it may be programmed easily. Further, in this scheme,
the current error waveform may still not be evenly symmetric,
especially for nonsinusoidal current references. This is because,
as is evident from Fig. 15, at each transfer of the output voltage-
level zone [e.g., from 0, +Vdc /4 to +Vdc /4, and +Vdc /2 in
Fig. 15 (b)], the current error moves out of the inner band to
the outer band for next voltage level change [see Fig. 15 (a)].
Due to this, a nonsinusoidal or changing current reference may
introduce a net positive or negative shift in the current error, and
therefore, in the controlled current.
The TB method utilizes a single band to control the current The corresponding hysteresis band sizes for the MOB scheme
as discussed earlier. It does not suffer from dc-tracking error is taken B1 = B2 = 0.12 A and B3 = B4 = 0.18 A and for the
problem but does require extra analog and digital circuitry for MB scheme is B = 0.12 A and ΔB = 0.06 A. It should be noted
current error measurement as well as to apply the TB con- that the main band for the current error regulation is taken of
trol [16]. The modified TB approach, however, does not need same widths in these three cases. The simulation studies show
to measure the current error, and therefore, does not suffer from the percent THD values of the controlled current is 5.45% us-
noise amplification problem. Depending on the available num- ing the MOB scheme, 5.54% using the MB scheme, and 4.2%
ber of output-phase voltage levels of the inverter, it requires a using the TB scheme. The better quality of the controlled cur-
number of bands, but with the aim of containing the current rent using the TB scheme is obvious, as it controls the current
error within the main band, i.e., the innermost band only. It error mainly within a single symmetrically placed hysteresis
also does not need to store the information of previous crossing band. Therefore, and also due to its various other advantages as
point, as opposed to the MB scheme. Therefore, the additional detailed earlier, the TB control of Fig. 18 is recommended.
logical or analog circuitry requirement is minimal. Furthermore,
the maximum possible switching frequency may be set by corre-
spondingly designing the width of hysteresis band. The modified VI. CONCLUSION
TB scheme keeps track of the switching duration between suc- This paper summarizes and reviews the various hysteresis
cessive switchings and may be designed to always keep it larger modulation techniques available in the literature for the multi-
than a certain allowed value. This modified TB control can be level converters. This includes, in general, the MB, MOB, and
applied to the other multilevel hysteresis schemes as well [16]. TB hysteresis modulation techniques. To generalize the exist-
The implementation of this TB control may be achieved by using ing MHM techniques for higher level inverters, their modified
a time counter with a programmable logic device or by program- versions have been also discussed. The basic principle of op-
ming it within a computer program itself, as used in this paper. eration and logical sequence of the design choices has been
A summary of the advantages and limitations of various mul- described for each of these schemes. The advantages of using
tilevel hysteresis regulation schemes presented in this paper is various accessible dc voltage levels have been fully exploited
given in Table I. by using these schemes. The various schemes considered in
To compare the tracking performances of the various this paper have been further investigated using simulation and
schemes, simulation studies are performed with the same sys- experimental studies for a five-level inverter system. However,
tem configurations and parameters as taken in the simulation these strategies can easily be extended to any multilevel inverter
studies presented earlier in this section. For achieving compa- structure, even in the case of n-level voltage waveforms and
rable performances, the hysteresis band sizes are taken B = three-phase systems.
0.12 A and ΔB = 0.06 A for the TB scheme of Fig. 18, which This paper also presents a comparative analysis of the var-
is three times as used in the earlier presented simulation studies. ious MHM schemes. Among these schemes, the modified TB
1408 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 5, MAY 2011

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regulation and capacitor voltage balancing schemes for flying capacitor Anshuman Shukla (S’04–M’09) received the
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529, Mar. 2008. Muzaffarpur Institute of Technology, Muzaffarpur,
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PESC, 2000, pp. 33–38. nology Kanpur, Kanpur, India, in 2003 and 2008,
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current controller for multilevel single phase voltage source inverters,” in Since September 2008, he has been with ABB
Proc. IEEE PESC’01, pp. 1845–1850. Corporate Research, Vasteras, Sweden. In 2008, he
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of flying capacitor multilevel inverter and its application in shunt compen- trical Engineering, University of South Carolina,
sation of distribution Systems,” IEEE Trans. Power Del., vol. 22, no. 1, Columbia. His current research interests include modulation and control of
pp. 396–405, Jan. 2007. power electronic converters and new converter topologies.
SHUKLA et al.: HYSTERESIS MODULATION OF MULTILEVEL INVERTERS 1409

Arindam Ghosh (S’80–M’83–SM’93–F’06) re- Avinash Joshi received the Ph.D. degree in electrical
ceived the Ph.D. degree in electrical engineering from engineering from the University of Toronto, Toronto,
the University of Calgary, Calgary, AB, Canada, in ON, Canada, in 1979.
1983. He is currently a Professor of electrical engineer-
He is currently a Professor of power engineering ing at the Indian Institute of Technology Kanpur,
with Queensland University of Technology, Brisbane, Kanpur, India. From 1970 to 1973, he was with the
Australia. From 1985 to 2006, he was with the De- General Electric Company of India Ltd., Calcutta,
partment of Electrical Engineering, Indian Institute India. His research interests include power electron-
of Technology Kanpur, Kanpur, India. His research ics, circuits, digital electronics, and microprocessor
interests include control of power systems and power systems.
electronic devices.
Dr. Ghosh is a Fellow of the Indian National Academy of Engineering.