a 7+ Basi Proceanc UST Athi andthe next chapter we focus onthe processing unit, which executes machine inructions and coordinates the activites of other units. This unit soften called the [struction Set Procesto (SP), or simpy the pocesror. We examine its itera struc- ‘ture and how it pecforms the asks of fetching decoding nd executing instructions of 4 program. The processing unit wsed tobe called the central processing uit (CPU). ‘The tem “cea” isles appropriate today because many moder computer systems ‘includ several processing nis. ‘The organization of processors as evolved over the yeas, driven by developments in technology and the need to provide high performance. A common statgy in the evelopment of high-performance processors is to make vaious functional us op- crate in parallel as much as posible. High-performance processors have « pipelined organization whee the execution of one instruction is stared before the execution of the preceding instructions competed. In anther approach, known as superscalar op- craton, several instructions are fetched and executed at the same time. Pipelining and superscalar architectures are discussed in Chapter 8 n this chapter we concentrate on the basic ideas that are common tall proceso ‘A typical compating task consists of a series of steps specified by a sequence of ‘machine instructions tha constiue a program. An instruction is executed by canying ‘outa sequence of more rudimentary operations. These operations and the means by Which they are controled are the main topic of his chapter. 7.1 SOME FUNDAMENTAL CONCEPTS ‘To excentea program the processor fetches one instruction at time and pcfooms the ‘operations specified. Instruction are fetched from socessive memory locations wat branch ra jump instruction is encountered. The proceasr keeps tack ofthe adress ‘ofthe memory leaton containing the net instruction tobe fetched using the program ‘counter, PC, After fetching an instruction, the contents ofthe PC are updated o point ‘othe next instruction nthe sequence. A branch instruction may fad a difereat value into the PC Another key register inthe processor is the instruction register, IR. Suppose that ‘eachinsnuction comprises 4 bytes, and that itis stored one memory word. Toexecate an instruction, the processor has to perfom the following the steps 1, Fetch the contents ofthe memory lesion pointed toby the PC. The contents of this location are interpreted as an instruction to be executed. Hence, they ae loaded into the IR. Symbolically, this canbe writen as, IR = (PCI) 2. Assuming that the memor is byte addressable, increment the contents ofthe PC by 4 that, Pep] +4 2. Cary out be actions specified bythe instruction in the TR,7.4 Somme FLNONNTAL CONCH ‘In cases where an instruction occupies more than one word, steps 1 and 2 must be repeated as many times as necessary to fetch the complete instruction. These two steps are usualy referred io asthe fetch phase; sep 3 constitutes the execwion phase. ‘Tostudy these operations in det we fist need o examine he internal organization ofthe processor. The main building blacks fa processor were introdced in Figur 2 ‘They canbe organized and interconnected in a variety of way. We will stat with & very simple organization, Later in his chapter and in Chapter 8 we will present more ‘complex structures tht provide high performance. Figure 7.1 shows an organization Figure 71. Sirgobusorgaizoon fhe datapath inside «proceso. aaau ‘enaptan 7+ Basic Procmsnc Unt in wich te sitmetc an logic wit (ALU) and all he registers ar interconnected ‘vin single common ba. This busi itera wo the processor and should not be confused withthe exertal bus at connects the proceso othe memory and VO devin. "Theda and aes ines ofthe extemal memory bs ae shown in Figure 7.1 cone othe inal proceso us vate memory daa register, MDR. and the memory aes reise, MAR, respectively. Regier MDR bat two puts and wo gts Data ay belondd ito MDR ete om he meory bs or rom he tra ‘processor bus. The data stored in MDR may be placed on either bus. The input of MAR 4s connected othe itera ut, and soup scone othe exeal bs. The contol nes ofthe emery bar connected tothe instruction decode nd contol logic lock. This unis responsible foriasig the signals tht ona he operation of allthe ut inside the pressor ud fo interacting with he memory bus ‘The number and use of th proceso registers RO through Ri ~ 1) vary consi ‘erably from one processor to another. Registers may be provided for general-purpose tee by the programmer, Soe may be diated special prose register, sch at index eis o slack poner. Thee register, Y, Zand TEMP in Figure 1, ave rocteen mentioned before. These regis ae transparent tothe programmer, tts, the programmer need nt be coscemed wih tem beaue they are ever reerencod ‘explicitly by any instruction. They are used by the processor for emporary storage caring execution of some insets. These egies are pve usd for sorng data erated ty oe ison fre te by anor inst, The mukiplxer MUX selects eter th ouput of riser ¥ oa constac vale 41 be provided as input A ofthe ALU. The conan 4 i wed to increment he coments ofthe program cour We wl feo te two possible ales of he MUX contol apt Set as Slot and Select forsleting the constant 4 orgie Y, respectively ‘As isrctin execution progresses, data ar transfered fom one register toa cetez often pasting through te ALU wo perfor some ate logic operation. ‘he nstucton decoder end contol logic nit is responsible for inplemeting the a ‘ions specified by the instruction loaded in the IR register. The decoder generates the contol signals needed to selec the register involved and diet the wane of dats The regs, the ALU, andthe imeronnecng bus ae colleivey refered asthe dauapath "With ew exceptions, aninstuctoncante executed perforing one oor of the flowing operons in some specifi sequence ‘+ Tener wor of dat fom on proesorregstero another tothe ALU * Perform an arithmetic or a logic operation and store the result in a processor reper + Fetch the contents of a given memory location and load them into @ processor reser + Stora word of dat from a processor eis into a given memarylction We now cosier in dtl how each ofthese operations is implemented, sing the Simple processor model a Figure 7.