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Spartan-6 FPGA Memory Interface Solutions

User Guide

UG416 (v1.2) March 3, 2010

Spartan-6 FPGA Memory Interface Solutions User Guide UG416 (v1.2) March 3, 2010
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solelywww.xilinx.com UG416 (v1.2) March 3, 2010 " id="pdf-obj-1-4" src="pdf-obj-1-4.jpg">

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

© Copyright 20092010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

l

Date

Version

Revision

12/2/09

1.0

Initial Xilinx release.

2/23/10

1.1

Updated Figure 1-29. Revised the text below the Calibrated Input Termination bullet on page 23. Added Xilinx ISim to first paragraph in Functional Simulation, page 39.

3/3/10

1.2

Added note about device migration to page 24.

Table of Contents

Revision History

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2

Preface: About This Guide

Guide Contents References

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5

5

Additional Resources

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5

Chapter 1: Getting Started

MIG

Overview

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7

System

Requirements

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8

MIG Tool: Step-by-Step Instructions

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8

Setting up a New Project

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8

Launching MIG

. Creating an MCB Design

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Selecting a Memory Standard

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11

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13

Setting Controller Options Setting Memory Device Options

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14

17

Multi-Port Configuration Arbitration Table Programming

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20

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Setting FPGA Options Design Summary

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23

26

Memory Model License

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27

PCB Information

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27

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27

Design Notes Finish

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MIG Directory Structure and File Descriptions

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27

28

Output Directory Structure

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28

Directory and File Contents

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28

<component name>/docs <component name>/example_design/

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28

28

<component name>/user_design

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31

MIG Example Design with Traffic Generator

 

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33

Traffic Generator Operation .

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33

Address as Data Pattern (Default) Hammer Data Pattern Neighbor Data Pattern Walking 1s and Walking 0s Data Pattern PRBS Data Pattern

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34

35

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37

39

. Setting up for Simulation

Functional Simulation

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39

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39

Implementing the Example Design

Top-Level Parameters

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40

Modifying the Example Design

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40

40

Traffic Generator Parameter

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42

Traffic Generator Signal Descriptions

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42

Spartan-6 FPGA Memory Interface Solutions

3

UG416 (v1.2) March 3, 2010

Modifying Port Address Space Custom Command Sequences . . . . . . . . .www.xilinx.com Spartan-6 FPGA Memory Interface Solutions UG416 (v1.2) March 3, 2010 " id="pdf-obj-3-3" src="pdf-obj-3-3.jpg">

Modifying Port Address Space Custom Command Sequences

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46

46

Memory Initialization and Traffic Test Flow

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47

Chapter 2: Debugging MCB Designs

Introduction

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49

Debug Tools

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50

Example Design

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50

Debug Signals

Reference Boards

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50

50

ChipScope Pro Tool

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51

Simulation Debug

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. Additional Debug Signals (Simulation Only)

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