LABORATORIO ELECTRÓNICA 3

PRACTICA 2: MULTIPLEXACION
AUXILIAR: DAVID BARRIENTOS

Luis Antonio Moran Marroquin 199616884

Lester Gabriel Chanta Méndez 201314671
Oscar Giovanni Lopez Lopez 200412955

CODIGO EN VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity practica2 is

Port(

CLK : in STD_LOGIC;

EN : out STD_LOGIC_VECTOR (2 downto 0);

SSD : out STD_LOGIC_VECTOR (7 downto 0)

);

end practica2;

architecture Behavioral of practica2 is

signal numero : integer range 0 to 9;

signal minuto : integer range 0 to 9;

signal decena : integer range 0 to 9;

signal segundo : integer range 0 to 9;

signal contador: integer range 0 to 11999999;

type FSM is (segundos, minutos,inicio,unidad);

signal Estado: FSM;

signal contador2: integer range 0 to 11999999;

begin

process (CLK)

begin

if(rising_edge(clk)) then

case Estado is

When segundos =>

if (contador2=11999999) then

contador2<=0;

if (segundo=9) then

Estado<= minutos;

else

segundo<=segundo+1;

end if;

else

contador2 <= contador2+1;

end if;

When minutos =>

if (decena=5) then

Estado<= unidad;

else
 decena<=decena+1;

segundo<=0;

Estado<= segundos;

end if;

When unidad =>

if (minuto=9) then

Estado<= inicio;

else

minuto<=minuto+1;

decena<=0;

Estado<= segundos;

end if;

When inicio =>

decena<=0;

segundo<=0;

contador2<=0;

minuto<=0;

estado<=segundos;

When Others =>

decena<= 0;

segundo<= 0;
 contador2<=0;

minuto<=0;

end case;

end if;

end process;

PROCESS(CLK)

begin

if (rising_edge(CLK) ) then

if (contador=99999) then

contador <=0;

else

contador <= contador+1;

end if;

Case numero is

When 0=> SSD<="11000000";

When 1=> SSD<="11111001";

When 2=> SSD<="10100100";

When 3=> SSD<="10110000";

When 4=> SSD<="10011001";

When 5=> SSD<="10010010";

When 6=> SSD<="10000010";

When 7=> SSD<="11111000";

When 8=> SSD<="10000000";

When 9=> SSD<="10010000";

 When others => SSD<="11111111";

End case;

if (contador =33333) then

EN<="110";

numero<=segundo;

elsif (contador =66666) then

EN<="101";

numero<=decena;

elsif (contador =99999) then

EN<="011";

numero<=minuto;

end if;

end if;

end process;

end Behavioral;

UCF

# # Clock 12 MHz

NET "Clk" LOC = P129 | IOSTANDARD = LVCMOS33 | PERIOD = 12MHz;

################################################################################
#####################

## Seven Segment Display

################################################################################
#####################

#"SevenSegment[7]"

NET "SSD[0]" LOC = P117 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "SSD[1]" LOC = P116 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "SSD[2]" LOC = P115 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "SSD[3]" LOC = P113 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "SSD[4]" LOC = P112 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "SSD[5]" LOC = P111 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "SSD[6]" LOC = P110 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "SSD[7]" LOC = P114 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "EN[2]" LOC = P124 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "EN[1]" LOC = P121 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;

NET "EN[0]" LOC = P120 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12;