GRE160 Manual 6F2T0179-r0.0

6 F 2 T 0 1 7 9
INSTRUCTION MANUAL
TRANSFORMER PROTECTION RELAY
GRE160
© TOSHIBA Corporation 2014

All Rights Reserved.
( Ver. 0.0 )
6 F 2 T 0 1 7 9
Safety Precautions
Before using this product, be sure to read this chapter carefully.
This chapter describes safety precautions when using the GRE160. Before installing and using the
equipment, read and understand this chapter thoroughly.
Explanation of symbols used

Signal words such as DANGER, WARNING, and two kinds of CAUTION, will be followed by
important safety information that must be carefully reviewed.
DANGER Indicates an imminently hazardous situation which will result in death or serious
injury if you do not follow instructions.
WARNING Indicates a potentially hazardous situation which could result in death or serious
injury if you do not follow instructions.
CAUTION Indicates a potentially hazardous situation which if not avoided, may result in
minor injury or moderate injury.
CAUTION Indicates a potentially hazardous situation which if not avoided, may result in
property damage.
 1 
6 F 2 T 0 1 7 9
DANGER
• Current transformer circuit
Never allow the current transformer (CT) secondary circuit connected to this equipment to be
opened while the primary system is live. Opening the CT circuit will produce a dangerous high
voltage.
WARNING
• Exposed terminals
Do not touch the terminals of this equipment while the power is on, as the high voltage generated is
dangerous.
• Residual voltage
Hazardous voltage can be present in the DC circuit just after switching off the DC power supply. It
takes about 30 seconds for the voltage to discharge.
• Fiber optic (option)

When connecting this equipment via an optical fiber, do not look directly at the optical signal.
CAUTION
• Earth
The earthing terminal of the equipment must be securely earthed.
CAUTION
• Operation conditions
The equipment must only be used within the range of ambient temperature, humidity and dust
detailed in the specification and in an environment free of abnormal vibration.
• Ratings
Before applying AC voltage and current or DC power supply to the equipment, check that they
conform to the equipment ratings.
• Printed circuit board

Do not attach and remove the printed circuit board while the power to the equipment is on, as this
may cause the equipment to malfunction.
• External circuit
When connecting the output contacts of the equipment to an external circuit, carefully check the
supply voltage used and prevent the connected circuit from overheating.
• Power supply
If power has not been supplied to the relay for two days or more, then all fault, event and disturbance
records and the internal clock may be cleared soon after restoring the power. This is because the
back-up RAM may have discharged and may contain uncertain data.
 2 
6 F 2 T 0 1 7 9
• Connection cable
Carefully handle the connection cable without applying excessive force.
• Modification
Do not modify this equipment, as this may cause the equipment to malfunction, and any such
modifications will invalidate the warranty.
• Disposal
This product does not contain expendable supplies nor parts that can be recycled. When disposing of
this equipment, do so in a safe manner according to local regulations as an industrial waste. If any
points are unclear, please contact our sales representatives.
• Plastics material
This product contains the following plastics material.
- Polycarbonate + ABS
 3 
6 F 2 T 0 1 7 9
Contents
Safety Precautions 1
1. Introduction 8
2. Application Notes 10
2.1 Protection Scheme 10
2.2 Current Differential Protection 11
2.2.1 Differential Scheme 11
2.2.2 Stability for CT Saturation during Through-fault Conditions 13
2.2.3 Matching of CT Secondary Currents 15
2.2.4 Connection between CT Secondary Circuit and the GRE160 18
2.2.5 Setting 19
2.3 Restricted Earth Fault Protection 25
2.4 Overcurrent Protection 29
2.5 Negative Sequence Overcurrent Protection 33
2.6 Thermal Overload Protection 35
2.7 Breaker Failure Protection 37
2.8 Inrush Current Detector 41
2.9 Overvoltage Protection 42
2.10 Undervoltage Protection 45
2.11 Frequency Protection 48
2.11.1 Frequency element 48
2.11.2 Frequency rate-of-change element 50
2.11.3 Trip Circuit 51
2.12 Overexcitation Protection 52
2.13 Voltage Controled Overcurrent Protection 54
2.14 Trip by External Devices 57
2.15 Tripping Output 58
2.16 Characteristics of Measuring Elements 59
2.16.1 Percentage Current Differential Element DIF 59
2.16.2 High-set Overcurrent Element HOC 60
2.16.3 Restricted Earth Fault Element REF 60
2.16.4 Inverse Time Overcurrent Element OCI and EFI 62
2.16.5 Definite Time Overcurrent element OC and EF 62
2.16.6 Thermal Overload Element THR 63
2.16.7 Overexcitation Element V/F 64
3. Technical Description 65
3.1 Hardware Description 65
3.1.1 Outline of Hardware Modules 65
3.2 Input and Output Signals 67
3.2.1 Input Signals 67
3.2.2 Binary Input Signals 68
 4 
6 F 2 T 0 1 7 9
3.2.3 Binary Output Signals 69

3.2.3 PLC (Programmable Logic Controller) Function 71
3.3 Automatic Supervision 72
3.3.1 Basic Concept of Supervision 72
3.3.2 Relay Monitoring and Testing 72
3.3.3 Trip Circuit Supervision 73
3.3.6 Circuit Breaker Monitoring 74
3.3.5 Failure Alarms 75
3.3.8 Trip Blocking 76
3.3.7 Setting 77
3.4 Recording Function 78
3.4.1 Fault Recording 78
3.4.2 Event Recording 79
3.4.3 Disturbance Recording 79
3.5 Metering Function 81
4. User Interface 83
4.1 Outline of User Interface 83
4.1.1 Front Panel 83
4.1.2 Communication Ports 85
4.2 Operation of the User Interface 86
4.2.1 LCD and LED Displays 86
4.2.2 Relay Menu 90
4.2.3 Displaying Records 92
4.2.4 Displaying the Status 100
4.2.5 Viewing the Settings 108
4.2.6 Changing the Settings 109
4.2.7 Control 156
4.2.8 Testing 158
4.3 Personal Computer Interface 162
4.4 MODBUS Interface 162
4.5 IEC 60870-5-103 Interface 162
4.6 IEC 61850 Communication _ Option 162
4.7 Clock Function 163
4.8 Special Mode 163
5. Installation 165
5.1 Receipt of Relays 165
5.2 Relay Mounting 165
5.2.1 Flush Mounting 165
5.3 Electrostatic Discharge 167
5.4 Handling Precautions 167
5.5 External Connections 167
6. Commissioning and Maintenance 168
6.1 Outline of Commissioning Tests 168
 5 
6 F 2 T 0 1 7 9
6.2 Cautions 168

6.2.1 Safety Precautions 168
6.2.2 Cautions on Tests 169
6.3 Preparations 169
6.4 Hardware Tests 170
6.4.1 User Interfaces 170
6.4.2 Binary Input Circuit 171
6.4.3 Binary Output Circuit 172
6.4.4 AC Input Circuits 173
6.5 Function Test 174
6.5.1 Measuring Element 174
6.5.2 Protection Scheme 189
6.5.3 Metering and Recording 189
6.6 Conjunctive Tests 190
6.6.1 On Load Test 190
6.6.2 Tripping Circuit Test 191
6.7 Maintenance 193
6.7.1 Regular Testing 193
6.7.2 Failure Tracing and Repair 193
6.7.3 Replacing Failed Modules 194
6.7.4 Resumption of Service 194
6.7.5 Storage 194
7. Putting Relay into Service 195
Appendix A 196
Block Diagram 196
Appendix B 198
Signal List 198
Appendix C 231
Programmable Reset Characteristics Programmable Reset Characteristics 231
Appendix D 233
Binary Output Default Setting List 233
Appendix E 235
Details of Relay Menu and LCD & Keypad Operation 235
Appendix F 248
Case Outline 248
Appendix G 250
External Connections 250
Appendix H 256
Relay Setting Sheet 256
Appendix I 277
Commissioning Test Sheet (sample) 277
 6 
6 F 2 T 0 1 7 9
Appendix J 282
Return Repair Form 282
Appendix K 287
Technical Data 287
Appendix L 296
Setting of REF Element 296
Appendix M 298
Symbols Used in Scheme Logic 298
Appendix N 301
Implementation of Thermal Model to IEC60255-149 301
Appendix Q 304
Inverse Time Characteristics 304
Appendix S 307
Ordering 307
 The data given in this manual are subject to change without notice. (Ver.0.0)
 7 
6 F 2 T 0 1 7 9
1. Introduction
GRE160 provides high-speed transformer and reactor protection, and realises high dependability
and security for diverse faults such as single-phase faults, multi-phase faults, overload and
over-excitation.
GRE160 is used as a main protection and backup protection of the following transformers and
reactors.
• Two-winding power transformers
• Auto-transformers
• Generator-transformer units
GRE160 is designed to provide stability under magnetizing inrush and overexcitation conditions,
applied to two-winding transformers. GRE160 is available for mixed 1A/5A inputs.
Models 100, 101 and 102 provide 2 three-phase current inputs for the current differential protection
applied to two-windinge tanransformers.
Models 200, 201 and 202 provide 2 three-phase current inputs and 2 zero-phase (neutral point)
current inputs for restricted earth fault protection,.
Models 300, 301 and 302 provide 2 three-phase current inputs and one-phase voltage input for
voltage overexitation, frequencym voltage controlled overcurrent protections.
Models 400, 401 and 402 provide 2 three-phase current inputs, 2 zero-phase (neutral point) current
inputs and one-phase voltage inputs.
Models 500, 501 and 502 provide 2 three-phase current inputs, 2 zero-phase (neutral point) current
inputs and four-phase voltage inputs.
All models include multiple, high accuracy, overcurrent protection elements (for phase and/or earth
fault) with inverse time and definite time delay functions.
All models provide continuous monitoring of internal circuits and of software. External circuits are
also monitored, by trip circuit supervision, CT and VT supervision, and CB condition monitoring
features.
A user-friendly HMI is provided through a backlit LCD, programmable LEDs, keypad and
menu-based operating system. PC access is also provided, either for local connection via a
front-mounted USB port. The communication system allows the user to read and modify the relay
settings, and to access data gathered by the relay’s metering and recording functions.
Data available either via the relay HMI or communications ports includes the following functions.
The GRE160 provides the following metering and recording functions.

• Metering
• Fault records
• Event records
• Disturbance records (available via communications ports)
Table 1.1.1 shows the members of the GRE160 series and identifies the functions to be provided by
each member.
 8 
6 F 2 T 0 1 7 9
Table 1.1.1 Series Members and Functions
Model Number GRE160 -

10_A 20_A 30_A 40_A 50_A
Current differential protection DIFT (87T)     
Restricted earth fault protection REF (87G)   
Phase Fault O/C OC(50P, 51P): 1st and 2nd stage Primary / Secondery     
Earth Fault O/C EF(50N, 51N): 1st and 2nd stage Primary / Secondary  (*1)   (*1)  
High-speed O/C HOC 1st     
Thermal Overload (49)     
Negative Phase Sequence Overcurrent NOC(46): 1st and 2nd stage     
Circuit Breaker Fail CBF(50BF)     
Phase Overvoltage OV(59): 1st and 2nd stage   
Phase Undervoltage UV(27): 1st and 2nd stage   
Overexcition protection V/F (24)   
Under/Overfrequency FRQ(81U/81O): 1st stage to 4th stage   
Frequency rate-of-change DFRQ: 1st stage to 4th stage   
Inrush Current Detector (2f for blocking)     
Voltage controlled O/C (51V)   
CT Supervision     
VT Supervision 
Trip circuit supervision     
Self supervision     
CB State Monitoring     
Trip Counter Alarm     
CB Operate Time Alarm     
Metering     
Watt meter 
Fault records     
Event records     
Disturbance records     
MODBUS Communication     
DNP 3.0 Communication     
IEC60870-5-103 Communication     
IEC61850 communication     
Note: The model of “ _ “ is 0, 1or 2 for number of BO and BI.

(*1) The Earth fault current is calcurated from three-phase current.
 9 
6 F 2 T 0 1 7 9
2. Application Notes
GRE160 is applied to both main protection and backup protection for the following transformers:
• Two-winding or three-winding power transformers
• Auto-transformers
• Generator-transformer units
2.1 Protection Scheme

GRE160 provides the following protection schemes with measuring elements in parentheses.
Appendix A shows the block diagrams of the GRE160 series.
• Current differential protection (DIFT)
• Restricted earth fault protection (1REF-2REF)
• Time-overcurrent protection (1OC-2OC, 1OCI-2OCI, 1EF-2EF and 1EFI-2EFI)
• Thermal overload protection (THM)
• Frequency protection (FRQ)
• Overexcitation protection (V/F)
• Trip and/or indication of external devices (Buchholtz relay, pressure or temperature sensing
devices etc.)
The DIFT, provided with DIF and HOC elements and the REF are applied for main protection. For
details, see Sections 2.2, 2.3 and 2.10.
They provide transformer protection coverage as follows:
REF: protection for winding to earth faults of star-winding side
DIF: protection for all internal transformer faults
(The DIF can be blocked by 2f or 5f element.)
HOC: protection for all internal transformer faults, specifically for heavy internal faults,
high-speed operation (The HOC is not blocked by 2f or 5f element. The sensitivity is set
above the estimated maximum inrush current.)
DIF
HOC
REF
For earth fault only
Small Differential current Large
The number of measuring elements for the restricted earth fault protection and time-overcurrent
protection is dependent on the relay models.
Figure 2.1.1 shows typical application and the relationship between AC inputs and the measuring
elements applied in each model.
 10 
6 F 2 T 0 1 7 9
GRE160
1OC/1OCI 1NOC/1NOCI CBF1 1OCV THM

1CT
VT
FRQ DFRQ OV/OVI UV/UVI V/F
HV Calculate 3I0
1nCT
1EF/1EFI * 1REF
LV
DIFT
2nCT
2EF/2EFI * 2REF
2CT Calculate 3I0
2OC/2OCI 2NOC/2NOCI CBF2 2OCV
* in model 100A and 300A, the EF current is calcurated from three phase current.
Figure 2.1.1 Measuring Elements
2.2 Current Differential Protection

2.2.1 Differential Scheme
Current differential protection DIFT provides an overall transformer protection deriving phase
current from each transformer winding, calculating the differential current on a per phase basis and
detecting phase-to-phase and phase-to-earth faults.
The current differential protection is based on Kirchhoff’s first law that the vector summation of all
currents flowing into a protected zone must be zero. Figure 2.2.1.1 shows the principle of current
differential protection. Differential current (id) is the vector summation of all terminal current of the
transformer. The differential current (id=i1+i2) is zero because the current (i1) equals current (−i2)
during a load condition or an external fault. During an internal fault, the differential current (id) is
not zero because the current (i1) does not equal to the current (−i2), and the DIFT operates.
Primary Secondary
I1 I2
Transformer
i1 i2
id=i1+i2
Differential current
detection DIFT
Figure 2.2.1.1 Current Differential Protection
Scheme logic
Figure 2.2.1.2 shows the scheme logic of the current differential protection. Current differential
element DIFT comprises sub-elements HOC, DIF, 2f and 5f which operate for differential current
on a per phase basis.
Note: For the symbols used in the scheme logic, see Appendix M.
HOC is a high-set overcurrent element operating for differential current. It provides high-speed
protection for heavy internal faults.
 11 
6 F 2 T 0 1 7 9
DIF is a percentage restraining element and has dual restraining characteristics, a weak restraint in
the small current region and a strong restraint in the large current region, to cope with erroneous
differential current which may be caused due to output imbalance of the CTs in case of an external
fault. (For the characteristics, see Section 2.10.)
The DIF output signal can be blocked when the 2F or 5F elements detect second harmonic inrush
current during transformer energization or fifth harmonic components during transformer
overexcitation. Blocking is enabled by setting scheme switch [2f-LOCK] or [5f-LOCK] to “ON”.
The following two or three blocking schemes are selectable by scheme switch [DIFTPMD].
“3POR”: When any one phase of the 2f or 5f element operates, tripping by the DIF element
is blocked in all 3 phases. “3POR” is recommended for transformers with large
capacity whose second harmonic component may be low. Its blocking function is
stronger than that of the “1P” or “2PAND” below.
“2PAND”: Even if 2f or 5f element operates during manetising inrush, the trip by DIF element
is allowed when any two phases or more of DIF element operate. “2PAND” is
recommended for a transformer with small or midium capacity whose second
harmonic component in inrush current is genarally higher than that of transformer
with large capacity.
“1P”: When any phase of the 2f or 5f elements operate, only the corresponding phase
output of the DIF element is blocked.
Protection by DIF and HOC can perform instantaneous three-phase tripping of two breakers. The
two breaker tripping signals DIFT-1 and DIFT-2 are enabled or disabled by the scheme switch
[DIFEN1] and [DIFEN2] settings.
DIFT
HOC-A 414
TRIP
413 HOC 224
415 & DIFT-1
HOC-B ≥1 & DIFEN1
401 DIF ≥1
+ & +
416
HOC-C HOCEN +
DIFEN & DIFT-2
DIFEN2
402 +
DIF-A & & & & ≥1 ≥1
DIF-B 403
& & & & 400
DIF & DIFT-DIF TP
404
DIF-C & &
& &
331
HOC & DIFT-HOC TP
406
2F-A & ≥1 1 & ≥1
≥1 352
407 DIFT TRIP
&
2F-B & ≥1 1
408 &
2F-C & ≥1 1
& &
410
5F-A &
& &
411 ≥1
5F-B &
& &
DIFTPMD
5F-C 412
& 3POR
+ 1P
2PAND (*2) ≥1
2F-Lock 405 &
≥1 1 &
+
5F-Lock ≥1
409
1
+
1616 DIF-A_BLOCK 1
1617 DIF-B_BLOCK 1
1618 DIF-C_BLOCK 1
Figure 2.2.1.2 Scheme Logic of Current Differential Protection
 12 
6 F 2 T 0 1 7 9
Display mode following differential tripping

Following a trip output, GRE160 can display either the operating phase or the faulted phase
according to the user’s requirements. The operating phase or faulted phase display is selectable by
the [Phase mode] setting in Record menu.
DIFT
[Operating phase]
414
HOC-A ≥1 Phase A
415
HOC-B ≥1 Phase B
416
HOC-C Phase C
401 ≥1
DIF
≥1
402 & & Phase N
DIF-A &
403 &
DIF-B
&
DIF-C
404 &
& Faulted phase
selection logic
406 1REF ≥1
2F-A & ≥1 1 &
≥1
407 1REF1
2F-B & ≥1 1 +
408 1REF2
2F-C & ≥1 1 +
[Faulted phase]
410 2REF &
5F-A &
≥1
411 2REF1
5F-B & +
5F-C 412 2REF2

& +
2F-Lock
+
5F-Lock
+
Figure 2.2.1.3 Operating Phase and Faulted Phase Selection Logic
2.2.2 Stability for CT Saturation during Through-fault Conditions
For current differential protection of transformers, GRE160 has a strong restraint characteristic in
the large current region for erroneous differential current due to CT saturation. Further, GRE160
provides a CT saturation countermeasure function. If any CTs saturate due to a large through-fault
current, an apparent differential current is generated in the differential circuit and may cause false
operation of the differential protection.
Operation Principle
Even when a CT saturates under very large primary currents, the waveform of the saturated CT
secondary current has two identifiable periods in each cycle: a non-saturated period and a saturated
period. The GRE160 utilizes this phenomenon and provides very secure operation for external faults
with a large through-fault current.
Figure 2.2.2.1 shows a block diagram of the CT saturation countermeasure (CTS). The CTS has a
waveform discriminating element (WDE) and starting element (SE). WDE operates if the change in
the instantaneous value of the differential current is less than a specified percentage of the change in
the instantaneous value of the restraining current. In the CTs non-saturated period, the differential
current is theoretically zero for through-fault currents. The element operates in this period.
 13 
6 F 2 T 0 1 7 9
Current
Input Differential Element
(DIFT_DIF) [CTSEN] & Tripping
Output
ON
Waveform Discriminating
Element 0 t
&
Starting Element
CTS
Figure 2.2.2.1 Differential Element with CT Saturation Countermeasure
The algorithm of this element is given by the following equation:

ΔId < 0.15×(Δip + Δin)
where,
Δid : Change in the differential current Id
(Δip + Δin) : Change in the restraining current in the positive and negative cycles
Id : Differential current
Ip : Sum of positive input currents
In : Sum of negative input currents
SE operates when the sum of the absolute values of the difference between the instantaneous values
of current data at each current input from one cycle is greater than 0.5 × (CT secondary rated
current).
SE discriminates between healthy and faulty power system conditions and blocks the output of
WDE which may otherwise operate during healthy conditions.
Figure 2.2.2.2 shows CT secondary current waveforms of the incoming and outgoing terminals, and
also the differential current at the time of an external fault with outgoing terminal CT saturation.
Figure 2.2.2.2 CT Secondary Current Waveforms and Differential Current for an External
Fault with CT Saturation
 14 
6 F 2 T 0 1 7 9
From the inception of the fault until the CT secondary current at the outgoing terminal saturates, the
differential current Id is zero and the change in the differential current Δid obtained from equation
(2) is also zero. However, the change in the restraining current given by equation (3) is a sufficiently
large positive value, so equation (1) is met and WDE operates.
SE detects changes in the terminal currents and rapidly operates, producing an AND output with
WDE. After this, since there is a period during which equation (1) is not satisfied, a certain time
delay is inserted to reliably block the operation of the DIFT_DIF differential element.
If, during an internal fault, there is a period during which the change in the instantaneous value of the
differential current is small due to CT saturation, WDE will not operate because the change in the
restraining current is also small during that period. Thus, during an internal fault, operation of the
differential element is not blocked falsely.
The CTS function can be disabled by the scheme switch [CTSEN].
2.2.3 Matching of CT Secondary Currents

The currents supplied to the differential elements must be matched in phase displacement and
amplitude under through-load and through-fault conditions.
Generally, it is difficult to completely match the incoming current with the outgoing current for the
relay input because the CT ratios at the primary and secondary sides of a transformer are not
matched in terms of the CT ratio, phase angle and cancelling of zero-sequence current.
GRE160 provides the α-method (Alpha) phase matching:
Primary Secondary
Ip Is
CT ratio: N1 CT ratio: N2
Transformer
Ip/N1=i1 Is/N2=i2
GRE160
Matching of phase Matching of phase
angle / Zero-sequence angle / Zero-sequence
current elimination current elimination
Matching of CT ratio Matching of CT ratio
Kct1×i1 Kct2×i2
Differential relay calculation
Figure 2.2.3.1 Matching Method
Phase matching is performed by setting according to the hands of a clock and the transformer
connections described in IEC60076-1. For details of the setting, refer to 2.2.5.
2.2.3.1 α-method phase matching

This method corrects the phase angle by using each winding current calculated as follows:
- Current substructed zero-sequence current from each phase current in Star- winding side of
transformer
- Phase-to-phase Current in Delta-winding side of transformer
The followings show calculation formula and current vectors in an example of a transformer Yd11.
 15 
6 F 2 T 0 1 7 9
Ipa Isa
Ip1 Is1 Isb
Ipc Ipb Isc
2 Ipa − Ipb − Ipc Isa − Isc

Ip1 = , Is1 = (1)
3 3
2 Ipb − Ipc − Ipa Isb − Isa
Ip 2 = , Is 2 = (2)
3 3
2 Ipc − Ipa − Ipb Isc − Isb
Ip3 = , Is3 = (3)
3 3
where,
Ipa, Ipb, Ipc : Primary side terminal current of transformer
Isa, Isb, Isc : Secondary side terminal current of transformer

Further, zero-sequence current is eliminated from the relay input current (Ip∗) for the calculation of
the differential current as follows:
2 Ipa − Ipb − Ipc 3Ipa − ( Ipa + Ipb + Ipc)
Ip1 = = = Ipa − Ipo
3 3
2 Ipb − Ipc − Ipa 3Ipb − ( Ipa + Ipb + Ipc)
Ip 2 = = = Ipb − Ipo
3 3
2 Ipc − Ipa − Ipb 3Ipa − ( Ipa + Ipb + Ipc)
Ip3 = = = Ipc − Ipo
3 3
2.2.3.2 Zero-sequence current elimination

In addition to compensating for the phase angle between the primary and secondary currents of the
transforemer, also phase angle matching prevents unnecessary operation due to zero-sequence
current during an external earth fault, such as in the following cases.
Case 1:
When an external fault occurs at the star-connected side of the transformer shown in Figure 2.2.3.2,
a zero-sequence current flows in star-connected side, but the zero-sequence current at the delta-side
circulates in the delta winding. The zero-sequence current is only fed into the star winding side of the
DIFT which is star-connected at the CT secondary, thus causing the DIFT to operate incorrectly.
The zero-sequence current is eliminated from a relay input current as described above.
Since the DIFT provides a function to eliminate the zero-sequence current by software, the DIFT is
insensitive the fault described.
 16 
6 F 2 T 0 1 7 9
I0 Transformer Ia
I0
I0
I0
I0 Ib
I0
Ic
3I0
DIFT
Figure 2.2.3.2 External Earth Fault at the Star-connected side of a Transformer
Case 2:
When the delta winding of a power transformer is earthed through an earthing transformer as shown
in Figure 2.2.3.3 and the earthing transformer is located within the differential protection zone, in
case of an external earth fault the zero-sequence current flows only on the delta side of the power
transformer and appears as a differential current.
Ia
I0
Ib
I0
Ic
I0
Earthing
Transformer
3I 0
DIF
Figure 2.2.3.3 External Earth Fault at the Delta-winding side of a Transformer with
in-zone Earthing Transformer
Since the DIFT provides a function to eliminate the zero-sequence current by software, the DIFT is
insensitive to the fault described.
2.2.3.3 Matching of CT Ratio

If I1 and I2 correspond to 1CT and 2CT secondary currents, differential current Id is calculated
according to the following equation,
Id = kct1⋅I1 + kct2⋅I2
where kct1 and kct2 are corresponding to 1CT and 2CT.
kct1, kct2 ; CT ration matching of primary and secondary winding
kct1 is obtained by using the following equation.
Kct1 = In/Ibase1
= In/( 3 × Ibase1) if 1CT is delta-connected.
 17 
6 F 2 T 0 1 7 9
Where
In = rated secondary current of 1CT (1A or 5A)
Ibase1 = secondary current of 1CT based on the kVA rating of the power transformer.
= transformer capacity(kVA)/( 3 × rated voltage(kV)) / CT ratio of 1CT
If the 1CT secondary circuit is delta-connected, 3 × Ibase1 is used instead of Ibase1 in the equation
above.
Kct2 is obtained in the same way.
At GRE160, kct1 and kct2 are calcurated from taransformer capacity (MVA) and rated voltage
(kV).
The differential current Id is zero under through-load and through-fault conditions.
Kct1 × I1 and kct2 × I2 are equal to the rated secondary current of each CT when the rated line
currents based on the kVA rating of the power transformer flow.
2.2.4 Connection between CT Secondary Circuit and the GRE160

GRE160 is provided with 2 three-phase current input terminals. The secondary wirings of 2
three-phase CT can be set the CT1POL and CT2POL settings.
To validate the phase angle matching described previously and apply in-phase current from each
winding to the relay according to CT1POL and CT2POL settings, connect the CT secondary
circuits to the current input terminals of the relay as follows.
Primary Secondary
1 3 5 5 3 1
TB4 GRE160 TB5
2 4 6 6 4 2
(a) CT1POL setting “Object”(=0) and CT2POL setting “Object”(=0)

Primary Secondary
1 3 5 1 3 5
TB4 GRE160 TB5
2 4 6 2 4 6
(b) CT1POL setting “Object”(=0) and CT2POL setting “Outside”(=1)
 18 
6 F 2 T 0 1 7 9
Primary Secondary
5 3 1 5 3 1
TB4 GRE160 TB5
6 4 2 6 4 2
(c) CT1P0OL setting “Outside”(=1) and CT2POL setting “Object”(=0)

Primary Secondary
5 3 1 1 3 5
TB4 GRE160 TB5
6 4 2 2 4 6
(d) CT1POL setting “Outside”(=1) and CT2POL setting “Outside”(=1)

Figure 2.2.4.1 Connection of CT Secondary Circuit and the GRE160
2.2.5 Setting
The following shows the setting elements necessary for the current differential protection and their
setting ranges. Setting can be performed on the LCD screen or PC screen.
Element Range Step Default Remarks

DIFT
DIF ik 0.10 − 1.00 (∗ ) 0.01 0.30 Minimum operating current
p1 10 − 100% 1% 100% % slope of small current region

p2 10 − 200% 1% 200% % slope of large current region
kp 1.00 − 20.00(*) 0.01 1.00 Break point of dual characteristics
k2f 10 − 50% 1% 15% Second harmonic detection
k5f 10 − 50% 1% 30% Fifth harmonic detection
TDIF 0.00-10.00s 0.01s 0.00s DIF definite time setting.
HOC kh 2.00 − 20.00(*) 0.01 4.00 High-set overcurrent protection
TDIFHS 0.00-10.00s 0.01s HOC definite time setting.
CT matching
TxCap 0.10 – 3000.00MVA 0.01MVA 100.00 Tramsformer Capacity
MVA
 19 
6 F 2 T 0 1 7 9
Vn1 0.4-500.00kV 0.1kV 132kV Rated voltage at primary winding side

Vn2 0.4-500.00kV 0.1kV 66kV Rated voltage at secondary winding side
CT1 1A / 5A 1A CT secondary rated current at primary
winding side
CT2 1A / 5A 1A CT secondary rated current at secondary
CT ratio winding side
1CT 1 – 30000A 1A Rated current at primary winding side
2CT 1 – 30000A 1A Rated current at secondary winding side
CT1POL Object/Outside Object CT secondary wiring at primary side
CT2POL Object/Outside Object CT secondary wiring at secondary side
Phase angle matching
yd_p 1(star) / 2(delta) 1 Primary winding mode
yd_s 1(star) / 2(delta) 1 Secondary winding mode
vec_s 0 – 11 1 0 Phase angle difference between primary
and secondary
Scheme switch
[DIFEN] Off / On Off Enable or disable tripping by DIF element
[HOCEN] Off / On Off Enable or disable HOC element
[DIFEN1] Off / On Enable or disable tripping by DIF1
element
[DIFEN2] Off / On Enable or disable tripping by DIF2
element
[DIFTPMD] 3POR / 2PAND / 1P 3POR Trip mode
[2f – LOCK] Off / On On Block by second harmonic
[5f – LOCK] Off / On Off Block by fifth harmonic
[CTSEN] Off / On Off CT saturation function
[Phase mode] Operationg / Fault Operating Fault display mode setting
Setting of ik
ik determines the minimum operation sensitivity of the DIF element. ik is set as a ratio to the CT
secondary rated current.
The minimum sensitivity setting ik is determined from the maximum erroneous differential current
under normal operating conditions.
Setting of p1, p2 and kp

Percentage restraining factor (% slope)
= (Differential current) / (Through current)
= (Differential current) / [{(Incoming current) + (Outgoing current)} /2]
p1 is the percentage restraining factor which defines the DIF restraining characteristic in the small
current region. The setting is determined by the sum of:
• CT accuracy error (generally considered as 5%)
• Tap error: Error between maximum/minimum tap and the middle tap when taking the middle
 20 
6 F 2 T 0 1 7 9
tap of the tap changer as a reference.

• Matching error: The error due to CT mismatch may be small enough to be neglected in the
setting.
• Relay calculation error, and others (5%)
The recommended setting is “Sum of above” × 1.5 (margin).
p2 is the percentage restraining factor which defines the restraining characteristic in the large
current region. The setting is determined from the maximum erroneous differential current which is
generated when a large through fault current flows.
kp is the break point of the dual percentage restraining characteristics. It is set above the maximum
operating current level of the transformer between the maximum forced-cooled rated current and the
maximum emergency overload current level, as a ratio to the CT secondary rated current.
Setting of k2f
k2f is set to detect the second harmonic content in the inrush current during transformer energization
and blocks GRE160 to prevent incorrect operation due to the inrush current. A setting of 15% is
suggested if there is no data on the minimum second harmonic content.
The threshold current of 2f-Lock element is same as ik setting current.
Setting of k5f
k5f is set to detect the fifth harmonic content during transformer over-excitation and blocks
GRE160 to prevent incorrect operation due to transient over-excitation conditions.
A setting of 30% is suggested if there is no data on the minimum fifth harmonic content.
The threshold current of 5f-Lock element is same as ik setting current.
Setting of kh
kh is the HOC setting and should be set above the estimated maximum inrush current.
The recommended setting is more than “Maximum peak value of Inrush current” × kct.
Setting for CT ratio matching

Taking the transformer shown in Figure 2.2.5.1 as an example, the CT ratio matching settings value
of kct1 and kct2 can be calculated from transformer capacity setting and rated voltage setting as
follows.
Calculation steps Primary Secondary
(1) Transformer capacity (kVA) setting 40 × 103
(2) Rated Voltage(kV) setting 154 66
(3) Rated line current(A) 150 350
=(1)/( 3 × (2))
(4) CT rated current setting 300 600
(5) Secondary rated line current(A) =(3)/(4) 2.50 2.92
(6) CT secondary rating(A) 5 5
(7) Calculated (at GRE160) Kct1=2.00 Kct2=1.71
 21 
6 F 2 T 0 1 7 9
Primary Secondary CT2
CT1 40MVA 40MVA
300/5 600/5
154kV 66kV
A B
kct1 kct2
GRE160
Figure 2.2.5.1 CT Ratio Matching
As explained in Section 2.2.3 for Mathcing of CT Secondary Currents, example of setting for
α-method is described as follows:
Setting for phase angle matching
The phase angle difference between line currents on either side of the power transformer are
corrected by setting according to the hands of a clock and the transformer connections described in
IEC60076-1 as follows:
Phase matching
If a winding is star-connected, set 1 (=star) for winding setting yd_p and yd_s. If delta-connected,
set 2 (=delta). Next, set the phase angle difference vec_s from the primary winding as a lagging
angle winding expressed in hours. One hour corresponds to lagging by thirty degrees.
Note: In the case of a zigzag connected winding, set 2 (=delta).
Example: Setting for star/delta transformer.
IEC60076-1 Setting
yd_p yd_s vec_s
Primary Secondary Y d 11 1 2 11
yd_p: Because the primary winding is star-connected, set 1.

yd_s: Because the secondary winding is delta-connected, set 2.
vec_s: Because the secondary winding lags the primary winding by 330°, set 11.
The settings for the transformer connections described in IEC60076-1 are listed in Table 2.2.5.2.
Note: The following calculation is performed in the relay for phase angle correction.
 22 
6 F 2 T 0 1 7 9
Table 2.2.5.1 Phase Angle Matching Calculation

O’clock Calculation Remarks
0 Ia’ = (2Ia − Ib − Ic)/ 3 Ib’ = (2Ib − Ic − Ia)/ 3 Ic’ = (2Ic − Ia − Ib)/ 3
1 Ia’ = (Ia – Ib)/ 3 Ib’ = (Ib − Ic)/ 3 Ic’ = (Ic – Ia)/ 3 Setting value
2 Ia’ = (Ia − 2Ib + Ic)/ 3 Ib’ = (Ia + Ib − 2Ic)/ 3 Ic’ = (Ib + Ic −2Ia)/ 3 0
11 1
3 Ia’ = (Ic − Ib)/ 3 Ib’ = (Ia – Ic)/ 3 Ic’ = (Ib − Ia)/ 3
4 Ia’ = (2Ic − Ia − Ib)/ 3 Ib’ = (2Ia − Ib − Ic)/ 3 Ic’ = (2Ib − Ia − Ic)/ 3 10 2
5 Ia’ = (Ic – Ia)/ 3 Ib’ = (Ia – Ib)/ 3 Ic’ = (Ib – Ic)/ 3
9 3
6 Ia’ = (Ib + Ic −2Ia)/ 3 Ib’ = (Ia − 2Ib + Ic)/ 3 Ic’ = (Ia + Ib − 2Ic)/ 3
7 Ia’ = (Ib − Ia)/ 3 Ib’ = (Ic − Ib)/ 3 Ic’ = (Ia – Ic)/ 3 4
8
8 Ia’ = (2Ib − Ia − Ic)/ 3 Ib’ = (2Ic − Ia − Ib)/ 3 Ic’ = (2Ia − Ib − Ic)/ 3 7 5
9 6
Ia’ = (Ib – Ic)/ 3 Ib’ = (Ic – Ia)/ 3 Ic’ = (Ia – Ib)/ 3
10 Ia’ = (Ia + Ib − 2Ic)/ 3 Ib’ = (Ib + Ic −2Ia)/ 3 Ic’ = (Ia − 2Ib + Ic)/ 3
11 Ia’ = (Ia – Ic)/ 3 Ib’ = (Ib − Ia)/ 3 Ic’ = (Ic − Ib)/ 3
Table 2.2.5.2 Setting for Phase Angle Matching
Transformer connections Settings for phase angle correction Remarks

described in IEC60076-1 Primary, Secondary, Phase angle Diff. Phase angle matching
Primary, (yd_p) (yd_s) (vec_s) calculation (Table 2.2.5.1)
Secondary
(P) (S)
Yy0 1 1 0 P: 0 O’clock
S: 0 O’clock
Dd0 2 2 0 P: 1 O’clock
S: 1 O’clock
Yd1 1 2 1 P: 0 O’clock
S: 1 O’clock
Dy1 2 1 1 P: 11 O’clock
S: 0 O’clock
S: 3 O’clock
S: 5 O’clock
S: 5 O’clock
Dy5 2 1 5 P: 7 O’clock
S: 0 O’clock
Yy6 1 1 6 P: 0 O’clock
S: 6 O’clock
S: 7 O’clock
 23 
6 F 2 T 0 1 7 9
S: 7 O’clock
Dy7 2 1 7 P: 5 O’clock
S: 0 O’clock
S: 9 O’clock
Dd10 2 2 10 P: 1 O’clock
S: 11 O’clock
Yd11 1 2 11 P: 0 O’clock
S: 11 O’clock
Dy11 2 1 11 P: 1 O’clock
S: 0 O’clock
Dz10 2 2 10 P: 1 O’clock
S: 11 O’clock
<How to set phase angle matching for GRE160>

Reference phase for phase angle matching
The phase of a star-connected winding side is used as the reference phase for phase angle matching.
Yd: primary
Dy: secondary
Dd: the reference vector leads the A phase of the primary side by 30°.
Phase rotation
The relationship between each terminal current vector of a transformer, which depends on the
transformer connection and the connection between the transformer and the power system, must be
checked. The phase displacement of a delta-connected side may not be determined only by the
transformer connection described in IEC60076. Table 2.2.5.3 shows an example illustrating the
connection of a transformer and power system and their current vectors when a Yd1 type
transformer is connected to the power system with both clockwise and anticlockwise phase rotation.
In this case, the setting for phase angle correction is not corresponding to that of Table 2.2.5.1.
Table 2.2.5.3 Transformer Connection and Current Vector
Delta-side connected with 30° lagging Delta-side connected with 30° leading
Connection between Primary
Transformer
Yd1 Secondary Primary
Transformer
Yd1 Secondary
Yd1 Transformer a U u a a U u a
and Power system b V v b b V v b
c W w c c W w c
Each winding a U
Transformer u a a U
Transformer u a
connection and I1a I2a
v
I2a’=I2a−I2c I1a I1c I2c
v
I2a’=I2a−I2b
b V b b V b
Incoming/Outgoing I1b
I1b I2b I2b’=I2b−I2a I1b I2b I2b’=I2b−I2c
current c W w c c W w c
I1c I2c I2c’=I2c−I2b I1c I1a I2a I2c’=I2c−I2a
 24 
6 F 2 T 0 1 7 9
I2b’=I2b−I2a I2c’=I2c−I2a
Incoming current I1a I1a
I2b
I2c
vector and Outgoing I2b I2c
current vector I1c I1b
30° I2c’=I2c−I2b I2b’=I2b−I2c 30°
I1c I1b I2a
I2a
I2a’=I2a−I2c I2a’=I2a−I2b
Incoming Outgoing Incoming Outgoing
Current Current Current Current
Setting Yd_p=1, yd_s=2, vec_s=1 (Same as Yd1) Yd_p=1, yd_s=2, vec_s=11 (same as Yd11)
Auto-transformer (with internal delta-winding)

Set Yy0.
Zigzag connected transformer
Set yd_p, yd_s and vec_s to 2 (=delta) for zigzag connected side. Zero-sequence current is canceled.
2.3 Restricted Earth Fault Protection

Restricted earth fault protection (REF) is a zero-phase current differential scheme applied to a
star-connected winding whose neutral is earthed directly, through a low impedance or a high
impedance. It gives highly sensitive protection for internal earth faults. Two REF of low impedance
scheme or high imepedance scheme selected by [1REFSCHEME] and [2REFSCHEME] settings.
Low-impedance Restricted earth fault protection

REF employs a low impedance current differential scheme which detects the differential current
between the zero-sequence current I0 derived from the three-phase line currents and the neutral
current IN in the neutral conductor as shown in Figure 2.3.1.
Ia+Ib+Ic
REF
IN
Figure 2.3.1 Restricted Earth Fault Protection
REF and the overall differential protection DIFT use the three-phase line currents in common.
GRE160 has two Low-impedance REF elements, providing separate protection for star-connected
and neutral-earthed windings.
Figure 2.3.2 shows the block diagram of the REF element which is composed of REF_DIF and
REF_DEF. The REF_DIF has a percentage restraining characteristic while the REF_DEF provides
a directional check feature to discriminate between internal and external faults. When the REF_DEF
is “ON”, the REF_DEF element is used. The REF_DEF element provides additional security
against incorrect operation of the REF element in the event of saturation of the neutral CT. The
REF_DEF is blocked when the maximum phase current exceeds 2 × kct × (Rated current of neutral
CT), since the REF element is used for earth fault protection of transformer winding. For details, see
Section 2.10.3. In case of terminal current larger than that, the DIFT element provides tripping. The
REF_DEF can be disabled by setting the scheme switch [REFDEF] to “OFF”.
 25 
6 F 2 T 0 1 7 9
REF_DIF
REF
REF_DEF &
internal fault detection
& ≥1
Ires≦2.0×Max_kct
[REF_DEF] ON
+
OFF
Figure 2.3.2 Block Diagram of REF
High-impedance Restricted earth fault protection

The 1REFOC1 to 2REFOC2 elements can be applied in a high impedance restricted earth fault
scheme, for protection of a star-connected transformer winding whose neutral is earthed directly or
through impedance.
As shown in Figure 2.3.3, the differential current between the residual current derived from the
three-phase line currents and the neutral current in the neutral conductor is introduced into the REF
elements. Two external components, a stabilising resistor and a varistor, are connected as shown in
the figure. The former increases the overall impedance of the relay circuit and stabilises the
differential voltage, and the latter suppresses any overvoltage in the differential circuit.
F
Transformer
Varistor
Stabilising GRE160
Resistor REF input
Figure 2.3.3 High Impedance REF
The elements have the same percentage restraining characteristics and are stable for all faults
outside the protected zone.
Figure 2.3.4 shows the scheme logic of the restricted earth fault protection when two REF elements
are applied. Each REF element can perform instantaneous or time-delayed tripping of two breakers.
The two breaker tripping signals 1REF-1 to 2REF-2 are enabled or disabled by the scheme switch
[1REF1EN] to [2REF2EN] settings.
 26 
6 F 2 T 0 1 7 9
T1REF
421 t 0 420 422
1REF & 1REF-1-TRIP
[1REF1EN]
0.00 - 10.00s +
“ON”
423
& 1REF-2-TRIP
[1REF2EN]
+
“ON” 503 1REF TRIP
≥1
T1REFOC1
575 t 0 576 577
1REFOC1 &
[1REFOC1]
0.00 - 10.00s +
“ON”
T1REFOC2
578 t 0 579 580
1REFOC2 &
[1REFOC2]
0.00 - 10.00s +
“ON”
425 2REF-1-TRIP
2REF
Same as above 2REF-2-TRIP
2REFOC1 504
2REF TRIP
≥1
2REFOC2
Figure 2.3.4 Scheme Logic of Restricted Earth Fault Protection
Appendix L shows applications of the three REF elements to various types of transformers. When
protecting a two-winding transformer, 1REF and 2REF elements should be applied to the primary
(or high-voltage) winding and secondary (or low -voltage) winding respectively. This is also valid
for auto-transformer protection but the application must comply with Appendix L.
In the application to auto-transformers, one REF element may introduce two line currents and one
neutral current as shown in Appendix L. 1REF and 2REF elements recognize the number of the line
currents according to the scheme switch setting of [1REF1EN] to [2REF2EN].
Setting
The following shows the setting elements for the restricted earth fault protection and their setting
ranges.
1REF 1ik 0.05 − 2.50(*) 0.01 0.50 Minimum operating current
1p2 50 − 100% 1% 100% % slope of DF2
1kp 0.50 −10.00(*) 0.01 1.00 DF2 restraining current section of
large current characteristic
2REF 2ik 0.05 − 2.50(*) 0.01 0.50 Minimum operating current
2p2 50 − 100% 1% 100% % slope of DF2
2kp 0.50 −10.00(*) 0.01 2.00 DF2 restraining current section of
large current characteristic
T1REF 0.00 − 10.00s 0.01s 0.00s
Delayed tripping
T2REF 0.00 − 10.00s 0.01s 0.00s
1REFOC1 to 0.01 – 1.00(*) 0.001 0.20 Overcurrent settings of
2REFOC2 0.15 High-impedance REF elements.
 27 
6 F 2 T 0 1 7 9
T1REFOC1 to 0.00 – 10.00s 0.01s 0.05s Timer settings of

T2REFOC2 0.10s High-impedance REF elements.
CT ratio
CTn1 1A / 5A Neutral CT secondary rated current
1A
at primary winding side
CTn2 1A / 5A Neutral CT secondary rated current
1A
at secondary winding side
1nCT 1 – 30000A 1A Rated current for neutral CT
at primary winding side
2nCT 1 – 30000A 1A Rated current for neutral CT
at secondary winding side
Scheme switch
[1REF1EN] , Off/On Enable or disable to output
[1REF2EN] tripping signal
[2REF1EN] , Off/On Enable or disable to output
[2REF2EN] tripping signal
[1REFOC1] to Off/On High-impedance REF elements
[2REFOC2]
[REF_DEF] 1REF and 2REF block elements
[1REFSCHEME], Low / High Low REF element setting.
[2REFSCHEME] Low / High Low REF element setting.
(*): Multiplier of secondary rated current
Setting of ik (1ik and 2ik)
1ik and 2ik are minimum operating current settings and are set as a ratio to the line CT secondary
rated current. ik is determined from the maximum erroneous zero sequence differential current under
normal operating conditions.
Setting for CT ratio matching

Taking the transformer shown in Figure 2.2.5.1 as an example, the CT ratio matching settings
values of 1kct1-1kct2 for 1REF element, and 2kct1-2kct2 for 2REF element can be calculated from
a ratio of the line CTs ratio to the neutral CT ratio and the line CTs have the notations shown in
Appendix L according to 1REF and 2REF applications.
For example, the 1kct1, 1kct2, 2kct1 and 2kct2 are calculated;
1kct1 = (CT ratio of line CT 1ct-1)/(CT ratio of neutral CT 1nCT)
where, CT ratio = (primary rated current)/(secondary rated current).
Setting of scheme switch [REF_DEF]

The function of REF_DEF is set to “On/Off” by setting.
Setting of scheme switch [1REFSCHEME] and [2REFSCHEME]

The element of REF is set to “Low / High” by setting.
 28 
6 F 2 T 0 1 7 9
2.4 Overcurrent Protection

GRE160 provides definite time and inverse time overcurrent elements for both phase faults and
earth faults, separately for each transformer winding. Three phase currents from each set of line
CTs are used for the phase fault protection elements, while the earth fault protection is based on the
neutral CT input.These elements can be used selectively depending on the requirements of the
particular application, but the following points should be noted:
• In the case of large power transformers, overcurrent protection is usually employed only as
back-up protection for terminal faults, and for uncleared LV system faults. In such cases, the
overcurrent elements can be applied either on one or both sides of the transformer as required.
• Coverage of internal transformer faults is generally limited.
• It is common practice to apply IDMTL phase and earth fault overcurrent protection as
back-up for the LV system. Current and time settings must be arranged to grade with
downstream relays and fuses. The phase fault current setting must also be set to exceed the
maximum overload current.
• High-set instantaneous overcurrent protection can be applied on the primary side to provide
back-up protection for terminal faults. The current setting must be higher than the maximum
through-fault current to ensure that the element does not operate for faults on the LV side.
One of the following IEC-standard-compliant (IEC60255-151) inverse time characteristics or one
long time inverse characteristic is available for the inverse current protection.
The definite time elements (1OC and 2OC) and the inverse time elements (1OCI and 2OCI) input
three phase currents from line CTs in the transformer windings.
The definite time elements (1EF and 2EF) and inverse time elements (1EFI and 2EFI) input neutral
currents from CTs in the neutral circuit.
Figure 2.4.1 and Figure 2.4.2 show the scheme logic of overcurrent protection. Each element can
perform time-delayed tripping of two breakers. The breaker tripping signals are blocked by the
scheme switch settings.
 29 
6 F 2 T 0 1 7 9
T1OC1
11 t 0 222
A & & 1OC1-A TRIP
1OC1 12 t 0 223
B & 1OC1-B TRIP
&
13 224 335
C & t 0 1OC1-C TRIP 1OC1 TRIP
&
[1OC1EN]
+ 0.00 - 300.00s ≥1
&
≥1
[1OC1-2F] &
+ "Block" ≥1
& & &
ICD1
&
17 226
A & & 1OCI1-A TRIP
1OCI1 B 18 227
& & 1OCI1-B TRIP
19 228 225
C 1OCI1-C TRIP 1OCI1 TRIP
& &
[1OCI1EN]
+
≥1 & ≥1
& ≥1 &
&
1536 1OC1_BLOCK 1 [1OCTP] "3POR"
& +
"2OUTOF3"
Note: 1OC2,2OC1 and 2OC2 provide the same logic as 1OC1.

1OCI2, 2OCI1 and 2OCI2 provides the same logic as 1OCI1.
Figure 2.4.1 Scheme Logic of the Overcurrent Protection
T1EF1
61 t 0 261
1EF1 & & 1EF1 TRIP
[1EF1EN] 0.00 - 300.00s
+
[1EF1-2F]
+ "Block"
&
ICD1
63 262
1EFI1 & & 1EFI1 TRIP
[1EFI1EN]
+
1544 1EF1_BLOCK 1
Note: 1EF2, 2EF1 and 2EF2 provide the same logic as 1EF1.
1EFI2, 2EFI1 and 2EFI2 provide the same logic as 1EFI1.
Figure 2.4.2 Scheme Logic of the Overcurrent Protection for Earth Faults
 30 
6 F 2 T 0 1 7 9
Setting
The following shows the setting elements for the overcurrent protection and their setting ranges.

Overcurrent setting
1OC1 to 2OC2 0.10 − 20.00(*) 0.01 1.00 Definite time overcurrent (line)
T1OC1 to T2OC2 0.00 − 300.00s 0.01s 0.00s Delayed tripping for OC
1OCI1 to 2OCI2 0.10 − 5.00(*) 0.01 1.00 Inverse time overcurrent (line)
T1OC1M to T2OC2M 0.010-15.000 0.001 OCI time multiplier setting. Required if
[M1OC1] to [M2OC2] = IEC, IEEE or US.
T1OC1R to T2OC2R 0.0 – 300.0 s 0.1 s 0.0 s OC definite time delayed reset. Required if
[1OC1R] to [2OC2R] = DEF.
T1OC1RM to 0.010-15.000 0.001 OCI dependent time delayed reset time
T2OC2RM multiplier. Required if [1OC1R] to [2OC2R]
= DEP.
OCI userconfigurable curve setting
1OC1-k to 2OC2-k 0.00-30.000 0.001
1OC1-α to 2OC2-α 0.01-5.00 0.01
OCI userconfigurable curve setting.
1OC1-c to 2OC2-c 0.000-5.000 0.001
Required if [M1OC1] to [M2OC2] = C.
1OC1-kr to 2OC2-kr 0.00-30.000 0.001
1OC1-β to 2OC2-β 0.01-5.00 0.01
Earth fault setting
1EF1 to 2EF2 0.10 − 20.00(*) 0.01 0.30 Definite time overcurrent (neutral)
T1EF1 to T2EF2 0.00 − 300.00s 0.01s 0.00s Delayed tripping for EF
1EFI1 to 2EFI2 0.10 − 5.00(*) 0.01 0.30 Inverse time overcurrent (neutral)
T1EF1M to T2EF2M 0.010 − 15.000 0.001 1.000 EFI time multiplier setting. Required if
[M1EF1] to [M2EF2] = IEC, IEEE or US.
T1EF1R to T2EF2R 0.0 – 300.0 s 0.1 s 0.0 s EF definite time delayed reset. Required if
[1EF1R] to [2EF2R] = DEF.
T1EF1RM to 0.010-15.000 0.001 EFI dependent time delayed reset time
T2EF2RM multiplier. Required
if [1EF1R] to [2EF2R] = DEP.
EFI userconfigurable curve setting
1EF1-k to 2EF2-k 0.00-30.000 0.001
1EF1-α to 2EF2-α 0.01-5.00 0.01
EFI userconfigurable curve setting.
1EF1-c to 2EF2-c 0.000-5.000 0.001
Required if [M1EF1] to [M2EF2] = C.
1EF1-kr to 2EF2-kr 0.00-30.000 0.001
1EF1-β to 2EF2-β 0.01-5.00 0.01
 31 
6 F 2 T 0 1 7 9

Scheme switch Inverse time characteristic selection of
[M1OC1] to [M2OC2] IEC/IEEE/US/C IEC OCI elements time characteristic
[M1OC1C-IEC] to NI / VI / EI / LTI NI Required if [M1OC1] to [M2OC2] = IEC.
[M2OC2C-IEC]
[M1OC1C-IEEE] to MI / VI / EI MI Required if [M1OC1] to [M2OC2] = IEEE.
[M2OC2C-IEEE]
[M1OC1C-US] to CO2 / CO8 CO2 Required if [M1OC1] to [M2OC2] = US.
[M2OC2C-US]
[M1EF1] to [M2EF2] IEC/IEEE/US/C IEC EFI elements time characteristic
[M1EF1C-IEC] to NI / VI / EI / LTI NI Required if [M1EF1] to [M2EF2] = IEC.
[M2EF2C-IEC]
[M1EF1C-IEEE] to MI / VI / EI MI Required if [M1EF1] to [M2EF2] = IEEE.
[M2EF2C-IEEE]
[M1EF1C-US] to CO2 / CO8 CO2 Required if [M1EF1] to [M2EF2] = US.
[M2EF2C-US]
Scheme switch Enable or disable tripping by
[1OC1EN] to Off / On OC elements
[2OC2EN]
[1OCI1EN] to Off / On OCI elements
[2OCI2EN]
[1OC1R] to [2OC2R] DEF / DEP DEF OCI reset characteristic. Required if
[M1OC1] to [M2OC2] = IEEE or US.
[1OC1-2F] to NA / Block NA OC and OCI elements 2f-Lock enable.
[2OC2-2F]
[1OCTP] , [2OCTP] 3POR / 2OUTOF3 3POR OC trip mode
[1EF1EN] to Off / On EF elements
[2EF2EN]
[1EFI1EN] to Off / On EFI elements
[2EFI2EN]
[1EF1R] to [2EF2R] DEF / DEP DEF EFI reset characteristic. Required if
[M1EF1] to [M2EF2] = IEEE or US.
[1EF1-2F] to NA / Block NA EF and EFI elements 2f-Lock enable.
[2EF2-2F]
(*) : Multiplier of CT secondary rated current.
The overcurrent elements use the same three-phase line currents and neutral current as the
differential protection and the restricted earth fault protection. When choosing settings, the
following relationships between the overcurrent elements and the connected windings must be taken
into account.
1OC, 1OCI : Primary (high-voltage) winding
2OC, 2OCI : Secondary (low-voltage) winding
1EF, 1EFI : 1REF applied neutral circuit
2EF, 2EFI : 2REF applied neutral circuit
 32 
6 F 2 T 0 1 7 9
2.5 Negative Sequence Overcurrent Protection

The negative sequence overcurrent protection (NC) is used to detect asymmetrical faults
(phase-to-phase and phase-to-earth faults) with high sensitivity in conjunction with phase
overcurrent protection and residual overcurrent protection. It also used to detect transformer
unbalance conditions.
GRE160 provides negative sequence overcurrent protection with definite time characteristics.
The definite time elements (1NC and 2NC) and the inverse time elements (1NCI and 2NCI) input
three phase currents from line CTs in the transformer windings.
The NC protections are enabled when three-phase current is introduced and the scheme switch
[APPLCT] is set to “On”.
Figure 2.5.1 shows the scheme logic of negative phase sequence overcurrent protection. Each
element can perform time-delayed tripping of two breakers. The breaker tripping signals are blocked
by the scheme switch settings.
T1NC1
110
1NC1 t 0 295
& 1NC1_TRIP
[NC1-2F] [1NC1EN] 0.00 - 300.00s

+ "Block" + "OFF"
&
ICD1
112 296
1NCI1 1NCI1_TRIP
&
[1NCI1EN]
+ "OFF"
1560 1NOC1_BLOCK 1
Note: 1NC2, 2NC1 and 2NC2 provide the same logic as 1NC1.
1NCI2, 2NCI1 and 2NCI2 provide the same logic as 1NCI1.
Figure 2.5.1 Negative Sequence Overcurrent Protection NC and NCI Scheme Logic
Setting
The table below shows the setting elements necessary for the NC protection and their setting ranges.
1NC1 to 2NC2 0.10 − 20.00(*) 0.01 0.40 Definite time overcurrent (line)
T1NC1 to T2NC2 0.00 − 300.00s 0.01s 0.00s Delayed tripping for NC
1NCI1 to 2NCI2 0.10 − 5.00(*) 0.01 0.40 Inverse time overcurrent (line)
T1NC1M to T2NC2M 0.010-15.000 0.001 NCI time multiplier setting. Required if
[M1NC1] to [M2NC2] = IEC, IEEE or US.
T1NC1R to T2NC2R 0.0 – 300.0 s 0.1 s 0.0 s NC definite time delayed reset. Required if
[1NC1R] to [2NC2R] = DEF.
T1NC1RM to 0.010-15.000 0.001 NCI dependent time delayed reset time
T2NC2RM multiplier. Required if [1NC1R] to [2NC2R]
= DEP.
 33 
6 F 2 T 0 1 7 9

NCI userconfigurable curve setting
1NC1-k to 2NC2-k 0.00-300.00 0.001
1NC1-α to 2NC2-α 0.01-5.00 0.01
NCI userconfigurable curve setting.
1NC1-c to 2NC2-c 0.000-5.000 0.001
Required if [M1NC1] to [M2NC2] = C.
1NC1-kr to 2NC2-kr 0.01-300.00 0.001
1NC1-β to 2NC2-β 0.00-5.00 0.01
Scheme switch Inverse time characteristic selection of
[M1NC1] to [M2NC2] IEC/IEEE/US/C IEC NCI elements time characteristic
[M1NC1C-IEC] to NI / VI / EI / LTI NI Required if [M1NC1] to [M2NC2] = IEC.
[M2NC2C-IEC]
[M1NC1C-IEEE] to MI / VI / EI MI Required if [M1NC1] to [M2NC2] = IEEE.
[M2NC2C-IEEE]
[M1NC1C-US] to CO2 / CO8 CO2 Required if [M1NC1] to [M2NC2] = US.
[M2NC2C-US]
Scheme switch Enable or disable tripping by
[1NC1EN] to Off / On NC elements
[2NC2EN]
[1NCI1EN] to Off / On NCI elements
[2NCI2EN]
[1NC1R] to [2NC2R] DEF / DEP DEF NCI reset characteristic. Required if
[M1NC1] to [M2NC2] = IEEE or US.
[1NC1-2F] to NA / Block NA NC and NOCI elements 2f-Lock enable.
[2NC2-2F]
Sensitive setting of NC and NCI thresholds is restricted by the negative phase sequence current
normally present on the system. The negative phase sequence current is measured in the relay
continuously and displayed on the metering screen of the relay front panel along with the maximum
value. It is recommended to check the display at the commissioning stage and to set to 130 to 150%
of the maximum value displayed.
The delay time setting T_NC is added to the inherent delay of the measuring elements NC. The
minimum operating time of the NC elements is around 200ms.
 34 
6 F 2 T 0 1 7 9
2.6 Thermal Overload Protection

The thermal overload protection is applied to protect transformers from electrical thermal damage.
The protection simulates the changing thermal state in the plant using a thermal model.
The thermal state of the electrical system can be shown by equation (1).
I2  −t 
θ =  1 − e τ × 100%
 (1)
I 2AOL  
where:
θ = thermal state of the system as a percentage of allowable thermal capacity,
I = applied load current,
IAOL = allowable overload current of the system,
τ = thermal time constant of the system.
The thermal state 0% represents the cold state and 100% represents the thermal limit, which is the
point at which no further temperature rise can be safely tolerated and the system should be
disconnected. The thermal limit for any given system is fixed by the thermal setting IAOL. The relay
gives a trip output when θ= 100%.
The thermal overload protection measures the largest of the three phase currents and operates
according to the characteristics defined in IEC60255-149.
Time to trip depends not only on the level of overload, but also on the level of load current prior to
the overload - that is, on whether the overload was applied from ‘cold’ or from ‘hot’.
Independent thresholds for trip and alarm are available.
The characteristic of the thermal overload element is defined by equation (2) and equation (3) for
‘cold’ and ‘hot’. The cold curve is a special case of the hot curve where prior load current Ip is zero,
catering for the situation where a cold system is switched on to an immediate overload.
 I2 
t =τ·Ln  2 2  (2)
 I − I AOL 
 I2 − I 2 
t =τ·Ln  2 2P  (3)
 I − I AOL 
where:
t = time to trip for constant overload current I (seconds)
I = overload current (largest phase current) (amps)
IAOL = allowable overload current (amps)
IP = previous load current (amps)
τ= thermal time constant (seconds)
Ln = natural logarithm
Figure 2.6.1 illustrates the IEC60255-149 curves for a range of time constant settings. The left-hand
chart shows the ‘cold’ condition where an overload has been switched onto a previously un-loaded
system. The right-hand chart shows the ‘hot’ condition where an overload is switched onto a system
that has previously been loaded to 90% of its capacity.
 35 
6 F 2 T 0 1 7 9
Thermal Curves (Cold Curve - Thermal Curves (Hot Curve -

no prior load) 90% prior load)
1000 1000
100
100
Operate Time (minutes)

10
10
1
τ
τ
1 100
100
50 0.1 50
20 20
0.1 10 10
0.01
5
5
2
2
1
0.01 1 0.001
1 10 1 10
Overload Current (Multiple of IAOL) Overload Current (Multiple of
IAOL)
Figure 2.6.1 Thermal Curves
Figure 2.6.2 shows the scheme logic of the thermal overload protection.
The thermal overload element THM has independent thresholds for alarm and trip, and outputs
alarm signal THM_ALARM and trip signal THM_TRIP. The alarm threshold level is set as a
percentage of the tripping threshold.
The alarming and tripping can be disabled by the scheme switches [THMAEN] and [THMEN]
respectively or PLC signals THMA_BLOCK and THM_BLOCK.
107
292
A & THM_ALARM
&
THM
108
T 293
& THM_TRIP
&
[THMAEN]
+
"ON"
[THMEN]
+
"ON"
1573 THMA_BLOCK 1
1572 THM_BLOCK 1
Figure 2.6.2 Scheme Logic of Thermal Overload Protection
The thermal overload element is only for primaly winding side (1CT).
 36 
6 F 2 T 0 1 7 9
Setting
The table below shows the setting elements necessary for the thermal overload protection and their
setting ranges.
THM 0.40 – 2.50 pu(∗) 0.01 pu 1.00 pu Thermal overload setting.
(THM = IAOL: allowable overload current)
THMIP 0.00 – 1.00 pu(∗) 0.01 pu 0.00 pu Previous load current
TTHM 0.5 - 500.0 min 0.1 min 10.0 min Thermal time constant
THMA 50 – 99 % 1% 80 % Thermal alarm setting.
(Percentage of THM setting.)
[THMEN] Off / On Off Thermal OL enable
[THMAEN] Off / On Off Thermal alarm enable
Note: THMIP sets a minimum level of previous load current to be used by the thermal element,
and is only active when testing ([THMRST] = “ON”).
Note: Ip sets a minimum level of previous load current to be used by the thermal element, and is
typically used when testing the element. For the majority of applications, Ip should be set to
zero, in which case the previous load current, Ip, is calculated internally by the thermal model,
providing memory of conditions occurring before an overload.
2.7 Breaker Failure Protection

When fault clearance fails due to a breaker failure, the breaker failure protection (BFP) clears the
fault by backtripping adjacent circuit breakers.
If the current continues to flow even after a trip command is output, the BFP judges it as a breaker
failure. The existence of the current is detected by an overcurrent element CBF provided for each
phase. For high-speed operation of the BFP, a high-speed reset overcurrent element (less than 20ms)
is used. The CBF element resets when the current falls below 80% of the operating value as shown
in Figure 2.7.1.
Pick-up
Drop-off
0 I
Drop-off/Pick-up=0.8
Figure 2.7.1 CBF element Characteristic
In order to prevent the BFP from starting by accident during maintenance work and testing, and thus
tripping adjacent breakers, the BFP has the optional function of retripping the original breaker. To
make sure that the breaker has actually failed, a trip command is made to the original breaker again
before tripping the adjacent breakers to prevent unnecessary tripping of the adjacent breakers
following the erroneous start-up of the BFP. It is possible to choose not to use retripping at all, or
use retripping with trip command plus delayed pick-up timer, or retripping with trip command plus
overcurrent detection plus delayed pick-up timer.
 37 
6 F 2 T 0 1 7 9
An overcurrent element and delayed pick-up timer are provided for each phase which also operate
correctly during the breaker failure routine in the event of an evolving fault.
The braker failure protection element (CBF1) input three phase currents from line CTs in the
transformer windings. The primary winding side of CBF element is CBF1, secondary winding side
is CBF2.
Scheme logic
BFP initiation is performed on a per-phase basis. Figure 2.7.2 shows the scheme logic for the BFP.
The BFP is started by single phase reclose initiation signals CBF_INIT-A to CBF_INIT-C or
three-phase reclose initiation signal CBF_INIT. (These signals are assigned by the PLC default
setting). These signals must continuously exist as long as the fault is present.
The backtripping signal to the adjacent breakers CBF TRIP is output if the overcurrent element
CBF operates continuously for the setting time of the delayed pick-up timer TBTC after initiation.
Tripping of adjacent breakers can be blocked with scheme switch [BTC].
There are two kinds of modes for the retrip signal to the original breaker CBF RETRIP, the mode in
which retrip is controlled by the overcurrent element CBF, and the direct trip mode in which retrip is
not controlled. The retrip mode together with the trip block can be selected with the scheme switch
[RTC]. In the scheme switch [RTC], “DIR” is the direct trip mode, and “OC” is the trip mode
controlled by the overcurrent element CBF.
Figure 2.7.3 shows a sequence diagram for the BFP when a retrip and backup trip are used. If the
circuit breaker trips normally, the CBF is reset before timer TRTC or TBTC is picked up and the
BFP is reset. As TRTC and TBTC start at the same time, the setting value of TBTC should include
that of TRTC.
If the CBF continues to operate, a retrip command is given to the original breaker after the setting
time of TRTC. Unless the breaker fails, the CBF is reset by retrip. TBTC does not time-out and the
BFP is reset. This sequence of events may happen if the BFP is initiated by mistake and unnecessary
tripping of the original breaker is unavoidable.
If the original breaker fails, retrip has no effect and the CBF continues operating and the TBTC
finally picks up. A trip command CBF TRIP is given to the adjacent breakers and the BFP is
completed.
The BFP protection can be disabled by the scheme switches [BTC] and [RTC] or the PLC signal
CBF BLOCK.
 38 
6 F 2 T 0 1 7 9
307
≥1 CBF1 TRIP
CBF1_OP- TBTC1
123 311 t 0 308
A & & CBF1 TRIP-A
124 CBF1_OP-
CBF1 B 312 t 0 309
CBF1 TRIP-B
125 & &
C
CBF1_OP-C
313 t 0 310
& & CBF1 TRIP-C
0.00 - 300.00s
[BTC1] ≥1 303
CBF1 RETRIP
+ TRTC1
"ON"
t 0 304
& CBF1 RETRIP-A
≥1
t 0 305
CBF1 RETRIP-B
& ≥1
t 0 306
& ≥1 CBF1 RETRIP-C
0.00 - 300.00s
1656 CBF1_INIT-A
≥1 &
1657 CBF1_INIT-B
≥1 &
1658 CBF1_INIT-C
≥1 &
Default setting
GEN._TRIP 1659 CBF1_INIT [RTC1]
+
"OC"
"DIR"
[APPL-CT]
+
"On" &
1570 CBF1_BLOCK 1
Note: CBF2 provides the same logic as CBF1.
Figure 2.7.2 Breaker Failure Protection Scheme Logic
 39 
6 F 2 T 0 1 7 9
Fault Start CBFP
Trip
Adjacent
breakers Closed Open
TRIP
Normal trip Retrip
Original
breakers Closed Open Open
Tcb Tcb
OCBF
Toc Toc
TBF1
TRTC
CBF
RETRIP
TBF2
TBTC
CBF
TRIP
Figure 2.7.3 Sequence Diagram
Setting
The setting elements necessary for the breaker failure protection and their setting ranges are as
follows:
CBF1, CBF2 0.10 – 2.00 pu (*) 0.01 pu 0.50 pu Overcurrent setting
TRTC1, TRTC2 0.00 – 300.00 s 0.01 s 0.50 s Retrip time setting
TBTC1, TBTC2 0.00 – 300.00 s 0.01 s 1.00 s Back trip time setting
[RTC1], [RTC2] Off / DIR / OC Off Retrip control
[BTC1], [BTC2] Off / On Off Back trip control
The overcurrent element CBF checks that the circuit breaker has opened and that the current has
disappeared. Therefore, since it is allowed to respond to load current, it can be set to 10 to 200% of
the rated current.
The settings of TRTC and TBTC are determined by the opening time of the original circuit breaker
(Tcb in Figure 2.7.3) and the reset time of the overcurrent element (Toc in Figure 2.7.3). The timer
setting example when using retrip can be obtained as follows.
Setting of TRTC = Breaker opening time + CBF reset time + Margin
= 40ms + 10ms + 20ms
= 70ms
Setting of TBTC = TCBF1 + Output relay operating time + Breaker opening time +
CBF reset time + Margin
= 70ms + 10ms + 40ms + 10ms + 10ms
= 140ms
If retrip is not used, the setting of the TBTC can be the same as the setting of the TRTC.
 40 
6 F 2 T 0 1 7 9
2.8 Inrush Current Detector

GRE160 provides to prevent incorrect operation from a magnetizing inrush current during
transformer energisation.
Inrush current detector ICD1 (primary side) and ICD2 (secondary side) are used to detect second
harmonic inrush current during transformer energisation and can be used to block the following
protections:
- 1OC1 to 2OC2
- 1OCI1 to 2OCI2
- 1EF1 to 2EF2
- 2EFI1 to 2EFI2
- 1NC1 and 1NC2
- 1NCI1 and 1NCI2
Blocking can be enabled or disabled by setting the scheme switches [∗OC∗-2F], [∗OCI∗-2F],
[∗EF∗-2F], [∗EFI∗-2F], [∗NC∗-2F] and [∗NCI∗-2F].
The ICD detects the ratio ICD-2f between the second harmonic current I2f and the fundamental
current I1f independently for each phase, and will operate if the ratio is larger than the setting value.
Figure 2.8.1 shows the characteristic of the ICD element and Figure 2.8.2 shows the ICD block
scheme. When ICD operates, OC, OCI, EF, EFI, NC and NCI elements are blocked independently.
The scheme logic of each element is shown in the previous sections.
I2f/I1f
|I2f|/|I1f|≥ICD-2f(%) & ICD
|I1f|≥ICDOC
ICD-2f(%)
0 ICDOC I1f
Figure 2.8.1 ICD Element Characteristic
100
A
101 ≥1 ICD1
ICD1
B
102
C
Note: ICD2 provides the same logic as ICD1.

Figure 2.8.2 ICD Block Scheme
Setting
The setting elements necessary for the ICD and their setting ranges are as follows:
ICD1-2f, ICD2-2f 10 – 50% 1% 15% Second harmonic detection
ICD1OC, ICD2OC 1.00 – 5.00 pu 0.01 pu 2.00 pu ICD threshold setting
 41 
6 F 2 T 0 1 7 9
2.9 Overvoltage Protection

GRE160-300A, 400A and 500A series provide two independent phase overvoltage elements each
having a programmable drop-off/pick-up (DO/PU) ratio. OV1 is programmable for inverse time
(IDMT) or definite time (DT) operation. OV2 has definite time characteristic only.
Figure 2.9.1 shows the characteristic of the overvoltage elements.
Pickup
Dropoff
0 V
Figure 2.9.1 Characteristic of Overvoltage Elements
The overvoltage protection element OV1 has an IDMT characteristic defined by equation (1)
following the form described in IEC 60255-127:
  
 k  + c
t (G ) =
TMS ×    
(1)
( )
a
 V − 1 
  Vs  
where:
t = operating time for constant voltage V (seconds),
V = energising voltage (V),
Vs = overvoltage setting (V),
TMS = time multiplier setting.
k, a, c = constants defining curve.
The IDMT characteristic is illustrated in Figure 2.9.2. In addition to the IDMT curve in Figure
2.9.2, a user configurable curve is available via scheme switche [OV1EN]. If required, set the
scheme switch [OV1EN] to “C” and set the curve defining constants k, a, c. These curves are
defined in Table 2.9.1.
Table 2.9.1 Specification of Inverse Time Curves
Curve Description k A c
“IDMT” 1 1 0
“C” (User Configurable) 0.000 – 30.000 0.00 – 5.00 0.000 – 5.000
by 0.001 step by 0.01 step by 0.001 step
The OV2 element is used for definite time overvoltage protection.
 42 
6 F 2 T 0 1 7 9
Definite time reset

The definite time resetting characteristic is applied to the OV1 element when the inverse time delay
is used.
If definite time resetting is selected, and the delay period is set to instantaneous, then no intentional
delay is added. As soon as the energising voltage falls below the reset threshold, the element returns
to its reset condition.
If the delay period is set to some value in seconds, then an intentional delay is added to the reset
period. If the energising voltage exceeds the setting for a transient period without causing tripping,
then resetting is delayed for a user-definable period. When the energising voltage falls below the
reset threshold, the integral state (the point towards operation that it has travelled) of the timing
function (IDMT) is held for that period.
This does not apply following a trip operation, in which case resetting is always instantaneous.
Both OV1 has a programmable drop-off/pick-up (DO/PU) ratio.
Overvoltage Inverse Time

Curves
1000.000
100.000
Operating Time (secs)
10.000
TMS = 10
TMS = 5
TMS = 2
1.000
TMS = 1
0.100
1 1.5 2 2.5 3
Applied Voltage (x Vs)
Figure 2.9.2 IDMT Characteristic
Scheme Logic
Figures 2.9.3 and 2.9.4 show the scheme logic of the overvoltage protection OV1 and OV2.
The OV1 protection provides selective definite time or inverse time characteristic as shown in
Figure 2.2.3. The definite time protection is enabled by setting [OV1EN] to “DT”, and trip signal
OV1 TRIP is given through the delayed pick-up timer TOV1. The inverse time protection is enabled
by setting [OV1EN] to “IDMT”, and trip signal OV1 TRIP is given.
Figure 2.9.4 shows the scheme logic of the definite time overvoltage protection OV2. The OV2
element gives trip signals OV2_TRIP through the delayed pick-up timer TOV2.
 43 
6 F 2 T 0 1 7 9
The OV1 and OV2 protection can be disabled by the scheme switches [OV1EN] and [OV2EN] or
the PLC signals OV1_BLOCK and OV2_BLOCK respectively.
150 TOV1
A & & t 0 332
OV1-A_TRIP
OV1 B 151 ≥1
C 152 & & t 0 333

OV1-B_TRIP
≥1
153 & & t 0 334
A OV1-C_TRIP
154
≥1
OV1 B 0.00 - 300.00s
INST
155
C
& 331
≥1 OV1_TRIP
[OV1EN] "DT"
≥1
+ &
"IDMT"
1584 OV1_BLOCK 1 &
Figure 2.9.3 OV1 Overvoltage Protection
156 TOV2
A & & t 0 336
OV2-A_TRIP
OV2 B 157
C 158 & & t 0 337

OV2-B_TRIP
[OV2EN]
& & t 0 338
+ OV2-C_TRIP
0.00 - 300.00s 335
1586 OV2_BLOCK 1 ≥1 OV2_TRIP
Figure 2.9.4 OV2 Overvoltage Protection

Setting
The table shows the setting elements necessary for the overvoltage protection and their setting
ranges.
OV1 10.0 – 200.0 V 0.1 V 120.0 V OV1 threshold setting
TOV1 0.00 – 300.00 s 0.01 s 1.00 s OV1 definite time setting. Required if [OV1EN] = DT.
TOV1M 0.05 – 100.00 0.01 1.00 OV1 time multiplier setting. Required if [OV1EN] = IDMT.
TOV1R 0.0 – 300.0 s 0.1 s 0.0 s OV1 definite time delayed reset.
OV1DPR 10 – 98 % 1% 95 % OV1 DO/PU ratio setting.
OV1-k 0.00-300.00 0.01 1.00 Configurable IDMT Curve setting of OV1
OV1-α 0.01-5.00 0.01 1.00 ditto
OV1-c 0.000-5.000 0.001 0.000 ditto
OV2 10.0 – 200.0 V 0.1 V 140.0 V OV2 threshold setting.
TOV2 0.00 – 300.00 s 0.01 s 1.00 s OV2 definite time setting.
OV2DPR 10 - 98 % 1% 95 % OV2 DO/PU ratio setting.
[OV1EN] Off/DT/IDMT/C Off OV1 Enable
[OV2EN] Off / On Off OV2 Enable
 44 
6 F 2 T 0 1 7 9
2.10 Undervoltage Protection

GRE160-300A, 400A and 500A series provide two independent phase undervoltage elements. UV1
is programmable for inverse time (IDMT) or definite time (DT) operation. UV2 has definite time
characteristic only.
Figure 2.10.1 shows the characteristic of the undervoltage elements.
0 V
Figure 2.10.1 Characteristic of Undervoltage Elements
The undervoltage protection element UV1 has an IDMT characteristic defined by equation (2)
following the form described in IEC 60255-127:
  
  + c
TMS ×  
k
t (G ) = a   (2)
 1 − V
 ( )
Vs  
where:
t = operating time for constant voltage V (seconds),
V = energising voltage (V),
Vs = undervoltage setting (V),
TMS = time multiplier setting.
k, a, c = constants defining curve.
The IDMT characteristic is illustrated in Figure 2.10.2. In addition to the IDMT curve in Figure
2.10.2, a user configurable curve is available via scheme switche [UV1EN]. If required, set the
scheme switch [UV1EN] to “C” and set the curve defining constants k, a, c. These curves are
defined in Table 2.10.1.
The UV2 element is used for definite time overvoltage protection.
Definite time reset

The definite time resetting characteristic is applied to the UV1 element when the inverse time delay
is used.
If definite time resetting is selected, and the delay period is set to instantaneous, then no intentional
delay is added. As soon as the energising voltage rises above the reset threshold, the element returns
to its reset condition.
If the delay period is set to some value in seconds, then an intentional delay is added to the reset
period. If the energising voltage is below the undervoltage setting for a transient period without
causing tripping, then resetting is delayed for a user-definable period. When the energising voltage
rises above the reset threshold, the integral state (the point towards operation that it has travelled) of
the timing function (IDMT) is held for that period.
 45 
6 F 2 T 0 1 7 9
This does not apply following a trip operation, in which case resetting is always instantaneous.
Undervoltage Inverse Time

Curves
1000.000
100.000
Operating Time (secs)
TMS = 10
10.000
TMS = 5
TMS = 2
TMS = 1
1.000
0 0.2 0.4 0.6 0.8 1
Applied Voltage (x Vs)
Figure 2.10.2 IDMT Characteristic
Scheme Logic
Figures 2.10.3 and 2.10.4 show the scheme logic of the undervoltage protection UV1 and UV2.
The UV1 protection provides a selective definite time or inverse time characteristic as shown in
Figure 2.10.3. The definite time protection is enabled by setting [UV1EN] to “DT”, and trip signal
UV1_TRIP is given through the delayed pick-up timer TUV1. The inverse time protection is
enabled by setting [UV1EN] to “IDMT”, and trip signal UV1_TRIP is given.
Figure 2.10.4 shows the scheme logic of the definite time undervoltage protection UV2. The UV2
element gives trip signals UV2_TRIP through the delayed pick-up timer TUV2.
The UV1 and UV2 protection can be disabled by the scheme switches [UV1EN] and [UV2EN] or
the PLC signals UV1_BLOCK and UV2_BLOCK respectively.
In addition, there is a user programmable voltage threshold VBLK. If all measured phase voltages
drop below this setting, then UV1 and UV2 are prevented from operating. This function can be
blocked by the scheme switch [VBLKEN]. The [VBLKEN] should be set to “OFF” (not used) when
the UV elements are used as fault detectors, and set to “ON” (used) when used for load shedding.
Note: The VBLK must be set lower than any other UV setting values.
Further, these protection can be blocked when VT failure (VTF) is detected.
 46 
6 F 2 T 0 1 7 9
160 TUV1
A & & t 0 342
UV1-A_TRIP
UV1 161 ≥1
B
162 & & t 0 343
C UV1-B_TRIP
≥1
163
A & & t 0 344
UV1-C_TRIP
UV1 B 164 ≥1
INST 0.00 - 300.00s
165
C
UVBLK 341
566 176
≥1 UV1_TRIP
A &
567 1 NON
UVBLK B & UVBLK
568 &
C
[VBLKEN]
+ &
"ON"
[UVTST]
+ "DT"
"OFF" [UV1EN]
≥1
+ "IDMT"
"C" ≥1
1588 UV1_BLOCK 1
Figure 2.10.3 UV1 Undervoltage Protection

166 TUV2
A & & t 0 346
167
UV2-A_TRIP
UV2 B
& t 0 347
C 168 & UV2-B_TRIP
[UV2EN]
+ & & t 0 348
UV2-C_TRIP
"ON"
NON UV BLK 0.00 - 300.00s
345
≥1 UV2_TRIP
1589 UV2_BLOCK 1
Figure 2.10.4 UV2 Undervoltage Protection

Setting
The table shows the setting elements necessary for the undervoltage protection and their setting
ranges.
UV1 5.0 – 130.0 V 0.1 V 60.0 V UV1 threshold setting
TUV1M 0.05– 100.00 0.01 1.00 UVI time multiplier setting. Required if [UV1EN] = IDMT.
TUV1 0.00 – 300.00 s 0.01 s 1.00 s UV1 definite time setting. Required if [UV1EN] = DT.
TUV1R 0.0 – 300.0 s 0.1 s 0.0 s UV1 definite time delayed reset.
UV1-k 0.00-300.00 0.01 1.00 Configurable IDMT Curve setting of UV1
UV1-α 0.01-5.00 0.01 1.00 ditto
UV1-c 0.000-5.000 0.001 0.000 ditto
UV2 5.0 – 130.0 V 0.1 V 40.0 V UV2 threshold setting.
TUV2 0.00 – 300.00 s 0.01 s 1.00 s UV2 definite time setting.
VBLK 5.0 - 20.0 V 0.1 V 10.0 V Undervoltage block threshold setting.
[UV1EN] Off/ DT/ IDMT/ C DT UV1 Enable
[VBLKEN] Off / On Off UV block Enable
[UV2EN] Off / On Off UV2 Enable
 47 
6 F 2 T 0 1 7 9
2.11 Frequency Protection

Providing two-stage frequency protection, GRE160 incorporates dedicated frequency measuring
elements and scheme logic for each stage. Each stage is programmable for underfrequency,
overfrequency or frequency rate-of-change protection on model 300A, 400A and 500A series.
Underfrequency protection is provided to maintain the balance between power generation capability
and loads. It is also used to maintain the frequency within the normal range by load shedding.
Overfrequency protection is typically applied to detect such an overfrequency condition caused by
disconnecting load from a particular generation location.
Frequency rate of change protection is applied to ensure that load shedding occurs very quickly
when the frequency change is very rapid.
2.11.1 Frequency element
Underfrequency element UF operates when the power system frequency falls under the setting value.
Overfrequency element OF operates when the power system frequency rises above the setting value.
These elements measure the frequency and check for underfrequency or overfrequency every 5
ms.They operate when the underfrequency or overfrequency condition is detected 16 consecutive
times.
The outputs of both the UF and OF elements are invalidated by undervoltage block element
(FRQBLK) operation during an undervoltage condition.
Figure 2.11.1 shows the characteristics for the UF and OF elements.
Hz
OF
OF setting
UF setting
UF
0 V
FVBLK setting
Figure 2.11.1 Underfrequency and Overfrequency Element
Scheme Logic
Figure 2.11.2 shows the scheme logic for the frequency protection in stage 1. The frequency element
FRQ1 can output a trip command under the condition that the system voltage is higher than the
setting of the undervoltage element FRQBLK (FRQBLK=1). The FRQ1 element is programmable
for underfrequency or overfrequency operation by the scheme switch [FRQ1EN].
The tripping can be disabled by the scheme switches [FRQ1EN] or PLC logic signal FRQ1
BLOCK.
The stage 2 (FRQ2) uses the same logic as that for FRQ1
 48 
6 F 2 T 0 1 7 9
TFRQ1
177 t 0 356
OF FRQ1_TRIP
FRQ1 & ≥1 & &
0.00 - 300.00s
1
UF
&
TFRQ2
178 t 0 357
OF FRQ2_TRIP
FRQ2 & ≥1 & &
0.00 - 300.00s
1
UF
&
181
FRQBLK 1 NON FRQBLK
[FRQ1EN] "OF"
"UF" ≥1
+
[FRQ2EN] "OF"
"UF" ≥1
+
1600 FRQ1_BLOCK 1
1601 FRQ2_BLOCK 1
Figure 2.11.2 Scheme Logic for Frequency Protection
Setting
The setting elements necessary for the frequency protection and their setting ranges are shown in the
table below.
FRQ1 -10.00 – +10.00 Hz 0.01 Hz -1.00 Hz FRQ1 frequency element setting
TFRQ1 0.00 – 300.00 s 0.01 s 1.00 s Timer setting of FRQ1
FRQ2 -10.00 – +10.00 Hz 0.01 Hz -1.00 Hz FRQ2 frequency element setting
TFRQ2 0.00 – 300.00 s 0.01 s 1.00 s Timer setting of FRQ2
FVBLK 40.0 – 100.0 V 0.1 V 40.0 V UV block setting
FRQ1EN Off / OF / UF Off FRQ1 Enable
FRQ2EN Off / OF / UF Off FRQ2 Enable
 49 
6 F 2 T 0 1 7 9
2.11.2 Frequency rate-of-change element
The frequency rate-of-change element calculates the gradient of frequency change (df/dt). GRE160
provides two rate-of-change elements, a frequency decay rate element (D) and a frequency rise rate
element (R). These elements measure the change in frequency (Δf) over a time interval (Δt=100ms),
as shown Figure 2.11.3 and calculate the Δf/Δt every 5 ms. They operate when the frequency
change exceeds the setting value 50 consecutive times.
Both D and R elements output is invalidated by undervoltage block element (FRQBLK) operation
during undervoltage condition.
Hz
Δf
Δt
sec
Figure 2.11.3 Frequency Rate-of-Change Element
Scheme Logic
Figure 2.11.4 shows the scheme logic of the frequency rate-of-change protection in stage 1. The
frequency rate-of-change element DFRQ1 can output a trip command under the condition that the
system voltage is higher than the setting of the undervoltage element FRQBLK (FRQBLK=1). The
DFRQ1 element is programmable for frequency decay rate or frequency rise rate operation by the
scheme switch [DFRQ1EN].
The tripping can be disabled by the scheme switches [DFRQ1EN] or PLC logic signal DFRQ1
BLOCK.
The stage 2 (DFRQ2) is the same logic of DFRQ1.
Setting
The setting elements necessary for the frequency protection and their setting ranges are shown in the
table below.
DFRQ1 0.1 – 15.0 Hz/s 0.1 Hz/s 0.5 Hz/s DFRQ1 element setting
DFRQ2 0.1 – 15.0 Hz/s 0.1 Hz/s 0.5 Hz/s DFRQ2 element setting
FVBLK 40.0 – 100.0 V 0.1 V 40.0 V UV block setting
DFRQ1EN Off / R / D Off DFRQ1 Enable
DFRQ2EN Off / R / D Off DFRQ2 Enable
 50 
6 F 2 T 0 1 7 9
184 360
OF DFRQ1_TRIP
DFRQ1 & ≥1 & &
1
UF
&
185 361
OF DFRQ2_TRIP
DFRQ2 & ≥1 & &
1
UF
&
222
FRQBLK 1 NON FRQBLK
[DFRQ1EN] "R"
"D" ≥1
+
[DFRQ2EN] "R"
"D" ≥1
+
1576 DFRQ1_BLOCK 1
1577 DFRQ2_BLOCK 1
Figure 2.11.4 Scheme Logic of Frequency Rate-of-change Protection
2.11.3 Trip Circuit
The trip circuit of the frequency protection is configured with the combination of FRQ trip and
DFRQ trip. The trip circuit is configured by the PLC function as shown in Figure 2.11.5.
FRQ1 TRIP 1680 FRQ_S1_TRIP

≥1 355
DFRQ1 TRIP ≥1 FRQ_TRIP
FRQ2 TRIP 1681 FRQ_S2_TRIP
≥1
DFRQ2 TRIP
By PLC
2.11.5 Frequency Protection Trip circuit
 51 
6 F 2 T 0 1 7 9
2.12 Overexcitation Protection

Overexcitation protection is applied to protect transformers from overvoltage and overfluxing
conditions on model 300A, 400A and 500A series.
Any single phase-to-phase connected voltage is used to detect overexcitation. Trip and alarm
characteristics, which are based on a measurement of the voltage/frequency ratio, are provided.
Figure 2.12.1 shows the scheme logic of overexcitation protection. Overexcitation element V/F
responds to voltage/frequency and outputs three signals. Signal T has an inverse time characteristic.
Signals H and A have high-set and low-set definite time characteristics respectively. Signal T and
signal H with a delayed pick-up timer TVFH are used for tripping. Signal A is used for alarm with
a delayed pick-up timer TVFA.
The V/F element has a reset feature with definite time reset. The reset time RT is set to match the
cooling characteristic that is the time for the protected transformer to reach a normal temperature
after releasing the overexitation condition.
431
T TVFH 430 437
≥1 V/F1_TRIP
V/F H 432 t 0 434 &
A 433 1 - 600s [V/FEN1]

+ 438
"ON" V/F2_TRIP
&
[V/FEN2]
+
"ON"
1582 V/F_BLOCK 1
TVFA
t 0 435 436
V/F-ALARM
[V/FA] &
1 - 600s
+
"ON"
1583 V/F-A_BLOCK 1
Figure 2.12.1 Scheme Logic of Overexcitation Protection
Overexcitation protection can trip two breakers. The breaker tripping signals V/F-1 and V/F-2 can
be blocked by the scheme switch [V/F EN1] and [V/F EN2] settings and V/F BLOCK signal.
Alarm signal V/F-A can be blocked by the scheme switch [V/FA] setting and V/F-A BLIOCK
signal..
 52 
6 F 2 T 0 1 7 9
Setting
The following shows the setting elements for the overexcitation protection and their setting ranges.
V 100.0 − 120.0V 0.1V 100.0V Transformer rated voltage / VT ratio
A 1.03 − 1.30(∗ ) 0.01 1.03 Alarm
L 1.05 − 1.30 0.01 1.05 Low level
H 1.10 − 1.40 0.01 1.40 High level
LT 1 − 600s 1s 600s Operation time at low level
(Inverse time curve)
HT 1 − 600s 1s 1s Operation time at high level
(Inverse time curve)
RT 60 − 3600s 1s 250s Reset time after removing
overexcitation condition
TVFH 1 − 600s 1s 10s Operating time at high level setting
(Definite time delay)
TVFA 1 − 600s 1s 10s Alarm time
(Definite time delay)
Scheme switch
[V/F1], [V/F2] Off/On (**) Enable or disable tripping
[V/FA] Off/On On Enable or disable alarm
(∗): Multiplier of (rated voltage) / (rated frequency)
(**): Refer to Appendix H for default setting.+
Figure 2.12.2 Setting Points
 53 
6 F 2 T 0 1 7 9
2.13 Voltage Controled Overcurrent Protection

A voltage controlled or voltage restrained inverse overcurrent protection OCV will respond to faults
that may occur on the lower voltage side of the transformer when the fault current may be lower than
the normal value certain type of fault. The OCV is equipped so that the relay can issue a trip signal
sensitively against a certain fault on lower voltage side when a current becomes lower than nominal
value.
Figure 2.13.1 shows the scheme logic of Voltage controlled overcurrent protection. The Voltage
controlled overcurrent protection element OCV can be selected either voltage controlled overcurrent
function “Cont” or voltage restrained overcurrent “Rest” function.
591 595
A & & OCV1-A TRIP
OCV 592 596
B & & OCV1-B TRIP
593 597 594
C & OCV1-C TRIP OCV1 TRIP
&
"Cont"
[OCV1EN] ≥1
≥1 &
+ ≥1
"Rest"
&
[OCV1-2F] & ≥1 &
+ "Block"
& &
ICD1
[OCVTP] "3POR"
1592 OCV1_BLOCK 1 +
"2OUTOF3"
Note: OCV2 provide the same logic as OCV1.
Figure 2.13.1 Scheme Logic of voltage controlled overcurrent Protection
Voltage controlled overcurrent function

The Voltage controlled overcurrent function can be changed the OCI element enable / disable by the
system voltage. When system voltage is higher than the setting of the voltage value, the OCI element
turned off. If the system voltage value exceed the setting value during OCI timer count-up, the OCI
timer counte is reseted.The Voltage Contorolled overcurrent function is enabled by the scheme
switch [OCVEN] = “Cont” setting.
(p.u.)
Ip
0 OCV V
(V)
Ip: Overcurrent element pick up current
OCV; Voltage controlled threshold voltage
Figure 2.13.2 Voltage Controlled overcurrent function pick-up zone
 54 
6 F 2 T 0 1 7 9
Voltage restrained overcurrent fucntion

The Voltage restrained overcurrent function can be changed the OCI pick up threshold level by the
system voltage. The change of the OCI threshold level is below.
1) 1.0 ≤ (input Voltage) OCV(V) … OCI threshold pick-up = 1.0 p.u. (Rated current)
2) 0.2 ≤ (input Voltage) OCV(V) < 1.0 … OCI threshold pick-up = (input Voltage) OCV(V)
3) (input Voltage) OCV(V) < 0.2 … OCI threshold pick-up = 0.2 p.u. (Rated current)
Ip: Overcurrent element pick up current

Ip
OCV; Voltage controlled
(p.u.) threshold voltage
1.0
0.2
0 0.2 1.0 V/OCV

(p.u.)
Figure 2.13.3 Voltage Restrained overcurrent function pick-up zone
The Voltage restrained overcurrent function is enabled by the scheme switch [OCVEN] = “Rest”
setting.
Setting
The following shows the setting elements for the voltage controlled overcurrent protection and their
setting ranges.
1OCV , 2OCV 10.00 − 120.00V 0.01V 70.00 Voltage threshold setting
1OCVIS, 2OCVIS 0.10 − 5.00(*) 0.01 1.00 Inverse time overcurrent if [OCV] = cont
T1OCVM, T2OCVM 0.010-15.000 0.001 1.000 OCV time multiplier setting.
T1OCVR, T2OCVR 0.0 – 300.0 s 0.1 s 0.0 s OCV definite time delayed reset. Required
if [M1OCVR] to [M2OCVR] = DEF.
T1OCVRM, 0.010-15.000 0.001 1.000 OCV dependent time delayed reset time
T2OCVRM multiplier. Required if [M1OCVR],
[M2OCVR] = DEP.
OCV userconfigurable curve setting
1OCV-k, 2OCV-k 0.00-30.000 0.001
1OCV-α, 2OCV-α 0.01-5.00 0.01
OCV userconfigurable curve setting.
1OCV-c, 2OCV-c 0.000-5.000 0.001
Required if [M1OCV], [M2OCV] = C.
1OCV-kr, 2OCV-kr 0.00-30.000 0.001
1OCV-β, 2OCV-β 0.01-5.00 0.01
 55 
6 F 2 T 0 1 7 9

Scheme switch
[M1OCV], [M2OCV] IEC/IEEE/US/C IEC OCV elements time characteristic
[M1OCVC-IEC], NI / VI / EI / LTI NI Required if [M1OCV] to [M2OCV] = IEC.
[M2OCVC-IEC]
[M1OCVC-IEEE], MI / VI / EI MI Required if [M1OCV] to [M2OCV] =
[M2OCVC-IEEE] IEEE.
[M1OC1V-US], CO2 / CO8 CO2 Required if [M1OCV] to [M2OCV] = US.
[M2OC2V-US]
[1OCVEN], Off / Cont / Rest Off OCV elements
[2OCVEN]
[M1OCVR], DEF / DEP DEF OCV reset characteristic. Required if
[M2OCVR] [M1OCV1] to [M2OCV2] = IEEE or US.
[1OCV-2F], NA / Block NA OC and OCI elements 2f-Lock enable.
[2OCV-2F]
[1OCVTP], 3POR / 2OUTOF3 3POR OC trip mode
[2OCVTP]
[OCV3PH] 1PH / 3PH 1PH Operation mode for 300A and 400A
[OCVREPH] AB / BC / CA AB Operation phase setting
[OCVCONT] ONE / BOTH ONE OCV element available side
(∗): Multiplier of (rated voltage) / (rated frequency)
Scheme switch setting of OCV3PH

The scheme switch [OCV3PH] is setting for OCV operating mode at 300A and 400A model. When
the [OCV3PH] is “1PH”, the operation phase is according to [OCVREPH] setting. The [OCV3PH]
is “3PH”, the operation phase is 3 phase regardless of voltage input phase.
Scheme switch setting of OCVREPH

The scheme swich [OCVREPH] is setting for the operation phase at 300A and 400A model and
[OCV3PH] “1P” setting. When the [OCVREPH] is “AB”, OCV operation phases are A phase and
B phase.
Scheme switch setting of OCVCONT

The scheme switch [OCVCONT] is setting for the operationg side for OCV operation at 300A,
400A and 500A model. When the [OCVCONT] is “ONE”, the operation side is according to
[VTLOC] setting. The [OCVCONT] is “BOTH”, the operation side is primary “1OCV” and
secondary “2OCV” regardless of voltage input side.
Primary Secondary
[OCV3PH] [OCV3PH]
[OCVREPH] [OCVREPH]
Transformer
1OCV 2OCV
[VTLOC] [OCVCONT] [VTLOC]
Figure 2.13.4 Voltage controlled overcurrent function scheme switch setting
 56 
6 F 2 T 0 1 7 9
2.14 Trip by External Devices

Up to four binary signals EXT. MECHANICAL TRIP1 to EXT. MECHANICAL TRIP4 can be
used for tripping external devices. Figure 2.14.1 shows the scheme logic for the signal
EXT_MEC.TP1. The signal can trip up to two breakers. Any of the tripping signals
EXT_MEC.TP1-1 to EXT_MEC.TP4-2 can be blocked by the scheme switches [M.T1-1] and
[M.T1-2] setting.
The other binary signals have the same scheme logic.
1700 490
EXT. MECHANICAL TRIP1 & M.1-1-TRIP
[M.T1-1]
+
491
& M.1-2-TRIP
[M.T1-2]
+
1704 MEC.TP1-BLK 1
Figure 2.14.1 Scheme Logic of Trip by External Device
Setting
The following shows the setting elements for tripping by external devices and their setting ranges.
Scheme switch Enable or disable tripping
M.T1-1 , -2
M.T2-1 , -2 Off/On (*)
M.T3-1 , -2
M.T4-1 , -2
(*): Default settings are dependent on the model. See Appendix H.
 57 
6 F 2 T 0 1 7 9
2.15 Tripping Output

Figure 2.15.1 shows the tripping logic. Each protection can output two tripping signals to enable
tripping for two breakers. The tripping signals are set according to the number of breakers to be
tripped and drive tripping output relays TRIP-1 and TRIP-2.
TRIP-1
DIF1-TRIP
1REF1-TRIP ≥1 369
2REF1-TRIP ≥1 TRIP-1
V/F1-TRIP
1OC1-TRIP
1OCI1-TRIP ≥1
1EF1-TRIP
1EFI1-TRIP
1NC1-TRIP
1NCI1-TRIP
2OC1-TRIP
2OCI1-TRIP ≥1
2EF1-TRIP
2EFI1-TRIP
2NC1-TRIP
2NCI1-TRIP
OCV1-TRIP
OV1-TRIP ≥1
UV1-TRIP
FREQ1-TRIP
CBF1-TRIP
M.1-1-TRIP
M.2-1 TRIP ≥1
M.3-1-TRIP
M.4.1-TRIP
TRIP-2
370
Same as TRIP-1 TRIP-2
Figure 2.15.1 Tripping Logic
 58 
6 F 2 T 0 1 7 9
2.16 Characteristics of Measuring Elements

2.16.1 Percentage Current Differential Element DIF
The segregated-phase current differential element DIF has dual percentage restraining
characteristics. Figure 2.16.1 shows the characteristics of DF1 and DF2 on the differential current
(Id) and restraining current (Ir) plane. Id is a vector summation of phase current of all windings and
Ir is a scalar summation of phase current of all windings.
Id Id = 2Ir (one-end infeed)
DF2
ik DF1
ik kp Ir
2
Figure 2.16.1 Current Differential Element
Characteristic DF1 is expressed by the following equation:

Id ≥ p1  Ir + (1 −p1/2)ik
where,
p1 : slope of DF1
ik : minimum operating current
Id and Ir are defined as follows for a two-winding transformer.
Id = | kct1⋅I1 + kct2⋅I2 |
Ir =(kct1⋅|I1 |+ kct2⋅|I2 |)/2
where,
kct1 ,kct2 : CT ratio matching factors of primary and secondary winding
I1 ,I2 : currents of primary and secondary winding
This characteristic has weaker restraint in the small current region and ensures sensitivity to low
level faults.
Id ≥ p2  Ir + (p1 −p2)kp + (1 −p1/2)ik
where,
p2 : slope of DF2
kp : break point of DF1 characteristic
This characteristic has stronger restraint in the large current region and ensures stability against CT
saturation during through faults.
 59 
6 F 2 T 0 1 7 9
2.16.2 High-set Overcurrent Element HOC
High-set overcurrent element HOC is an instantaneous overcurrent characteristic, and is applied in

the differential circuit. The characteristic is expressed by the following equation:
Id ≥ kh
Id is defined as follows for two-winding transformer.

Id = | kct1⋅I1 + kct2⋅I2 |
where,
kct1, kct2: CT ratio matching factors of primary and secondary winding
HOC is an un-restrained current differential element which can protect a transformer against
damage due to a heavy internal fault, because it has a simple operation principle and high-speed
operation. Note that HOC is not immune to transformer inrush currents and therefore cannot be
applied with a sensitive setting.
2.16.3 Restricted Earth Fault Element REF

The restricted earth fault element REF is composed of REF_DIF and REF_DEF, as was shown in
Figure 2.3.2.
The REF_DIF has dual percentage restraining characteristics. Figure 2.16.2 shows the
characteristics on the differential current (Id) and restraining current (Ir) plane. Id is the differential
current between the residual current of each winding and the neutral current and Ir is the restraining
current which is the larger of the residual current and the neutral current.
Id
DF2
max-kct⋅ik DF1
kp Ir
max-kct⋅ik
Figure 2.16.2 REF_DIF Characteristic

Id ≥ p1⋅Ir + (1-p1) ⋅ik⋅max-kct
where,
p1 : slope of DF1 (fixed to 10%)
ik : minimum operating current
max-kct : CT ratio matching of line CT to neutral CT (when plural line CTs are applied,
maximum kct is employed.)
For the 1REF element, Id and Ir are calculated by the following equations when applied to a circuit
with one neutral CT and two line CTs. (For the REF element application, see Appendix L.)
Id = |1kct1⋅I1o + 1kct2⋅I2o + IN |
Ir = max.( 1kct1⋅|I1a| , 1kct1⋅|I1b| , 1kct1⋅|I1c| , 1kct2⋅|I2a| , 1kct2⋅|I2b| , 1kct2⋅|I2c|, |IN| )
 60 
6 F 2 T 0 1 7 9
where,
I1o ,I2o : residual current of primary and secondary winding
I1a ,I1b ,I1c ,I2a ,I2b ,I2c : phase current of primary and secondary winding
IN : residual current of neutral circuit
1kct1, 1kct2: CT ratio matching of primary and secondary line CT to neutral CT
Id ≥ p2 (Ir−kp)
where
p2 : slope of DF2
kp : break point of DF1 characteristic
The characteristic of REF_DEF is composed of a directional characteristic and a non-directional

characteristic as shown in Figure 2.16.3 (a) and (b). This characteristic is employed so that the REF
is not blocked at one-end infeed current IN.
90°
(*1)
3I0
180° 0 0°
IN Ik2 3I0
Ik1
Operating
270°
Ik1, ik2: Current sensitivity (0.01pu, 0.025pu fixed)

IN: Neutral current of transformer
3I0: Zero sequence current (calculated from Ia, Ib, Ic)
*1: MAX(Ia,Ib,Ic) ≤ 2×MAX(kct1,kct2,kct3)
(a) (b)
Figure 2.16.3 REF_DEF Characteristic
The REF_DEF detects an internal fault by checking the direction between transformer neutral
current IN and zero-sequence current 3I0 calculated from phase currents Ia, Ib and Ic. The REF_DEF
is blocked when the maximum phase current is larger than 2 times of Max-kct as follows:
Max.(1kct1•I1a, ….1kct2•I2c) ≥ IBLK=Max.(1kct1,1kct2)×2
 61 
6 F 2 T 0 1 7 9
2.16.4 Inverse Time Overcurrent Element OCI and EFI
The OCI and EFI elements have one long time inverse characteristic and three inverse time
characteristics in conformity with IEC 60255-151 as shown in Figure 2.16.4. One of these
characteristics can be selected.
These characteristics are expressed by the following equations and curves.
(s) T=1.0
200
100
50
Long Time Inverse

120
t=T×
(I/Is)−1 20
Standard Inverse
0.14 10
t = T × (I/Is)0.02 − 1
Long-time Inverse
Very Inverse 5
13.5 Operating
t=T× time
(I/Is) − 1
Standard Inverse
2
Extremely Inverse
80
t = T × (I/Is)2 − 1
1
Very Inverse
where,
t : operating time
0.5
I : fault current
Is : current setting
T : time multiplier setting 0.2 Extremely Invease
0.1
1 2 5 10 20 30
Current I (Multiple of setting current)
Figure 2.16.4 Characteristics of Inverse Time Overcurrent Element
2.16.5 Definite Time Overcurrent element OC and EF
The OC and EF elements measure the phase currents and the residual current respectively.
 62 
6 F 2 T 0 1 7 9
2.16.6 Thermal Overload Element THR
Thermal overload element THM has a characteristic based on thermal replica according to the IEC
60255-149 standard (see Appendix N), which evaluates the largest phase current of the CT
secondary circuits. Figure 2.16.5 shows the characteristic of THM element.
 I2 
t =τ·Ln  2 2  (2)
 I − I AOL 
 I2 − I 2 
t =τ·Ln  2 2P  (3)
 I − I AOL 
where:
t = time to trip for constant overload current I (seconds)
I = overload current (largest phase current) (amps)
IAOL = allowable overload current (amps)
IP = previous load current (amps)
τ= thermal time constant (seconds)
Ln = natural logarithm
Figure 2.16.5 illustrates the IEC60255-149 curves for a range of time constant settings. The
left-hand chart shows the ‘cold’ condition where an overload has been switched onto a previously
un-loaded system. The right-hand chart shows the ‘hot’ condition where an overload is switched
onto a system that has previously been loaded to 90% of its capacity.
Thermal Curves (Cold Curve - Thermal Curves (Hot Curve -

no prior load) 90% prior load)
1000 1000
100
100
10
10
1
τ
τ
1 100
100
50 0.1 50
20 20
0.1 10 10
0.01
5
5
2
2
1
0.01 1 0.001
1 10 1 10
Overload Current (Multiple of IAOL) Overload Current (Multiple of
IAOL)
Figure 2.16.5 Thermal Curves
 63 
6 F 2 T 0 1 7 9
2.16.7 Overexcitation Element V/F
The characteristic is based on the ratio of voltage to frequency. The alarm is definite time delayed,
while the tripping characteristic is either definite time or inverse time, as shown in Figure 2.16.6.
A: Alarm level
H: High level (definite time tripping)
V/Hz L: Low level (pick up level)
HT: Operating time at high level
H LT: Operating time at low level
TVFH: Operating time at high level setting
TVFA: Alarm time
L
A
0 TVFA HT LT sec
TVFH (log T)
Figure 2.16.6 Characteristic of Overexcitation Element
The inverse time characteristic of V/F is expressed by the following equation.

K2
t = エラー! ブックマークが定義されていません。
(V/F) − K1
E
where,
t : operating time
V : voltage (any phase-to-phase voltage)
F : frequency
V/F=(Vm/Fm) / (Vs/Fs)
(Vm: Input voltage, Fm: Input frequency, Vs: Setting of rated voltage, Fs: Rated frequency)
(LT) × L − (HT) × H
K1=
(LT) − (HT)
A E
(LT) × (HT) × (H − L)
K2=
(LT) − (HT)
A E
The V/F element has a reset feature with definite time reset (RT). When the V/F falls below the reset
threshold, the integral state of the inverse time function is reset to the initial value after the RT time.
Example: V/F=(Vin/Fin)/(V/Fs)=(130/50)/(100/50)=1.3, in case of Vin: Input voltage (130V),
Fin: Input frequency (50Hz), V: Rated voltage (100V), Fs: Rated frequency (50Hz)
 64 
6 F 2 T 0 1 7 9
3. Technical Description
3B
3.1
24B Hardware Description
3.1.1 Outline of Hardware Modules
The case outline of GRE160 is shown in Appendix F.

As shown in Figure 3.1.1, the human machine interface (HMI) panel has a liquid crystal display
(LCD), light emitting diodes (LED), operation keys and a USB type-B connector on the front panel.
The LCD consists of 16 columns by 8 rows (128 x 64dots) with a back-light and displays recording,
status and setting data.
There are a total of 14 LED indicators and their signal labels and LED colors are defined as follows:
Label Color Remarks
IN SERVICE Green Lit when the relay is in service and flashing when the relay is in “Test”
menu.
TRIP Red Lit when a trip command is issued.
ALARM Yellow Lit when relay alarm is detected.
Relay Fail Red Lit when a relay failure is detected.
CB CLOSED Red/Green/ Lit when CB is closed.
Yellow
CB OPEN Green Lit when CB is open.
LOCAL Yellow Lit when Local Control is enabled
REMOTE Yellow Lit when Remote Control is enabled
(LED1) Red/Green/ User-configurable
Yellow
Yellow
Yellow
Yellow
Yellow
Yellow
LED1 to LED6 are user-configurable. Each is driven via a logic gate which can be programmed for
OR gate or AND gate operation. Further, each LED has a programmable reset characteristic,
settable for instantaneous drop-off, or for latching operation. A configurable LED can be
programmed to indicate the OR combination of a maximum of 4 elements, and the LED color can be
changed to one of three colors- (Red / Green / Yellow) , the individual status of which can be viewed
on the LCD screen as “Virtual LEDs.” For the setting, see Section 4.2.6.10. For the operation, see
Section 4.2.1.
The TRIP LED and an operated LED, if latching operation is selected, must be reset by the user,
 65 
6 F 2 T 0 1 7 9
either by pressing the RESET key, by energising a binary input which has been programmed for
‘Remote Reset’ operation, or by a communications command. Other LEDs operate as long as a
signal is present. The RESET key is ineffective for these LEDs. Further, whether or not the TRIP
LED is lit is controlled with the scheme switch [AOLED] by the output of an alarm element such as
THM ALARM.
The CB CLOSED and CB OPEN LEDs indicate CB condition. The CB CLOSED LED color can
be changed to one of three colors-(Red / Green / Yellow) .
The LOCAL / REMOTE LED indicates the CB control hierarchy. When the LOCAL LED is lit, the
CB can be controlled using the ○ and ｜ keys on the front panel. When the REMOTE LED is lit,
the CB can be controlled using a binary input signal or via relay communications. When neither of
these LEDs are lit , the CB control function is disabled.
The VIEW key, same as ▼ key, starts the LCD indication and switches between windows. The
VIEW key will scroll the screen through “Virtual LED” → “Metering” →”Indication and
back-light off” when the LCD is in the Digest screen mode.
The ENTER key starts the Main menu indication on the LCD.
The END key clears the LCD indication and turns the LCD back-light off when the LCD is in the
“MAIN MENU”.
The operation keys are used to display the record, status and setting data on the LCD, input settings
or change settings.
The USB connector is a B-type connector. This connector is used for connection with a local
personal computer.
Light emitting
Liquid crystal
diodes (LED)
display
Operation keys
Control keys
Figure 3.1.1 Front Panel USB connector

(type B)
 66 
6 F 2 T 0 1 7 9
3.2
25B Input and Output Signals
3.2.1 Input Signals
AC input signals
Table 3.2.1 shows the AC input signals necessary for the GRE160 models and their respective input
terminal numbers. See Appendix G for external connections.
Winding 1 and 2 in the Table correspond to high-voltage or primary and low-voltage or secondary
winding respectively. All input signals detection depend upon their scheme switch [APPL] setting
and VT mounted position (primary side or secondary side) is set by [VTLOC] setting.
Table 3.2.1 AC Input Signals
Terminal AC input element GRE160- GRE160- GRE160- GRE160- GRE160-

No.
100,101,102 200,201,202 300,301,302 400,401,402 500,501,502
TB4
1-2 A phase current of winding 1     
3-4 B phase current of winding 1     
5-6 C phase current of winding 1     
7-8 Neutral current of winding 1   
TB5
1-2 A phase current of winding 2     
3-4 B phase current of winding 2     
5-6 C phase current of winding 2     
7-8 Neutral current of winding 2   
TB5
1-2 A phase voltage input   
3-4 B phase voltage input 
5-6 C phase voltage input 
7-8 Zero phase voltage input 
Setting
The following shows the setting for AC input application. ([APPL])
Scheme switch
APPLCT Off/On On Enable or disable current input
APPLVT Off/On Off Enable or disable phasevoltage input
APPLVE Off/On Off Enable or disable Zerophase input
VTLOC pre / sec pre VT mounted position setting
 67 
6 F 2 T 0 1 7 9
3.2.2 Binary Input Signals

The GRE160 provides 6 (Model 100/200/300/400/500), 12 (Model 101/201/301/401/501) or 18
(Model 102/202/302/402/502) programmable binary input circuits. Each binary input circuit is
programmable by PLC function, and provided with the function of Logic level inversion.
Logic level inversion and detection threshold voltage change

The binary input circuit of the GRE160 is provided with a logic level inversion function, a pick-up
and drop-off delay timer function and a detection threshold voltage change as shown in Figure 3.2.1.
Each input circuit has a binary switch BISNS which can be used to select either normal or inverted
operation. This allows the inputs to be driven either by normally open or normally closed contacts.
Where the driving contact meets the contact conditions then the BISNS can be set to “Norm”
(normal). If not, then “Inv” (inverted) should be selected. The pick-up and drop-off delay times can
be set 0.0 to 300.00s respectively.
The binary input detection nominal voltage is programmable by the user, and the setting range varies
depending on the rated DC power supply voltage. In the case that a 110V / 220Vdc rated model is
ordered, the input detection nominal voltage can be set to 48V, 110V or 220V for BI1 and BI2, and
to 110V or 220V for the other BIs. In the case of a 24 / 48Vdc model, the input detection nominal
voltage can be set to 12V, 24V or 48V for BI1 and BI2, and to 24V or 48V for the other BIs.
The binary input detection threshold voltage (i.e. minimum operating voltage) is normally set at 77V
and 154V for supply voltages of 110V and 220V respectively. In case of 24V and 48V supplies, the
normal thresholds are 16.8V and 33.6V respectively. Binary inputs can be configured for operation
in a Trip Circuit Supervision (TCS) scheme by setting the [TC1SPEN] switch for primary side and
[TC2SPEN] switch for secondary side to “Enable”. In case TCS using 2 binary inputs is to be
applied (refer to Section 3.3.3), then the binary input detection threshold of BI1 and BI2 should be
set to less than half of the rated dc supply voltage. The TCS using 2 binary inputs available for only
one side (primary or secondary) of CB trip circuit.
The logic level inversion function, pick-up and drop-off delay timer and detection voltage change
settings are as follow:
Element Contents Range Step Default
BI1SNS – BI(*)SNS Binary switch Norm/ Inv Norm
BITHR1 BI1-2 threshold Voltage 48 / 110 / 220 110
(12 / 24 / 48 ) (24)
BITHR2 BI3-(*) threshold voltage 110 / 220 (24 / 48) 110 (24)
TC1SPEN, TCS enable Off / On / Opt-On Off
TC2SPEN
BI1PUD – BI(*)PUD Delayed pick-up timer 0.00 - 300.00s 0.01s 0.00
BI1DOD – BI(*)DOD Delayed drop-off timer 0.00 - 300.00s 0.01s 0.00
(*):The number of binary inputs. The model *00 has 6 binary inputs,
the model *01 has 12 binary inputs, the model *02 has 18 binary inputs.
The binary input signals can be programmed to switch between two settings groups. Change of
active setting group is performed by PLC (Signal No. 2640 and 2641).
Four alarm messages (Alarm1 to Alarm4) can be set. The user can define a text message within 16
characters for each alarm. The messages are valid for any of the input signal BIs by setting. When
inputs associated with that alarm are raised, the defined text is displayed on the LCD. These alarm
 68 
6 F 2 T 0 1 7 9
output signals are signal Nos. 2560 to 2563.

GRE160
(+) (−) BI1PUD BI1DOD [BI1SNS]
BI1 t 0 0 t
BI1 command
BI1
"Norm"
1
"Inv"
BI2PUD BI2DOD [BI2SNS]
BI2 t 0 0 t
BI2 command
BI2
"Norm"
[BITHR1]
1
+ "Inv"
"220V"
BI3 +
"110V"
+
"48V"
BI(*)PUD BI(*)DOD [BI(*)SNS
BI(*) t 0 0 t ]
BI(*) BI(*) command
"Norm"
[BITHR2] 1
+ "Inv"
"220V"
+
"110V"
0V
Figure 3.2.1 Logic Level Inversion
Function selection
The input signals BI1 COMMAND to BI6 COMMAND are used for the functions listed in Table
3.2.2. Each input signal can be allocated for one or some of those functions by setting. For setting,
refer to Section 4.2.6.8.
The Table also shows the signal name corresponding to each function used in the scheme logic and
LCD indication and driving contact condition required for each function.
3.2.3 Binary Output Signals
The number of binary output signals and their output terminals are as shown in Appendix F. All
outputs, except the relay failure signal, can be configured.
The signals shown in the signal list in Appendix B can be assigned to the output relay BOs
individually or in arbitrary combinations. The output relays BO1 and BO2 connect to CB1 OPEN /
CLOSE for CB1 control, BO3 and BO4 connect to CB2 OPEN / CLOSE for CB2 control. The CB
close control switch ｜ is linked to BO1 or BO3 and the CB open control switch ○ is linked to
BO2 or BO4, when the control function is enabled.
The reset time of the tripping output relay following fault clearance can be programmed. The setting
is respective for each output relay.
The signals shown in the signal list in Appendix B can be assigned to the output relay BOs
individually or in arbitrary combinations. Signals can be combined using either an AND circuit or
 69 
6 F 2 T 0 1 7 9
an OR circuit with 6 gates each as shown in Figure 3.2.2. The output circuit can be configured
according to the setting menu. Appendix H shows the factory default settings.
Further, each BO has a programmable reset characteristic, settable for instantaneous drop-off
“Ins”, for delayed drop-off “Dl”, for dwell operation “Dw” or for latching operation “Lat” by the
scheme switch [RESET]. The time of the delayed drop-off “Dl” or dwell operation “Dw” can be set
by TBO. When “Dw” is selected, the BO operates for the TBO set time if the input signal does not
continue longer than the TBO set time. If the duration of the input signal exceeds the TBO set time,
the BO output is continuous for the input signal time.
When the relay is latched, it can be reset with the RESET key on the relay front panel or a binary
input. This resetting resets all the output relays collectively.
The relay failure contact closes when a relay defect or abnormality in the DC power supply circuit
is detected.
Signal List
& Auxiliary relay

6 GATES
Appendix B
or ≥1
≥1
6 GATES
&
TBO
0 t
&
[RESET] "Dw" 0.00 – 10.00s
+ "Dl"
& S
F/F
"Lat"
R
Reset button
+
≥
768 By PLC
BI1_COMMAND 1639 IND.RESET
Figure 3.2.2 Configurable Output
Settings
The setting elements necessary for binary output relays and their setting ranges are as follows:
[RESET] Ins / Dl / Dw /Lat See Appendix C Output relay reset time. Instantaneous,
delayed, dwell or latched.
[Logic] OR / AND See Appendix C BO gate logic.
TBO 0.00 – 10.00s 0.01s See Appendix C BO output timer.
 70 
6 F 2 T 0 1 7 9
3.2.3 PLC (Programmable Logic Controller) Function
GRE160 is provided with a PLC function allowing user-configurable sequence logics on binary
signals. The sequence logics with timers, flip-flops, AND, OR, NOT logics, etc. can be produced by
using the PC software “PLC tool” and linked to signals corresponding to relay elements or binary
circuits.
Configurable binary inputs, binary outputs and LEDs, and the initiation trigger of disturbance
record are programmed by the PLC function. Temporary signals are provided for complicated
logics or for using a user-configured signal in many logic sequences.
PLC logic is assigned to protection signals by using the PLC editor tool. For PLC tool, refer to PLC
tool instruction manual.
Figure 3.2.3 Sample Screen of PLC Tool
 71 
6 F 2 T 0 1 7 9
3.3
26B Automatic Supervision
3.3.1 Basic Concept of Supervision
Though the protection system is in a non-operating state under normal conditions, it is waiting for a
power system fault to occur at any time and must operate for the fault without fail. Therefore, the
automatic supervision function, which checks the health of the protection system during normal
operation by itself, plays an important role. A numerical relay based on microprocessor technology
is able to implement such as automatic supervision function. GRE160 implements an automatic
supervision function based on the following concept:
• The supervising function should not affect protection performance.
• Perform supervision with no omissions wherever possible.
• When a failure occurs, it should be possible to easily identify the failure location.
• Under relay failure detection , CB open control is enabled, but CB close control is disabled.
3.3.2 Relay Monitoring and Testing
The relay is supervised with the following items.
AC input imbalance monitoring

The AC current input is monitored such that the following equation is satisfied and the health of the
AC input circuit is checked.
• CT circuit current monitoring for [APPLCT] = “On” setting
Max(|Ia|, |Ib|, |Ic|) − 4 × Min(|Ia|, |Ib|, |Ic|) ≥ k0
where,
Max(|Ia|, |Ib|, |Ic|) = Maximum amplitude among Ia, Ib and Ic
Min(|Ia|, |Ib|, |Ic|) = Minimum amplitude among Ia, Ib and Ic
k0 = 20% of rated current

• Zero sequence voltage monitoring at 500 model.
|Va + Vb + Vc| / 3 ≤ 6.35 (V)
• Negative sequence voltage monitoring at 500 model.
|Va + a2Vb + aVc| / 3 ≤ 6.35 (V)
where, a = Phase shift of 120°, a2 = Phase shift of 240°
The CT circuit current monitoring allows high sensitivity detection of failures that have occurred in
the AC input circuit. This monitoring can be disabled by scheme switch [CT1SVEN] at primary
side and [CT2SVEN] at secondary side..
The zero sequence monitoring and negative sequence monitoring allow high sensitivity detection of
failures that have occurred in the AC input circuits. These monitoring functions can be disabled by
scheme switches [V0SVEN] and [V2SVEN] respectively at 500 model.
The negative sequence voltage monitoring allows high sensitivity detection of failures in the voltage
input circuit, and it is effective for detection particularly when cables have been connected with the
incorrect phase sequence at 500 model.
 72 
6 F 2 T 0 1 7 9
A/D accuracy checking

An analogue reference voltage is transmitted to a prescribed channel in the analogue-to-digital
(A/D) converter, and it is checked that the data after A/D conversion is within a prescribed range
and that the A/D conversion characteristics are correct.
Memory monitoring
The memories are monitored as follows depending on the type of the memory and checked that the
memory circuits are healthy:
• Random access memory monitoring:
Writes/reads prescribed data and checks the storage function.
• Program memory monitoring: Checks the checksum value of the written data.
• Setting value monitoring: Checks discrepancy between the setting values stored in
duplicate.
Watchdog Timer
A hardware timer which is cleared periodically by software is provided and it is checked that the
software is running normally.
Power Supply monitoring

The secondary voltage level of the built-in voltage converter is monitored and checked that the DC
voltage is within a prescribed range.
3.3.3 Trip Circuit Supervision

The circuit breaker tripping control circuit can be monitored by either one or two binary inputs, as
described below.
Trip Circuit Supervision using 1 binary input

The circuit breaker tripping control circuit can be monitored using a single binary input. Figure
3.3.3 shows a typical scheme. A binary input BIn is assigned to No.1632:TC1_FAIL signal by
PLC. When the trip circuit is complete, a small current flows through the binary input and the trip
circuit. Then logic signal of the binary input circuit BIn is "1".
If the trip supply is lost or if a connection becomes open circuit, then the binary input resets and the
BIn output is "0". A trip circuit fail alarm TC1SV is output when the BIn output is "0".
If a trip circuit failure is detected, then “ALARM” LED is lit and “Err: TC” is displayed in LCD
message.
Monitoring is enabled by setting the scheme switch [TC1SPEN] to "ON" or "OPT-ON" and the one
BI selected "TCFAIL". When "OPT-ON" is selected, monitoring is enabled only while CB is closed.
TC2SV for CB2 provide the same logic as TC1SV.
(+) Trip circuit supervision
BIn
Trip t 0 1270
1632 TC1_FAIL 1 & TC1SV
output
CB CLOSE 0.4s
& ≥1
"OPT-ON"
[TC1SPEN]
"ON"
+
CB1 trip coil
Figure 3.3.3 Trip Circuit Supervision Scheme Logic
 73 
6 F 2 T 0 1 7 9
Trip Circuit Supervision using 2 binary inputs

The circuit breaker tripping control circuit can also be monitored in either the breaker closed or open
condition using two binary inputs. Figure 3.3.4 shows a typical scheme. At CB closed condition, the
monitoring current flows in the photo-coupler BI1. On the other hand, at CB opened condition, the
monitoring current flows in photo-coupler BI1 of BI2 via tripping cable, circuit breaker auxiliary
contacts and the trip coil. This current flows for both the breaker open and closed conditions.
If the trip circuit supply is lost or if a connection becomes open circuit then the TCS issues a Trip
Circuit Fail alarm.
Monitoring is enabled by setting the scheme switch [TC1SPEN] to "ON" or "OPT-ON" and the two
BIs selected "TCFAIL". When "OPT-ON" is selected, monitoring is enabled only while CB is
closed. TCS by 2BIs should be applied using BI1 and BI2 for the BI inputs. The TCS with 2BIs sets
the BI threshold voltage ([BITHR1]) to approximately half of the trip supply voltage. If the trip
supply voltage is 110V (or 24V) , [BITHR1] sets "48" (or "12").
The TCS using 2 binary inputs available for only one CB trip circuit (CB1 or CB2).
The resistors on the BI1 and BI2 photo coupler circuits should be added as shown in Figure 3.3.4
below in consideration of the fail-safe of relay failure
GRE140 Circuit Breaker
Trip Output CB Aux. CB Trip Coil -ve Trip

+ve
Contacts Supply
Trip
Supply
Resistor
Binary Input Binary Input

(BI1) (BI2)
Figure 3.3.4 Scheme Logic of Trip Circuit Supervision using 2 binary inputs
3.3.6 Circuit Breaker Monitoring

The relay provides the following circuit breaker monitoring functions.
Circuit Breaker State Monitoring

Circuit breaker state monitoring is provided for checking the health of a circuit breaker (CB). If two
binary inputs are programmed to the functions ‘CB1_N/O_CONT’ and ‘CB1_N/C_CONT’, then
the CB state monitoring function becomes active. In normal circumstances these inputs are in
opposite states. Figure 3.3.5 shows the scheme logic. If both show the same state for a duration of
five seconds, then a CB state alarm CBSV operates and “Err:CB1” and “CB1 err” are displayed in
an LCD message and event record message respectively.
The monitoring can be enabled or disabled by setting of scheme switch [CB1SMEN].
t 0 1272
1633 CB1_N/O_CONT 1 CB1SV
≥1 &
5.0s
1634 CB1_N/C_CONT
[CB1SMEN]
"ON"
+
Figure 3.3.5 CB1 State Monitoring Scheme Logic
 74 
6 F 2 T 0 1 7 9
Normally open and normally closed contacts of the CB are connected to binary inputs BIm and BIn
respectively, and functions of BIm and BIn are assigned to “CB1_N/O_CONT” and
“CB1_N/C_CONT” by PLC.
CB2SV for CB2 provide the same logic as CB1SV.
Circuit Breaker Condition Monitoring

Periodic maintenance of a CB is required for checking the trip circuit, the operation mechanism and
the interrupting capability. Generally, maintenance is based on a time interval or a number of fault
current interruptions.
The following CB condition monitoring functions are provided to determine the time for
maintenance of the CB:
• Trip is counted for maintenance of the trip circuit and CB operating mechanism. The trip
counter increments the number of tripping operations performed. An alarm is issued and informs
the user of the time for maintenance when the count exceeds a user-defined setting TC1ALM and
TC2ALM.
The trip count alarm can be enabled or disabled by setting the scheme switch [TC1AEN] and
[TC2AEN].
The counter can be initiated by PLC signals TP_COUNT and TP_COUNT-∗. The default
setting is the TP_COUNT and is assigned to the GEN_TRIP signal.
• Operating time monitoring is provided for CB mechanism maintenance. It checks CB operating
time and the need for mechanism maintenance is informed if CB operation is slow. The operating
time monitor records the time between issuing the tripping signal and the phase currents falling
to zero. An alarm is issued when the operating time for any phase exceeds a user-defined setting
OPT1ALM and OPT2ALM. The operating time is set in relation to the specified interrupting
time of the CB. The operating time alarm can be enabled or disabled by setting the scheme switch
[OPT1AEN] and [OPT2AEN].
The CB operating time monitoring feature can be initiated by PLC signals OT_ALARM_A to
OT_ALARM_C. The default settings for OT_ALARM_A to OT_ALARM_C are assigned to
the GEN_TRIP signal.
The maintenance program should comply with the switchgear manufacturer’s instructions.
3.3.5 Failure Alarms

When a failure is detected by the automatic supervision, it is followed with an LCD message, LED
indication, external alarm and event recording. Table 3.3.1 summarizes the supervision items and
alarms.
The LCD messages are shown on the "Auto-supervision" screen, which is displayed automatically
when a failure is detected or displayed by pressing the VIEW key. The event record messages are
shown on the "Event record" screen by opening the "Record" sub-menu.
The alarms are retained until the failure is recovered.
The alarms can be disabled collectively by setting the scheme switch [AMF] to "OFF". The AC
input imbalance monitoring alarms can be disabled collectively by setting the scheme switches
[CT1SVEN], [CT2SVEN], [V0SVEN] and [V2SVEN] to "OFF". The setting is used to block
unnecessary alarms during commissioning, test or maintenance.
When the Watchdog Timer detects that the software is not running normally, LCD display and event
recording of the failure may not function normally.
 75 
6 F 2 T 0 1 7 9
Table 3.3.1 Supervision Items and Alarms
Supervision Item LCD LED LED LED Event record Message

Message "IN SERVICE" "ALARM" "Relay fail"
Err:CT1, CT1 err,CT2 err,
AC input imbalance Err:CT2,
On/Off (2) On (4) V0 err, V2 err,
monitoring Err:V0,
Err:V2 (1) Relay fail or Relay fail-A (2)
A/D accuracy check Err:A/D Off On (4) Relay fail
Memory monitoring Err:SUM,
Err:RAM,
Off On (4) Relay fail
Err:BRAM,
Err:EEP
Watchdog Timer ---- Off On (4) ----
Power supply monitoring Err:DC Off (3) Off Relay fail-A
Trip circuit supervision Err:TC1 On On Off TC1 err, TC2err, Relay fail-A
Err:TC2
CB state monitoring Err:CB1 On On Off CB1 err, CB2 err, Relay fail-A
Err:CB2
CB condition monitoring ALM:TP TP COUNT ALM,
On On Off
Trip count alarm COUNT Relay fail-A
Operating time alarm ALM: OP time On On Off OP time ALM, Relay fail-A
(1): Various messages are provided as expressed with "Err:---" in the table in Section 6.7.2.
(2): The LED is on when the scheme switch [CT1SVEN], [CT2SVEN], [V0SVEN] or [V2SVEN] is
set to "ALM" and off when set to "ALM & BLK" (refer to Section 3.3.6). The message "Relay
fail-A" is recorded when the scheme switch [SVCNT] is set to "ALM".
(3): Whether the LED is lit or not depends on the degree of the voltage drop.
(4): The binary output relay "FAIL" operates except for DC supply fail condition.
The failure alarm and the relationship between the LCD message and the location of the failure is
shown in Table 6.7.1 in Section 6.7.2.
3.3.8 Trip Blocking
When a failure is detected by the following supervision items, the trip function is blocked as long as
the failure exists, and is restored when the failure is removed.
• A/D accuracy check
• Memory monitoring
• Watchdog Timer
When a fault is detected by the AC input imbalance monitoring function, the scheme switches
[CT1SVEN], [CT2SVEN], [V0SVEN] and [V2SVEN] setting can be used to determine if both
tripping is blocked and an alarm is output, or if only an alarm is output.
 76 
6 F 2 T 0 1 7 9
3.3.7 Setting
The setting element necessary for the automatic supervision and its setting range are shown in the
table below.

Trip counter supervision
TC1ALM 1 - 10000 1 10000 Trip counter alarm setting for CB1
TC2ALM 1 - 10000 1 10000 Trip counter alarm setting for CB2
CB Operation time supervision
OPT1ALM 100 – 5000ms 1 ms 1000ms CB operation time alarm setting for CB1
OPT2ALM 100 – 5000ms 1 ms 1000ms CB operation time alarm setting for CB2
[CB1SVEN], Off / On Off AC input imbalance monitoring (current)
[CB2SVEN]
[TC1AEN], Off / On Off Trip counter Alarm monitoring
[TC2AEN]
[OPT1AEN], Off / On Off CB Operation time Alarm monitoring
[OPT2AEN]
[CT1SVEN], Off/ALM&BLK/ALM Off AC input imbalance monitoring (current)
[CT2SVEN]
[V0SVEN] Off/ALM&BLK/ALM Off AC input imbalance monitoring (Vo)
[V2SVEN] Off/ALM&BLK/ALM Off AC input imbalance monitoring (V2)
 77 
6 F 2 T 0 1 7 9
3.4
27B Recording Function
GRE160 is provided with the following recording functions:
Fault recording
Event recording
Disturbance recording
These records are displayed on the LCD of the relay front panel or on the local or remote PC.
3.4.1 Fault Recording

Fault recording is started by a tripping command of the GRE160 or PLC command by user-setting
and the following items are recorded for one fault:
Date and time of fault occurrence
Operating phase or fault phase
Tripping command
Tripping mode
Relevant events
Power system quantities
User configurable initiation
Up to the 4 most-recent faults can be stored as fault records. If a new fault occurs when 4 faults have
been stored, the record of the oldest fault is deleted and the record of the latest fault is then stored, the
oldest fault record is deleted and the record of the latest fault is then stored.
Date and time of fault occurrence

The time resolution is 1ms using the relay internal clock.
To be precise, this is the time at which a tripping command has been initiated, and thus it is
approximately 10 ms after the occurrence of the fault.
Operating phase or fault phase

The operating phase or fault phase can be selected to be displayed following tripping, depending on
the requirements of user.
Tripping mode
This shows the protection scheme that initiated the tripping command.
Faulted phase
This is the phase to which an operating command is output.
Relevant events
Such events as autoreclose, re-tripping following the reclose-on-to-a fault or autoreclose are
recorded with time-tags.
Tripping command
The tripping output relay(s) operated is shown in terms of its number (e.g. CB1, CB2.).
 78 
6 F 2 T 0 1 7 9
Power system quantities

The following power system quantities for pre-fault and post-fault are recorded.
- Magnitude and phase angle of phase current of each winding (Ia1, Ib1, Ic1 up to Ia3, Ib3, Ic3)
- Magnitude and phase angle of neutral current of each winding (In1 up to In3)
- Magnitude and phase angle of symmetrical component current of each winding (I11, I21, I01 up
to I12, I22, I02)
- Magnitude and phase angle of phase-to-phase voltage (V)
- Magnitude of phase differential current (Ida, Idb, Idc)
- Magnitude of phase residual current (Ira, Irb, Irc)
- Magnitude of residual differential current for REF protection (Id01, Id02)
- Magnitude of residual current for REF protection (Ir01 , Ir02)
- Percentage of thermal capacity (THM%)
- Frequency (f)
Phase angles above are expressed taking that of the voltage as a reference phase angle. If the voltage
input is not provided, then the positive sequence current of the primary winding is used as a
reference phase angle.
3.4.2 Event Recording

The events shown are recorded with a 1 ms resolution time-tag when the status changes. Up to 200
records can be stored. If an additional event occurs when 200 records have been stored, the oldest
event record is deleted and the latest event record is then stored.
The user can set a maximum of 128 recording items, and their status change mode. The event items
can be assigned to a signal number in the signal list. The status change mode is set to “On” (only
recording On transitions) or “On/Off”(recording both On and Off transitions) mode by setting. The
“On/Off” mode events are specified by the “Bi-trigger events” setting. If the “Bi-trigger events” is
set to “100”, No.1 to 100 events are “On/Off” mode and No.101 to 128 events are “On” mode.
The name of an event can be set by RSM100. A maximum of 22 characters can be set, but the LCD
displays only 11 characters. Therefore, it is recommended that a maximum of 11 characters are set.
The set name can be viewed on the Set.(view) screen.
The elements necessary for event recording and their setting ranges are shown in the table below.
The default setting of event record is shown in Appendix G.
BITRN 0 - 128 1 100 Number of bi-trigger(on/off) events
EV1 – EV128 0 - 3071 Assign the signal number
3.4.3 Disturbance Recording

Disturbance Recording is started when overcurrent starter elements operate or a tripping command
is output, or PLC command by user-setting (max. 4: Signal No. 2632 to 2635) is output. The
records include 12 analog signals (primary: Ia1, Ib1, Ic1, In1, secondary: Ia2, Ib2, Ic2, In2, voltage:
Va, Vb, Vc, Vn), 32 binary signals and the dates and times at which recording started. Any binary
signal in shown in Appendix B can be assigned by the binary signal setting of disturbance record.
The default setting of binary signal is shown in Appendix H.
 79 
6 F 2 T 0 1 7 9
The LCD display only shows the dates and times of disturbance records stored. Details can be
displayed on a PC. For how to obtain disturbance records on the PC, see the PC software instruction
manual.
The pre-fault recording time can be set between 0.1 and 4.9s and the post-fault recording time can be
set between 0.1 and 3.0s. But the total for the pre-fault and post-fault recording time is 5.0s or less.
The number of records stored depends on the post-fault recording time. The approximate
relationship between the post-fault recording time and the number of records stored is shown in
Table 3.4.2.
Note: If the recording time setting is changed, the records stored so far are deleted.
Table 3.4.2 Fault Recording Time and Number of Disturbance Records Stored
Recording time 0.1s 0.5s 1.0s 1.50s 2.0s 2.5s 3.0s

50Hz 40 25 15 10 9 7 6
60Hz 40 20 10 9 7 6 6
Note: Recording time = pre-fault recording time + post-fault recording time.
Disturbance recording is initiated when overcurrent elements operate, a tripping signal is output, 2F
or 5F element operates or external event signals are input. Three phase overcurrent elements 1OCPS
and 2OCPS are applied to the line CTs and neutral overcurrent elements 1OCPG and 2OCPG to the
neutral CTs.
The initiations are blocked by the scheme switches.
Settings
The elements necessary for starting disturbance recording and their setting ranges are shown in the
table below.
Time1 0.1-4.9 s 0.1 s 2.0 Pre-fault recording time
Time2 0.1-4.9 s 0.1 s 2.0 Post-fault recording time
1OCPS 0.10 - 20.00(*) 0.01 Phase overcurrent element
2OCPS 0.10 - 20.00(*) 0.01
1OCPG 0.05 - 20.00(*) 0.01 Neutral overcurrent element
2OCPG 0.05 - 20.00(*) 0.01
OV 10.0-200.0 V 0.1 V 120.0 V Overvoltage detection
UV 1.0-130.0 V 0.1 V 60.0 V Undervoltage detection
Scheme switch ON/OFF Initiating disturbance record
TRIP1and TRIP2 by tripping
1OCPS, 2OCPS by phase overcurrent element
1OCPG, 2OCPG by neutral overcurrent element
2F by 2F element
5F by 5F element
EVENT1 to EVENT3 by external event
OV by phase overvoltage element
UV by phase undervoltage element
(*) : Multiplier of CT secondary rated current
 80 
6 F 2 T 0 1 7 9
3.5
28B Metering Function
The GRE160 performs continuous measurement of the analogue input quantities. The measurement
data shown below are displayed on the LCD of the relay front panel or on the local or remote PC.
- Magnitude of phase current of each winding (Ia1, Ib1, Ic1, Ia2, Ib2, Ic2)
- Magnitude of neutral current of each winding (Ie1, Ie2)
- Magnitude of symmetrical component current of each winding (I11, I21, I01, I12, I22, I02)
- Magnitude of phase voltage (Va, Vb, Vc, Vph)
- Magnitude of phase-to-phase voltage (Vab, Vbc, Vca)
- Magnitude of zero sequence voltage which is measured directly in the form of the system residual
voltage (Ve)
- Magnitude of symmetrical component voltage (V1, V2, V0)
- Magnitude of phase differential current (Ida, Idb, Idc)
- The ratio of negative to positive sequence current (I2/I11, I2/I12)
- Magnitude of differential current between the residual current and each phase current
(Ira, Irb, Irc)
- Magnitude of differential current between the residual current of each windings and neutral
current (Id01, Id02)
- Magnitude of differential current between the residual current and neutral current (Ir01, Ir02)
- Percentage of thermal capacity (THM%)
- Frequency (f)
- Frequency rate of change(df)
- Power factor (PF)
- Active power (P)
- Reactive power (Q)
- Apparent power (S)
- watt-hour (WH)
- var-hour (varH)
Demand
- Maximum of phase current (Ia1, Ib1, Ic1, Ia2, Ib2, Ic2 : max.)
- Maximum of zero sequence current from residual circuit (Ie1 , Ie2 : max)
- Maximum of the ratio of negative to positive sequence current (I2/I1(I21), I2/I11(I211),
I2/I2(I22), I2/I12(I212): max)
- Maximum and minimum of phase voltage (Va, Vb, Vc: max, min)
- Maximum and minimum of zero sequence voltage (V0: max, min)
- Maximum and minimum of the system residual voltage (Ve: max, min)
- Maximum of active power (P: max.)
- Maximum of reactive power (Q: max.)
- Maximum of apparent power (S: max.)
- Maximum and minimum of frequency (f: max, min)
- Maximum and minimum of frequency rate of change (df: max, min)
The above system quantities are displayed in values on the primary side or on the secondary side of
the CT according to a setting. To display accurate values, it is necessary to set the CT ratio and VT
ratio too. For the setting method, see "Setting the transformer parameters" in 4.2.6.7.
The displayed quantities depend on relay model are as shown in Table 3.5.1. Input current and
voltage greater than 0.01×In(rated current) and 0.06V at the secondary side are required for the
measurement.
 81 
6 F 2 T 0 1 7 9
Table 3.5.1 Displayed Quantity

Model 100 200 300 400 500
Ia1, Ia2     
Ib1, Ib2     
Ic1, Ic2     
Ie1, Ie2   
 
I01, I02   
I11, I21     
I12, I22     
I2/I12     
THM     
Va 
Vb 
Vc 
Vph   --
Ve 
Vab 
Vbc 
Vca 
V1 
V2 
V0 
f   
df   
PF 
P 
Q 
S 
WH+, - 
varH+, - 
 82 
6 F 2 T 0 1 7 9
4. User Interface
4B
4.1
29B Outline of User Interface
The user can access the relay from the front or rear panel.
Local communication with the relay is also possible using RSM (Relay Setting and Monitoring) via
a USB port. Furthermore, remote communication is also possible using either MODBUS or
IEC60870-5-103 communication protocols via the RS485 port.
This section describes the front panel configuration and the basic configuration of the menu tree for
the local human machine communication ports and HMI (Human Machine Interface).
4.1.1 Front Panel
As shown in Figure 3.1.1, the front panel is provided with a liquid crystal display (LCD), light
emitting diodes (LED), operation keys, and USB type B connector.
LCD
The LCD screen, provided with an 8-line, 16-character display and back-light, provides the user
with information such as records, status and settings. The LCD screen is normally unlit, but
pressing the VIEW key will display the digest screen and pressing the ENTER key will display
the main- menu screen.
These screens are turned off by pressing the END key when viewing the LCD display at the top of
the main-menu. If any display is left for about 5 minutes without operation, the back-light will go
off.
LED
There are 14 LEDs. The signal labels and LED colors are defined as follows:
Label Color Remarks
IN SERVICE Green Lit when the relay is in service and flashing when the relay is in “Test”
menu.
TRIP Red Lit when a trip command is issued.
ALARM Yellow Lit when an alarm command is issued or a relay alarm is detected.
Relay Fail Red Lit when a relay failure is detected.
CB CLOSED R /G / Y Lit when CB is closed.
CB OPEN Green Lit when CB is open.
Local Yellow Lit when Local Control is enabled
Remote Yellow Lit when Remote Control is enabled
(LED1) R/G/Y user-configurable
 83 
6 F 2 T 0 1 7 9
LED1-6 are configurable. For setting, see Section 4.2.6.10.

The TRIP LED lights up once the relay is operating and remains lit even after the trip command goes
off. The TRIP LED can be turned off by pressing the RESET key. Other LEDs are lit as long as a
signal is present and the RESET key is invalid while the signal is being maintained.
Operation keys
The operation keys are used to display records, status, and set values on the LCD, as well as to input
or change set values. The function of each operation key is as follows:
 ▼, ▲,
▲
, ▼: Used to move between lines displayed on a screen and to enter numerical
values and text strings.
 CANCEL : Used to cancel entries and return to the upper screen.
 END : Used to end the entering operation, return to the upper screen or turn off the
display.
 ENTER : Used to store or establish entries.
VIEW and RESET keys

Pressing the VIEW key displays digest screens such as "Metering", "Latest fault",
"Auto-supervision", "Alarm display" and "Indication". The VIEW key is the same as the ▼ key.
Pressing the RESET key causes the Trip LED to turn off and any latched output relays to be
released.
Control key
The control keys are used for CB control. When the cursor of the LCD display is not at the CB
control position-(CB close/open , Local / Remote), the Control key does not function.
 ○ : Used for CB open operation. When CB is in the open position, the ○ key does not
function.
② ｜ : Used for CB close operation. When CB is in the closed position, the ｜ key does not
function
③ L/R : Used for CB control hierarchy (local / remote) change.
USB connector
The USB connector is a B-type connector for connection with a local personal computer.
 84 
6 F 2 T 0 1 7 9
4.1.2 Communication Ports
The following two interfaces are provided as communication ports:

• USB port
• RS485 port
• IRIG-B port
• Optional Fiber optic or Ethernet LAN port for serial communication
• Optional Communication Unit port
USB port
This connector is a standard B-type connector for USB transmission and is mounted on the front
panel. By connecting a personal computer to this connector, setting operation and display functions
can be performed.
IRIG-B port
The IRIG-B port collects serial IRIG-B format data from an external clock to synchronize the relay
calendar clock. The IRIG-B port is isolated from the external circuit by a photo-coupler.
This port is on the back of the relay, as shown in Figure 4.1.1.
RS485 port
The RS485 port is used for MODBUS or IEC60850-5-103 communication to connect between
relays and to construct a network communication system. (See Figure 4.4.1 in Section 4.4.)
The RS485 port is provided on the rear of the relay as shown in Figure 4.1.1.
Optional Fibre or Ethernet LAN port

Optional Ethernet LAN port can be connected to an automation system via an Ethernet
communication networks using the IEC 61850 protocol. 100Base-TX (T1: RJ-45 connector) or
100Base-FX (F1: SC connector) for Ethernet LAN is provided at the rear of the relay as shown in
Figure 4.1.1.
Optional secondary RS485 port and Optional Ethernet port are CANNOT be used at the same time.
 85 
6 F 2 T 0 1 7 9
TB6 TB5 TB4 TB3 TB2 TB1
1 2 1 2 1 2
3 4 3 4 3 4
5 6 5 6 5 6
7 8 7 8 7 8
9 10 9 10 9 10
Standard 11 12 11 12 11 12
RS485 13 14 13 14
13 14
terminal 15 16 15 16
IRIG-B 　Optional 　Optional Secondary

Communication Port RS485 terminal
SC connector or
RJ45
Figure 4.1.1 Locations of Communication Port
4.2 Operation of the User Interface

The user can access such functions as recording, measurement, relay setting and testing with the
LCD display and operation keys.
4.2.1 LCD and LED Displays
Displays during normal operation

When the GRE160 is operating normally, the green "IN SERVICE" LED is lit and the LCD is off.
When the LCD is off press the VIEW key to display the digest screens which are "Indication",
"Metering", "Latest fault", "Auto-supervision" and the "Alarm Display" screens in turn. The "Latest
fault", "Auto-supervision" and "Alarm Display" screens are displayed only when there is some data.
The following are the digest screens and can be displayed without entering the menu screens.
Indication
I N D 1 [ 0 0 0 0 0 0 0 0 ]
I N D 2 [ 0 0 0 0 0 0 0 0 ]
 86 
6 F 2 T 0 1 7 9
Metering
I a 1 * * . * * k A
I b 1 * * . * * k A
I c 1 * * . * * k A
I e 1 * * . * * k A Not available for model 100, 300 series
I a 2 * * . * * k A
I b 2 * * . * * k A
I c 2 * * . * * k A
I e 2 * * . * * k A Not available for model 100, 300 series
I d a * . * * p u
I d b * . * * p u
I d c * . * * p u
I r a * . * * p u
I r b * . * * p u
I r c * . * * p u
I d 0 1 * . * * p u
I d 0 2 * . * * p u
I r 0 1 * . * * p u
I r 0 2 * . * * p u
V p h * * * . * * k V Not available for model 100, 200, 500 series
V a * * * . * * k V Not available for model 100, 200, 300, 400 series
V b * * * . * * k V Not available for model 100, 200, 300, 400 series
V c * * * . * * k V Not available for model 100, 200, 300, 400 series
V e * * . * * * k V Not available for model 100, 200, 300, 400 series
V a b * * . * * * k V Not available for model 100, 200, 300, 400 series
V b c * * . * * * k V Not available for model 100, 200, 300, 400 series
V c a * * . * * * k V Not available for model 100, 200, 300, 400 series
To clear the latched indications (LEDs, LCD screen for the Latest fault), press the RESET key for
3 seconds or more.
For any display, the back-light is automatically turned off after five minutes.
Indication
This screen shows the status of elements assigned as a virtual LED.
I N D 1 [ 0 0 0 0 0 1 0 0 ]
I N D 2 [ 0 0 0 1 0 0 0 0 ]
Status of element,
Elements depend upon user setting. 1: Operate, 0: Not operated (Reset)
 87 
6 F 2 T 0 1 7 9
Displays in tripping
Latest fault
P h a s e A B C : Faulted phases
D I F T : Tripping element
If a fault occurs and a tripping command is output when the LCD is off, the red "TRIP" LED and
other configurable LEDs if signals are assigned to them triggered by tripping
Press the VIEW key to scroll the LCD screen to read the rest of the messages.
Press the RESET key for more than 3s to turn off the LEDs; the Trip LED and configurable LEDs
(LED1 through LED6) that have been assigned as latched signals will be triggered by tripping.
To return from the menu screen to the digest "Latest fault" screen, do the following:
• Return to the top screen of the menu by repeatedly pressing the END or CANCEL key.
• Press the END key to turn off the LCD when the LCD is displaying the top menu.
• Press the VIEW key to display the digest screens.
Displays in automatic supervision operation

Auto-supervision
E r r : R O M , A / D
If the automatic supervision function detects a failure while the LCD is off, the "Auto-supervision"
screen is displayed automatically, showing the location of the failure, and the "ALARM" LED
lights.
Press the VIEW key to display other digest screens in turn including the "Metering" and "Latest
fault" screens.
Press the RESET key to turn off the LEDs. However, if the failure continues, the "ALARM" LED
remains lit.
After recovery from a failure, the "ALARM" LED and "Auto-supervision" display turn off
automatically.
If a failure is detected while any of the other screens are being displayed, the current screen remains
displayed and the "ALARM" LED lights.
While any of the menu screens are displayed, the VIEW and RESET keys do not function. To
return to the digest "Auto-supervision" screen, do the following:
• Return to the top screen of the menu by repeatedly pressing the END or CANCEL key.
• Press the END key to turn off the LCD.
• Press the VIEW key to display the digest screen.
 88 
6 F 2 T 0 1 7 9
Alarm Display
Alarm Display (ALM1 to ALM4)
* * * * * * * * * * * * * *
* * * * * * * * : A L M 1
Four alarm screens can be provided, and their text messages are defined by the user. (For setting, see
Section 4.2.6.8) These alarms are raised by associated binary inputs.
Press the VIEW key to display other digest screens in turn including the "Metering" and "Latest
fault" screens.
To clear the Alarm Display, press the RESET key. Clearing is available after displaying up to
ALM4.
 89 
6 F 2 T 0 1 7 9
4.2.2 Relay Menu

Figure 4.2.1 shows the menu hierarchy in the GRE160. The menu has five sub-menus, "Record",
"Status", "Set. (view)", "Set. (change)", "Control" and "Test". For details of the menu hierarchy, see
Appendix E.
MAIN MENU Record Fault
Event
Disturbance
Counter
Status Metering
Binary I/O
Relay element
Time sync.
Clock adjust.
LCD contrast
Set. (view) Version
Description
Comms
Record
Status
Protection
Binary I/P
Binary O/P
LED
Control
Frequency
Set. (change) Password
Description
Comms
Record
Status
Protection
Binary I/P
Binary O/P
LED
Control
Frequency
Control Password(Ctrl)
Local / Remote
CB1 close/open
CB2 close/open
Test Password(Test)
Switch
Binary O/P
Figure 4.2.1 Relay Menu
 90 
6 F 2 T 0 1 7 9
Record
In the "Record" menu, the fault records, event records and disturbance records are displayed or
erased.
Status
The "Status" menu displays the power system quantities, binary input and output status, relay
measuring element status, signal source for time synchronisation (BI, IEC60870-5-103), clock
adjustment and LCD contrast.
Setting (view)
The "Set. (view)" menu displays the relay version, plant name, relay address and baud rate in
communication, the current settings of record, status, protection, binary inputs, configurable binary
outputs and configurable LEDs.
Setting (change)
The "Set. (change)" menu is used to change the settings of password, plant name, relay address and
baud rate in communication, record, status, protection, binary inputs, configurable binary outputs
and configurable LEDs.
Since this is an important menu and is used to change settings related to relay tripping, it has
password security protection.
Control
The "Control" menu is used to operate the CB. When the cursor (>) is in the Local / Remote position,
the CB control location change over key L/R is enabled. When the cursor (>) is in the CB1
close/open or CB2 close/open position, the CB1 or CB2 control keys ○ and ｜ are enabled.
Since this is an important menu and is related to relay tripping, it has password security protection.
Test
The "Test" menu is used to set testing switches, to forcibly operate binary output relays.This menu
also has password security protection.
When the LCD is off, press the ENTER key to display the top "MAIN MENU" screen and then
proceed to the relay menus.
M A I N M E N U
＞ R e c o r d
S t a t u s
S e t . ( v i e w )
S e t . ( c h a n g e )
C o n t r o l
T e s t
To display the "MAIN MENU" screen when the digest screen is displayed, press the VIEW key to
turn off the LCD, then press the ENTER key.
 91 
6 F 2 T 0 1 7 9
Press the END key when the top screen is displayed to turn off the LCD.
An example of the sub-menu screen is shown below. The top line shows the hierarchical layer. The
last item is not displayed for all the screens. " " , " " or " " displayed on the far right shows that
lower or upper lines exist.
To move the cursor downward or upward for setting or for viewing other lines not displayed on the
window, use the ▼ and ▲ keys.
/ 7 D I F p r o t .
D I F E N _
> D I F E N 1
O f f / O n
H O C E N 1
O f f / O n
D I F E N 1 1
O f f / O n
D I F E N 2 0
O f f / O n
D I F T P M D 0
3 P O R / 2 P A N D / 1 P
2 f - l o c k 0
O f f / O n
5 f - l o c k 0
O f f / O n
P h a s e m o d e 0
O p e r a t i n g / F a u l T
C T S E N
O f f / O n
To return to the higher screen or move from the right side screen to the left side screen in Appendix
E, press the END or CANCEL key.
The CANCEL key can also be used to return to the higher screen but it must be used carefully
because it may cancel entries made so far.
To move between screens of the same hierarchical depth, first return to the higher screen and then
move to the lower screen.
4.2.3 Displaying Records
The sub-menu of "Record" is used to display fault records, event records and disturbance records.
4.2.3.1 Displaying Fault Records
To display fault records, do the following:
• Open the top "MAIN MENU" screen by pressing any keys other than theエラー! ブックマー
クが定義されていません。 ENTER key.
• Select "Record" to display the "Record" sub-menu.
 92 
6 F 2 T 0 1 7 9
/ 1 R e c o r d
＞ F a u l t
E v e n t
D i s t u r b a n c e
C o u n t e r
• Select "Fault" to display the "Fault" screen.
/ 2 F a u l t
＞ V i e w r e c o r d
C l e a r
• Select "View record" to display the dates and times of fault records stored in the relay from the
top in new-to-old sequence.
/ 3 F a u l t
＞ ♯ 1 0 1 / J a n / 2 0 1 2
0 0 : 0 0 : 0 0 . 0 0 0
♯ 2 0 1 / J a n / 2 0 1 2
0 0 : 0 0 : 0 0 . 0 0 0
♯ 3 0 1 / J a n / 2 0 1 2
0 0 : 0 0 : 0 0 . 0 0 0
• Move the cursor to the fault record line to be displayed using the ▲ and ▼ keys and press the
ENTER key to display the details of the fault record.
/ 4 F a u l t ♯ 1
0 1 / J a n / 2 0 1 2
0 0 : 0 0 : 0 0 . 0 0 0
D I F T
P h a s e A B C
T R I P - 1 - 2
P r e f a u l t v a l u e s
I a 1 * * * . * * k A
I b 1 * * * . * * k A
I c 1 * * * . * * k A
I e 1 * * * . * * k A Not available for model 100, 300 series
 93 
6 F 2 T 0 1 7 9
I a 2 * * . * * * A
I b 2 * * * . * * k A
I c 2 * * * . * * k A
I 1 1 * * . * * * A
I 2 1 * * * . * * k A
I 0 1 * * * . * * k A
I 1 2 * * * . * * k A
I 2 2 * * * . * * k A
I 0 2 * * * . * * k A
V a * * * . * * k V Not available for model 100, 200 series*
V a b * * * . * * k V Not available for model 100, 200, 300, 400 series
V b c * * * . * * k V Not available for model 100, 200, 300, 400 series
V c a * * * . * * k V Not available for model 100, 200, 300, 400 series
V 1 * * * . * * k V Not available for model 100, 200, 300, 400 series
V O * * * . * * k V Not available for model 100, 200, 300, 400 series
I 2 / I 1 1 * * . * *
I 2 / I 1 2 * * . * *
T H M * * * . * %
I d a * * * . * * p u
I d b * * * . * * p u
I d c * * * . * * p u
I r a * * * . * * p u
I r b * * * . * * p u
I r c * * * . * * p u
I d o 1 * * * . * * p u
I d o 2 * * * . * * p u
I r o 1 * * * . * * p u
I r o 2 * * * . * * p u
ｆ * * . * * H z Not available for model 100, 200 series
d f - * * . * * H z / s Not available for model 100, 200 series
P F - * . * * * Not available for model 100, 200 series
F a u l t v a l u e s
I a 1 * * * . * * k A
I b 1 * * * . * * k A
I c 1 * * * . * * k A
I a 2 * * . * * * A
 94 
6 F 2 T 0 1 7 9
I b 2 * * * . * * k A
I c 2 * * * . * * k A
I 1 1 * * . * * * A
I 2 1 * * * . * * k A
I 0 1 * * * . * * k A
I 1 2 * * * . * * k A
I 2 2 * * * . * * k A
I 0 2 * * * . * * k A
V a * * * . * * k V Not available for model 100, 200 series*
I 2 / I 1 1 * * . * *
I 2 / I 1 2 * * . * *
T H M * * * . * %
I d a * * * . * * p u
I d b * * * . * * p u
I d c * * * . * * p u
I r a * * * . * * p u
I r b * * * . * * p u
I r c * * * . * * p u
I d o 1 * * * . * * p u
I d o 2 * * * . * * p u
I r o 1 * * * . * * p u
I r o 2 * * * . * * p u
* In 300, 400 model, the part of “Va”display “Vph”.
The lines which are not displayed in the window can be displayed by pressing the ▲ and ▼ keys.
To clear all the fault records, do the following:

• Open the "Record" sub-menu.
 95 
6 F 2 T 0 1 7 9

• Select "Clear" to display the following confirmation screen.
C l e a r r e c o r d s
E N D = Y C A N C E L = N
• Press the END (= Y) key to clear all the fault records stored in back-up RAM.
If all fault records have been cleared, the "Latest fault" screen of the digest screens is not displayed.
Note: When changing the units (kA/A) of primary side current with RSM100, press the "Units"
button which is indicated in the primary side screen.
4.2.3.2 Displaying Event Records

To display event records, do the following:
• Open the top "MAIN MENU" screen by pressing the ENTER key.

• Select "Event" to display the "Event" screen.
/ 2 E v e n t
C l e a r
• Select "Display" to display the events with date from the top in new-to-old sequence.
/ 3 E v e n t
2 4 / A ｕ g / 2 0 1 2 1 0 0
1 O C 1 - A t r i p O n
2 4 / A ｕ g / 2 0 1 2 0 9 9
1 O C 1 - A t r i p O N
2 2 / A ｕ g / 2 0 1 2 9 8
1 O C 1 - A t r i p O n
1 0 / J ｕ l / 2 0 1 2 0 0 4
1 O C 1 - A t r i p O n
1 0 / J ｕ l / 2 0 1 2 0 0 3
1 O C 1 - A t r i p O n
2 9 / J ｕ n / 2 0 1 2 0 0 2
1 O C 1 - A t r i p O n
 96 
6 F 2 T 0 1 7 9
1 0 / M a y / 2 0 1 2 0 0 1
1 O C 1 - A t r i p O n
▼
The time is displayed by pressing the key.
/ 3 E v e n t
1 3 : 2 2 : 4 5 . 2 1 1
1 O C 1 - A t r i p O n
1 3 : 2 2 : 4 5 . 2 0 0
1 O C 1 - A t r i p O N
1 3 : 2 2 : 4 5 . 1 1 1
1 O C 1 - A t r i p O n
1 3 : 2 2 : 4 4 . 2 1 1
1 O C 1 - A t r i p O N
1 3 : 2 2 : 4 4 . 2 0 0
1 O C 1 - A t r i p O N
1 3 : 2 2 : 4 4 . 1 1 1
1 O C 1 - A t r i p O n
1 3 : 2 2 : 4 4 . 1 0 0
1 O C 1 - A t r i p O n
▲
Press the key to return to the screen with date.
To clear all the event records, do the following:

• Select "Event" to display the "Event" screen.
• Press the END (= Y) key to clear all the event records stored in back-up RAM.
"Data lost" or "E.record CLR" and "F.record CLR" are displayed at the initial setting.
 97 
6 F 2 T 0 1 7 9
4.2.3.3 Displaying Disturbance Records

Details of disturbance records can be displayed on the PC screen only (*); the LCD displays only the
recorded date and time for all disturbances stored in the relay. They are displayed in the following
sequence.
(*) For the display on the PC screen, refer to RSM100 manual.

• Select "Disturbance" to display the "Disturbance" screen.
/ 2 D i s t u r b a n c e
C l e a r
• Select "View record" to display the date and time of the disturbance records from the top in
new-to-old sequence.
♯ 1 0 1 / J a n / 2 0 1 2
0 0 : 0 0 : 0 0 . 0 0 0
♯ 2 0 1 / J a n / 2 0 1 2
0 0 : 0 0 : 0 0 . 0 0 0
♯ 3 0 1 / J a n / 2 0 1 2
0 0 : 0 0 : 0 0 . 0 0 0
To clear all of the disturbance records, do the following:

• Press the END (= Y) key to clear all the disturbance records stored in back-up RAM.
4.2.3.4 Displaying Counter

 98 
6 F 2 T 0 1 7 9
• Select "Counter" to display the "Counter" screen.
/ 2 C o u n t e r
＞ V i e w c o u n t e r
C l e a r T r i p s 1
C l e a r T r i p s 1 A (*)
C l e a r T r i p s 1 B (*)
C l e a r T r i p s 1 C (*)
C l e a r T r i p s 2
C l e a r T r i p s 2 A (*)
C l e a r T r i p s 2 B (*)
C l e a r T r i p s 2 C (*)
(*) Note: These settings are only available when single phase External Trip BI functions
are used. In this case, the main "Clear Trips" option is not available.
• Select "View Counter" to display the counts stored in the relay.
/ 3 C o u n t e r
T r i p s 1 * * * * *
T r i p s 1 A * * * * * (*)
T r i p s 1 B * * * * * (*)
T r i p s 1 C * * * * * (*)
T r i p s 2 * * * * *
T r i p s 2 A * * * * * (*)
T r i p s 2 B * * * * * (*)
T r i p s 2 C * * * * * (*)
(*) Note: These settings are only available when single phase External Trip BI functions
are used. In this case, the main "Trips" option is not available.
To clear each count, do the following:
• Select "Clear Trips1" to display the following confirmation screen.
C l e a r T r i p s 1 ?
 99 
6 F 2 T 0 1 7 9
• Select "Clear Trips1 A" to display the following confirmation screen.
C l e a r T r i p s 1 A ?
• Select "Clear Trips1 B" to display the following confirmation screen.
C l e a r T r i p s 1 B ?
• Select "Clear Trips1 C" to display the following confirmation screen.
C l e a r T r i p s 1 C ?
Clear Trips2 provides the same display as Clear Trips1

• Select "Clear ARCs" to display the following confirmation screen.
C l e a r A R C s ?
• Press the END (= Y) key to clear the count stored in back-up RAM.
4.2.4 Displaying the Status

From the sub-menu of "Status", the following statuses can be displayed on the LCD:
Metering data of the protected transformer
Status of binary inputs and outputs
Status of measuring elements output
Status of time synchronisation source
Status of clock adjustment
Status of LCD contrast
The data are renewed every second.
 100 
6 F 2 T 0 1 7 9
4.2.4.1 Displaying Metering Data

To display metering data on the LCD, do the following:
• Select "Status" on the top "MAIN MENU" screen to display the "Status" screen.
/ 1 S t a t u s
＞ M e t e r i n g
B i n a r y I / O
R e l a y e l e m e n t
T i m e s y n c .
C l o c k a d j u s t .
L C D c o n t r a s t
• Select "Metering" to display the "Metering" screen.
/ 2 M e t e r i n g
＞ M e t e r i n g
D e m a n d
• Select " Metering " to display the current power system quantities on the "Metering" screen.
/ 3 M e t e r i n g
I a 1 * * * . * * k A
I b 1 * * * . * * k A
I c 1 * * * . * * k A
I a 2 * * * . * * k A
I b 2 * * * . * * k A
I c 2 * * * . * * k A
I 2 / I 1 1 * * * . * *
I 2 / I 1 2 * * * . * *
I 1 1 * * . * * * A
I 2 1 * * * . * * k A
I 0 1 * * * . * * k A
I 1 2 * * * . * * k A
I 2 2 * * * . * * k A
I 0 2 * * * . * * k A
I d a * * * . * * p u
I d b * * * . * * p u
 101 
6 F 2 T 0 1 7 9
I d c * * * . * * p u
I r a * * * . * * p u
I r b * * * . * * p u
I r c * * * . * * p u
I d o 1 * * * . * * p u
I d o 2 * * * . * * p u
I r o 1 * * * . * * p u
I r o 2 * * * . * * p u
V a * * * . * * k V Not available for model 100, 200, series*
T H M * * * . * %
P - * * * * * * k W Not available for model 100, 200, 300, 400 series
Q - * * * * * * k v a r Not available for model 100, 200, 300, 400 series
S - * * * * * * k V A Not available for model 100, 200, 300, 400 series
W h + * * * * * * k W Not available for model 100, 200, 300, 400 series
W h - * * * * * * k W Not available for model 100, 200, 300, 400 series
v a r h + * * * * * * k v a r Not available for model 100, 200, 300, 400 series
v a r h - * * * * * * k v a r Not available for model 100, 200, 300, 400 series
Note: I 1 for primary(high-voltage) winding current

I 2 for secondary(low-voltage) winding current
Ia , Ib , Ic for phase current
Ie for neutral current
I1 , I2 , I0 for symmetrical component current
Ida, Idb, Idc for differential current
Ido1, Ido2 for zero-phase differential current in 1REF, 2REF
Metering data is expressed as primary values or secondary values depending on the setting. For
setting, see Section 4.2.6.6.
Note: When changing the units (kA/A) of primary side current with RSM100, press the "Units"
button which is indicated in the primary side screen.
 102 
6 F 2 T 0 1 7 9
• Select "Demand" to display the current demand on the "Metering" screen.
/ 3 D e m e n d
I a 1 m a x * * . * * k A
I b 1 m a x * * . * * k A
I c 1 m a x * * . * * k A
I e 1 m a x * * . * * k A Not available for model 100, 300 series
I 2 1 m a x * * . * * k A
I 2 1 1 m a x * * . * *
I a 2 m a x * * . * * k A
I b 2 m a x * * . * * k A
I c 2 m a x * * . * * k A
I e 2 M a x * * . * * k A Not available for model 100, 300 series
I 2 2 M a x * * . * * k A
I 2 1 2 m a x * * . * *
P m a x * * * * * k W Not available for model 100 to 400 series
Q m a x * * * * * k v a r Not available for model 100 to 400 series
S m a x * * * * * k V A Not available for model 100 to 400 series
V a m a x * * * . * * k V Not available for model 100, 200 series*
V a m i n * * * . * * k V Not available for model 100 to 400 series
V b m a x * * * . * * k V Not available for model 100 to 400 series
V b m i n * * * . * * k V Not available for model 100 to 400 series
V c m a x * * * . * * k V Not available for model 100 to 400 series
V c m i n * * * . * * k V Not available for model 100 to 400 series
V e m a x * * * . * * k V Not available for model 100 to 400 series
V e m i n * * * . * * k V Not available for model 100 to 400 series
V o m a x * * * . * * k V Not available for model 100 to 400 series
V o m i n * * * . * * k V Not available for model 100 to 400 series
f m a x * * . * * H z Not available for model 100, 200 series
f m i n * * . * * H z Not available for model 100, 200 series
d f m a x * * . * * H z / s Not available for model 100, 200 series
d f m i n * * . * * H z / s Not available for model 100, 200 series

To clear all max data, do the following:
• Press the RESET key on any max demand screen (primary or secondary) to display the
following confirmation screen.
C l e a r m a x ?
 103 
6 F 2 T 0 1 7 9
• Press the END (= Y) key to clear all max data stored in back-up RAM.
4.2.4.2 Displaying the Status of Binary Inputs and Outputs
To display the binary input and output status, do the following:
• Select "Binary I/O" to display the binary input and output status.
For Models 100, 200, 300, 400 and 500:
/ 2 B i n a r y I / O
I P [ 0 0 0 0 0 0 ]
O P [ 0 0 0 0 ]
F A I L [ 0 ]
For Models 101, 201, 301, 401 and 501:
/ 2 B i n a r y I / O
I P [ 0 0 0 0 0 0 ]
I P 2 [ 0 0 0 0 0 0 ]
O P [ 0 0 0 0 ]
O P 2 [ 0 0 0 0 0 0 ]
F A I L [ 0 ]
For Models 102, 202, 302, 402 and 502:
/ 2 B i n a r y I / O
I P [ 0 0 0 0 0 0 ]
I P 2 [ 0 0 0 0 0 0 ]
I P 3 [ 0 0 0 0 0 0 ]
O P [ 0 0 0 0 ]
O P 2 [ 0 0 0 0 0 0 ]
O P 3 [ 0 0 0 0 0 0 ]
F A I L [ 0 ]
The display format is shown below.

[       ]
Input (IP) BI1 BI2 BI3 BI4 BI5 BI6
Input2(IP2) BI7 BI8 BI9 BI10 BI11 BI12
Input3(IP3) BI13 BI14 BI15 BI16 BI17 BI18
Output (OP) BO1 BO2 BO3 BO4
Output2(OP2) BO5 BO6 BO7 BO8 BO9 BO10
Output3(OP3) BO11 BO12 BO13 BO14 BO15 BO16
FAIL FAIL
 104 
6 F 2 T 0 1 7 9
The row IP shows the binary input status. BI1 to BI8 correspond to each binary input signal. In
models 100, 200, 300, 400 and 500 BI7 to BI18 are not available, BI13 to BI18 are not available for
models 101, 201, 301, 401 and 501. For binary input signals, see Appendix H. The status is
expressed with logical level "1" or "0" at the photo-coupler output circuit.
The row OP shows the binary output status. BO5 to BO16 are not available for models 100, 200,
300, 400 and 500. BO11 to BO16 are not available for models 101, 201, 301, 401 and 501.
The status of these outputs is expressed with logical level "1" or "0" at the input circuit of the output
relay driver. That is, the output relay is energised when the status is "1".
FAIL is a normally closed contact for detection of a relay fail condition.
4.2.4.3 Displaying the Status of Measuring Elements

To display the status of measuring elements on the LCD, do the following:
• Select 3 "Ry element" to display the status of the relay elements.
/ 2 R y e l e m e n t
D I F # 1 [ 0 0 0 0 0 0 ]
D I F # 2 [ 0 0 0 0 0 0 ]
R E F [ 0 0 0 0 0 0 ] Not available for model 100 and 300 series.
V / f [ 0 0 0 ] Not available for model 100 and 200 series.
O C V [ 0 0 0 0 0 0 ] Not available for model 100 and 200 series.
O C # 1 [ 0 0 0 0 0 0 ]
O C # 2 [ 0 0 0 0 0 0 ]
O C I # 1 [ 0 0 0 0 0 0 ]
O C I # 2 [ 0 0 0 0 0 0 ]
E F [ 0 0 0 0 ]
E F I [ 0 0 0 0 ]
N O C [ 0 0 0 0 ]
N O C I [ 0 0 0 0 0 ]
T H M [ 0 0 ]
C B F [ 0 0 0 0 0 0 ]
I C D [ 0 0 0 0 0 0 ]
O V [ 0 0 0 0 0 0 ] Not available for model 100 and 200 series.
U V [ 0 0 0 0 0 0 ] Not available for model 100 and 200 series.
F R Q [ 0 0 ] Not available for model 100 and 200 series.
D F R Q [ 0 0 ] Not available for model 100 and 200 series.
The display format is as shown below.
 105 
6 F 2 T 0 1 7 9
[        ]
DIF1 DIF-A DIF-B DIF-C 2f-A 2f-B 2f-C DEF elements
DIF2 5f-A 5f-B 5f-C HOC-A HOC-B HOC-C DEF elements
REF 1REF 2REF 1REFOC1 1REFOC2 2REFOC1 2REFOC2 REF elements
V/f V/f-A V/f-T V/f-H V/f elements
OCV 1OCV-A 1OCV-B 1OCV-C 2OCV-A 2OCV-B 2OCV-C 51V elements
OC1 1OC1-A 1OC1-B 1OC1-C 1OC2-A 1OC2-B 1OC2-C OC elements
OC2 2OC1-A 2OC1-B 2OC1-C 2OC2-A 2OC2-B 2OC2-C OC element
OCI1 1OCI1-A 1OCI1-B 1OCI1-C 1OCI2-A 1OCI2-B 1OCI2-C OC elements
OCI2 2OCI1-A 2OCI1-B 2OCI1-C 2OCI2-A 2OCI2-B 2OCI2-C OC element
EF 1EF1 1EF2 2EF1 2EF2 EF element
EFI 1EFI1 1EFI2 2EFI1 2EFI2 EFI element
NOC 1NC1 1NC2 2NC1 2NC2 NOC element
THM THM-A THM-T THM element
CBF 1CBF-A 1CBF-B 1CBF-C 2CBF-A 2CBF-B 2CBF-C CBF element
ICD 1ICD-A 1ICD-B 1ICD-C 2ICD-A 2ICD-B 2ICD-C ICD elements
OV OV1-A OV1-B OV1-C OV2-A OV2-B OV2-C OV elements
UV UV1-A UV1-B UV1-C UV2-A UV2-B UV2-C UV elements
FRQ FRQ1 FRQ2 FRQ elements
DFRQ DFRQ1 DFRQ2 DFRQ elements
The status of each element is expressed with logical level "1" or "0". Status "1" means the element is
in operation.
To display all the lines on the LCD, press the ▲ and ▼ keys.
4.2.4.4 Displaying the Status of the Time Synchronization Source

The internal clock of the GRE160 can be synchronised with external clocks such as the binary input
signal clock, Modbus or IEC60870-5-103. To display on the LCD whether these clocks are active
(=Act.) or inactive (=Inact.) and which clock the relay is synchronised with, do the following:
• Select "Time sync." to display the status of time synchronisation sources.
/ 2 T i m e s y n c .
B I : I n a c t .
* M o d b u s : A c t .
I R I G : I n a c t .
I E C : I n a c t .
The asterisk on the far left shows that the internal clock is synchronised with the marked source
clock. If the marked source clock is inactive, the internal clock runs locally.
Note: If the Binary input signal has not been detected for one hour or more after the last detection, the
status becomes "inactive".
For details of the setting time synchronisation, see Section 4.2.6.6.
 106 
6 F 2 T 0 1 7 9
4.2.4.5 Clock Adjustment
To adjust the clock when the internal clock is running locally, do the following:
• Select "Clock adjust." to display the setting screen.
/ 2 2 6 / A u g / 2 0 1 1
0 0 : 0 0 : 0 0 [ L ] L:Local, B;BI, M;MODBUS, R;IRIG-B, E;IEC60870-5-103
> M i n u t e
0 _
H o u r
0 _
D a y
2 6 _
M o n t h
8 _
Y e a r
2 0 1 9 _
Lines 1 and 2 show the current date and time. The time can be adjusted only when the clock is
running locally. When [B], [M], [R] or [E] is active, the adjustment is invalid.
• Enter a numerical value for each item and press the key. For details on how to enter a numerical
value, see 4.2.6.1.
• Press the END key to adjust the internal clock to the set hours without fractions and return to
the previous screen.
If a date which does not exist in the calendar is set and END is pressed, "**** Error ****" is
displayed on the top line and the adjustment is discarded. Return to the normal screen by pressing the
CANCEL key and adjust again.
4.2.4.6 LCD Contrast
To adjust the contrast of the LCD screen, do the following:

• Select "LCD contrast" to display the setting screen.
/ 2 L C D C o n t r a s t
■ ■ ■ ■
• Press the
▲
or key to adjust the contrast. The characters on the screen become thinner by
▲
pressing the key and thicker by pressing the key.
 107 
6 F 2 T 0 1 7 9
4.2.5 Viewing the Settings

The sub-menu "Set. (view)" is used to view the settings made using the sub-menu "Set. (change)".
The following items are displayed:
Relay version
Description
Relay address, IP address and baud rate in Modbus or IEC60870-5-103.
Record setting
Status setting
Protection setting
Binary input setting
Binary output setting
LED setting
Control setting
Frequency setting
Enter an item on the LCD to display each item as described in the previous sections.
4.2.5.1 Relay Version
To view the relay version, do the following.

• Press the "Set.(view)" on the main menu.
/ 1 S e t . ( v i e w )
> V e r s i o n
D e s c r i p t i o n
C o m m s
R e c o r d
S t a t u s
P r o t e c t i o n
B i n a r y I / P
B i n a r y O / P
L E D
C o n t r o l
F r e q u e n c y
• Press "Version" on the "Set.(view)" menu.
/ 2 V e r s i o n
> R e l a y t y p e
S o f t w a r e .
 108 
6 F 2 T 0 1 7 9
• Select "Relay type" to display the relay type form and model number. (ex.;GRE160-400A-10-10)
G R E 1 6 0 - 4 0 0 A - 1 0
- 1 0
• Select "Software" to display the relay software type form and version. (ex.;GS1***-**-*)
■ M a i n s o f t w a r e ↓
G S 1 * * * - * * - *
■ P L C d a t a
P G R E 1 6 0 A * * * *
( * * * * * * * * )
■ I E C 1 0 3 D a t a
I G R E 1 6 0 A * * * *
( * * * * * * * * )
4.2.5.2 Settings
The "Description", "Comms", "Record", "Status", "Protection", "Binary I/P", "Binary

O/P" ,"LED" , "Control" and "Frequency" screens display the current settings input using the "Set.
(change)" sub-menu.
4.2.6 Changing the Settings

The "Set. (change)" sub-menu is used to make or change settings for the following items:
Password
Description
Relay address, IP address and baud rate in RSM or IEC60870-5-103
Recording setting
Status setting
Protection setting
Binary input setting
Binary output setting
LED setting
Control setting
Frequency setting
All of the above settings except the password can be seen using the "Set. (view)" sub-menu.
CAUTION
Modification of settings : Care should be taken when modifying settings for "active group",
"scheme switch" and "protection element" in the "Protection" menu. Dependencies exist between the
settings in the various menus, with settings in one menu becoming active (or inactive) depending on
the selection made in another menu. Therefore, it is recommended that all necessary settings changes
be made while the circuit breaker tripping circuit is disconnected.
 109 
6 F 2 T 0 1 7 9
Alternatively, if it is necessary to make settings changes with the tripping circuit active, then it is
recommended to enter the new settings into a different settings group, and then change the "active
group" setting, thus ensuring that all new settings become valid simultaneously.
4.2.6.1 Setting Method

There are three setting methods as follows:
- To enter a selected item
- To enter a text string
- To enter numerical values
To enter a selected item

If a screen as shown below is displayed, setting can be performed setting as follows.
The cursor can be moved to upper or lower lines within the screen by pressing the ▲ and ▼ keys.
If setting (change) is not required, skip the line with the ▲ and ▼ keys.
/ 1 S e t . ( c h a n g e )
> P a s s w o r d
C o m m s
R e c o r d
S t a t u s
P r o t e c t i o n
B i n a r y I / P
B i n a r y O / P
L E D
C o n t r o l
F r e q u e n c y
• Move the cursor to a setting item.

• Press the ENTER key.
To enter a text string

Text strings are entered under the "Plant name" , "Description" or "Alarm text" screen.
/ 2 D e s c r i p t i o n
> P l a n t n a m e
A ｌ a r m 1 T e x t
To select a character, use keys ▼ , ▲ ,

▲
and to move the blinking cursor down, up, left and
 110 
6 F 2 T 0 1 7 9
right. "→" and "←" on the final line indicate a space and backspace, respectively. A maximum of 22
characters can be entered.
A B C D E F G H I J K L M N O P
Q R S T U V W X Y Z a b c d e f
g h i j K l m n o p q r s t u v
w x y z 0 1 2 3 4 5 6 7 8 9 ( )
[ ] @ _ { } * / + - < = > ! “ ♯
$ % & ‘ : ; , . ^ `  
• Set the cursor position in the grid square where you want the text to appear by selecting "→" or
"←" and pressing the ENTER key.
• Move the blinking cursor to a select the desired character.

• Press the ENTER key to enter the blinking character at the cursor position in the grid square.
• Press the END key to confirm the entry and return to the upper screen.
To correct the entered character, do either of the following:

• Discard the character by selecting "←" and pressing the ENTER key and enter the new
character.
• Discard the whole entry by pressing the CANCEL key and restart the entry from the first step.
To enter numerical values
When the screen shown below is displayed, setting can be performed setting as follows:
The number to the left of the cursor shows the current setting or default setting set at shipment. The
cursor can be moved to upper or lower lines within the screen by pressing the ▲ and ▼ keys. If a
setting (change) is not required, skip the line with the ▲ and ▼ keys.
/ 4 T i m e / S t a r t e r
T i m e 1 _ s
> T i m e 1 2 . 0 s
T i m e 2 2 . 0 s
1 O C P S 2 . 0 0 p u
2 O C P S 1 . 0 0 p u
1 O C P G 2 . 0 0 p u
2 O C P G 1 . 0 0 p u
O V 1 2 0 . 0 V Not available for model 100, 300 series.
U V 6 0 . 0 V Not available for model 100, 300 series.
• Move the cursor to a setting line.

• Press the
▲
or key to set a desired value. The value is can be raised or powered by pressing
 111 
6 F 2 T 0 1 7 9
▼
the or key.
• Press the ENTER key to enter the value.
• After completing the setting on the screen, press the END key to return to the upper screen.
The numerical value entered can be modified as follows:
• If the need to change the numerical value is decided before pressing the ENTER key, press the
CANCEL key and enter the new numerical value.
• If it is after pressing the ENTER key, move the cursor to the correct line by pressing the ▲
and ▼ keys and enter the new numerical value.
Note: If the CANCEL key is pressed after any entry is confirmed by pressing the ENTER key, all
the entries made so far on the screen concerned are canceled and the screen will return to the
upper level.
To complete the setting

Enter the settings after making entries on each setting screen by pressing the ENTER key, the new
settings are not yet used for operation, though stored in the memory. To validate the new settings,
take the following steps.
• Press the END key to return to the upper screen. Repeat this until the confirmation screen
shown below is displayed. The confirmation screen is displayed just before returning to the "Set.
(change)" sub-menu.
C h a n g e s e t t i n g s ?
E N T E R = Y C A N C E L = N
• When the screen is displayed, press the ENTER key to start operation using the new settings,
or press the CANCEL key to correct or cancel entries. In the latter case, the screen returns to
the setting screen to enable re-entries. Press the CANCEL key to cancel entries made so far
and to turn to the "Set. (change)" sub-menu.
4.2.6.2 Password
For the sake of security of Setting changes password protection can be set as follows:
• Select "Set. (change)" on the " MAIN MENU " screen to display the "Setting change" screen.
• Select "Password" to display the "Password" screen.
• Enter a 4-digit number within the grid square after "Input" and press the ENTER key.
S e t . ( c h a n g e )
I n p u t [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜
 112 
6 F 2 T 0 1 7 9
• For confirmation, enter the same 4-digit number in the grid square after "Retype".
S e t . ( c h a n g e )
R e t y p e [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜
• Press the END key to display the confirmation screen. If the retyped number is different from
that first entered, the following message is displayed on the bottom of the "Password" screen
before returning to the upper screen.
"Unmatch passwd!"
Re-entry is then requested.
Password trap
After the password has been set, the password must be entered in order to enter the setting change
screens.
If "Set. (change)" or "Test" is entered on the top "MAIN MENU" screen, the password trap screen
"Password" is displayed. If the password is not entered correctly, it is not possible to move to the
"Setting (change)" or "Test" sub-menu screens.
S e t . ( c h a n g e )
P a s s w o r d [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜
Canceling or changing the password
To cancel the password protection, enter "0000" in the two grid square on the "Password" screen.
The "Set. (change)" screen is then displayed without having to enter a password.
The password can be changed by entering a new 4-digit number on the "Password" screen in the
same way as the first password setting.
If you forget the password
Press the CANCEL and RESET keys together for one second on the top "MAIN MENU"
screen. The screen goes off, and the password protection of the GRE160 is canceled. Set the
password again.
4.2.6.3 Description
To enter the plant name and other data, do the following. These data are attached to records.
• Select "Set. (change)" on the " MAIN MENU " screen to display the " Set. (change)" screen.
• Select "Description" to display the "Description" screen.
 113 
6 F 2 T 0 1 7 9
/ 2 D e s c r i p t i o n
> P l a n t n a m e
A l a r m 1 T e x t
A l a r m 2 T e x t
A l a r m 3 T e x t
A l a r m 4 T e x t
• To enter the plant name, select "Plant name" on the "Description" screen.
• To enter special items, select "Description" on the "Description" screen.
• To enter special items, select "Alarm1 Text" to "Alarm4 Text" on the "Description" screen.
4.2.6.4 Communication
If the relay is linked with Modbus, IEC60870-5-103 communication or Ethernet LAN (optional) an
address must be set. Do this as follows:
• Select "Set. (change)" on the "MAIN MENU" screen to display the "Set. (change)" screen.
• Select "Comms" to display the "Comms" screen.
/ 2 C o m m s
＞ A d d r .
S w i t c h
• Select "Addr./Param." on the "Comms" screen to enter the relay address number.
/ 3 A d d r .
M o d b u s _
> M o d b u s 2
I E C 0
• Press the ENTER key.
CAUTION: Do not duplicate the relay address number.

• Select "Switch" on the "Comms" screen to select the protocol and transmission speed (baud
rate), etc., of theModbus ,IEC60870-5-103.
 114 
6 F 2 T 0 1 7 9
/ 3 S w i t c h
R S 4 8 5 B R _
> R S 4 8 5 B R 0
9 . 6 / 1 9 . 2
I E C B L K
N o r m a l / B l o c k e d
• Select the number and press the ENTER key.
<RS485BR>
This line is to select the baud rate for RS485 communication.
<IECBLK>
Select 2 (=Blocked) to block transmission from relay to BCU for IEC60870-5-103 communication.
When using the IEC60870-5-103 communication, select 1 (=Normal).
4.2.6.5 Setting the Recording

To set the recording function as described in Section 4.2.3, do the following:
• Select "Set. (change)" on the "MAIN MENU" screen to display the "Set. (change)" screen.
• Select "Record" to display the "Record " screen.
/ 2 R e c o r d
> F a u l t
D i s t u r b a n c e
C o u n t e r
Setting the disturbance recording

/ 3 F a u l t
P h a s e m o d e
> P h a s e m o d e
O p e r a t i n g / F a u l t
<Phase mode>
To set the display phase (operating phase or fault phase) for Fault record screen, do the following.
• Enter 0(=Operating) or 1(=Fault) by pressing the
▲
or key and press the ENTER key.
 115 
6 F 2 T 0 1 7 9
Setting the disturbance recording

> T i m e / S t a r t e r
S c h e m e s w
• Select "Time/starter" to display the "Time/starter" screen.
/ 4 T i m e / S t a r t e r
T i m e 1 _ s
> T i m e 1 2 . 0 s
T i m e 2 2 . 0 s
1 O C P S 2 . 0 0 p u
2 O C P S 0 . 5 0 p u
1 O C P G 2 . 0 0 p u
2 O C P G 0 . 5 0 p u
O V 1 2 0 . 0 V Not available for model 100, 200 series.
U V 6 0 . 0 V Not available for model 100, 200 series.
• Enter the recording time and starter element settings.

To set whether or not a function is to be used as a starter, do the following:
• Select "Scheme sw" on the "Disturbance" screen to display the "Scheme sw" screen.
/ 4 S c h e m e s w
T r i p _
> T r i p 1 1
O f f / O n
T r i p 2 1
O f f / O n
1 O C P S 1
O f f / O n
2 O C P S 1
O f f / O n
1 O C P G 1
O f f / O n
2 O C P G 1
O f f / O n
2 F 1
O f f / O n
 116 
6 F 2 T 0 1 7 9
5 F 1
O f f / O n
E V E N T 1 1
O f f / O n
E V E N T 2 1
O f f / O n
E V E N T 3 1
O f f / O n
O V 1
Not available for model 100, 200 series.
O f f / O n
U V 1
Not available for model 100, 200 series.
O f f / O n
• Enter 1 to use as a starter. If not to be used as a starter, enter 0.
Setting the counter

/ 3 C o u n t e r
> S c h e m e s w
A l a r m s e t
To set whether or not a counter is to be used, do the following:

• Select "Scheme sw" on the "Counter" screen to display the "Scheme sw" screen.
/ 4 S c h e m e s w
T C 1 S P E N _
> T C 1 S P E N 1
O f f / O n / O p t - O n
T C 2 S P E N 1
C B 1 S M E N 1
O f f / O n
C B 2 S M E N 1
O f f / O n
T C 1 A E N 1
O f f / O n
T C 2 A E N 1
O f f / O n
O P T 1 A E N 1
O f f / O n
O P T 2 A E N 1
 117 
6 F 2 T 0 1 7 9
O f f / O n
• Enter 1 to use as a counter. If not to be used as a counter, enter 0.

To set the threshold setting, do the following:
• Select "Alarm set" on the "Counter" screen to display the "Alarm set" screen.
/ 4 A l a r m s e t
T C A L M _
> T C 1 A L M 1 0 0 0 0
T C 2 A L M 1 0 0 0 0
O P T 1 A L M 5 0 0 0 m s
O P T 2 A L M 5 0 0 0 m s
• Enter the threshold settings.
4.2.6.6 Status
To set the status display described in Section 4.2.4, do the following:

Select "Status" on the "Set. (change)" sub-menu to display the "Status" screen.
/ 2 S t a t u s
> M e t e r i n g
T i m e s y n c .
Setting the metering

• Select "Metering" to display the "Metering" screen.
/ 3 M e t e r i n g
D i s p l a y _
> D i s p l a y 0
P r i / S e c / P r i - A
P o w e r 0 Available for model 500 series.
S e n d / R e c e i v e
C u r r e n t 1 Available for model 500 series.
L a g / L e a d
• Enter 0 or 1 or 2 for Display.

Enter 0(=Pri) to display the primary side current in kilo-amperes(kA).
Enter 1(=Sec) to display the secondary side current.
Enter 2(=Pri-A) to display the primary side current in amperes(A).
 118 
6 F 2 T 0 1 7 9
• Enter 0(=Send) or 1(=Receive) for Power, and 0(=Lag) or 1(=Lead) for Current, and press the
ENTER key.
Note: Power and Current setting (at model 500 model series )
Active Power Display
Power setting=0 (Send) Power setting=1 (Receive)
－＋＋－
V V
I I
－＋＋－
Reactive Power Display
Current setting=0 (Lag) Current setting=1 (Lead)
＋＋－－
V V
I I
－－＋＋
Setting the time synchronisation

The calendar clock can run locally or be synchronised with the binary input signal, RSM clock, or
by using IEC60870-5-103. This is selected by setting as follows.
• Select "Time sync" to display the "Time sync" screen.
/ 3 T i m e s y n c .
T i m e s y n c . _
> T i m e s y n c . 1
O f f / B I / M o d b u s / I
R I G / I E C 1 0 3
• Enter 0, 1, 2 or 3 and press the ENTER key.

Enter 0(=off) not to be synchronised with any external signals.
Enter 1(=BI) to be synchronised with the binary input signal.
Enter 2(=Modbus) to be synchronised with Modbus.
Enter 3(=IRIG) to be synchronised with IRIG-B time signal.
Enter 4(=IEC103) to be synchronised with IEC60870-5-103.
Note: When selecting BI, Modbus, IRIG-B or IEC60870-5-103, check that they are active on the
"Status" screen in "Status" sub-menu.
If BI is selected, the BI command trigger setting should be “None” otherwise the repetitive
operation of the BI selected will quickly fill the event records (See Section 4.2.6.5.)
If it is set to inactive BI, Modbus, IRIG-B or IEC60870-5-103, the calendar clock runs locally.
 119 
6 F 2 T 0 1 7 9
4.2.6.7 Protection
The GRE160 can have 2 setting groups for protection in order to accommodate changes in the
operation of the power system, one setting group is assigned active. To set the protection, do the
following:
• Select "Protection" on the "Set. (change)" screen to display the "Protection" screen.
/ 2 P r o t e c t i o n
> C h a n g e a c t . g p .
C h a n g e s e t
C o p y g p .
Changing the active group

• Select "Change act. gp." to display the "Change act. gp." screen.
/ 3 C h a n g e a c t .
g p .
A c t i v e g p . _
> A c t i v e g p . 1
• Enter the group number and press the ENTER key.
Changing the settings

Almost all the setting items have default values that are set when the product is shipped. For the
default values, see Appendix H. To change the settings, do the following:
• Select "Change set." to display the "Act gp.= *" screen.
/ 3 A c t g p . = 1
> C o m m o n
G r o u p 1
G r o u p 2
Changing the Common settings

• Select "Common" to set the current and voltage input state and input imbalance monitoring and
press the ENTER key.
 120 
6 F 2 T 0 1 7 9
/ 4 C o m m o n
A P P L C T _
> A P P L C T 1
O f f / O n
A P P L V T 1 Available for model 300, 400, 500 series
O f f / 1 P P / 3 P N
A P P L V E 1 Available for model 500 model series
O f f / O n
C T 1 0
1 A / 5 A
C T 2 1
1 A / 5 A
C T 1 P O L 0
O b j e c t / O u t s i d e
C T 2 P O L 0
O b j e c t / O u t s i d e
C T n 1 0 Not available for model 100, 300 series
1 A / 5 A
C T n 2 0 Not available for model 100, 300 series
1 A / 5 A
V T L O C 2 Not available for model 100, 200 series
O f f / A L M & B L K / A L M
C T 1 S V E N 1
C T 2 S V E N 1
V 0 S V E N 1 Available for model 500 series
V 2 S V E N 1 Available for model 500 series
O F f / O n / O p t - O n
A 0 L E D 1
O f f / O n
<APPLCT>
• Enter 0(=Off: not used) or 1(=On: used) to set the current input state and press the ENTER
key.
<APPLVT>
• Enter 0(=Off: not used) or 1(=On: used) to set the voltage input state and press the ENTER
key.
 121 
6 F 2 T 0 1 7 9
<APPLVE>
• Enter 0(=Off: not used) or 1(=On: used) to set the zero phase voltage input state and press the
ENTER key.
<CT1, CT2>
To set CT secondary rated current, do the following.
• CT secondary rated current setting. Enter 0(=1A), 1(=5A) and press the ENTER key.
CT1 is the primary side of transformer, CT2 is the secondary side of transformer.
<CT1POL, CT2POL>
To set CT secondary wiring , do the following.
• CT secondary wiring setting. Enter 0(=Object), 1(=Outside) and press the ENTER key.
Refor to section 2.2.4.
<CTn1, CTn2>
To set zero-phase CT secondary rated current, do the following.
• Zero-phase CT secondary rated current setting. Enter 0(=1A), 1(=5A) and press the ENTER
key.
CTn1 is the primary side of transformer, CTn2 is the secondary side of transformer.
<VTLOC>
To set VT location at main circuit (primary side or secondary side), do the following.
• VT location setting. Enter 0(=pri), 1(=sec) and press the ENTER key.
< CT1SVEN, CT2SVEN, V0SVEN, V2SVEN>

To set AC input imbalance supervision enable, do the following.
• Enter 0(=Off) or 1(=ALM&BLK) or 2(=ALM) by pressing the
▲
or key and press the

ENTER key.
<AOLED>
This switch is used to control the “TRIP” LED lighting when an alarm element outputs.
• Enter 1 (=On) to light the “TRIP” LED when an alarm element outputs, and press the ENTER
key. If not, enter 0 (=Off) and press the ENTER key.
Changing the Group settings

• Select the "Group∗" on the "Act gp.= *" screen to change the settings and press the ENTER
key.
/ 4 G r o u p ＊
> P a r a m e t e r
T r i p
 122 
6 F 2 T 0 1 7 9
Setting the parameter

Enter the line name, the CT/VT ratio and the fault locator as follows:
• Select "Parameter" on the "Group ∗" screen to display the "Parameter" screen.
/ 5 P a r a m e t e r
> L i n e n a m e
C T / V T r a t i o
• Select "Line name" to display the "Line name" screen.

• Enter the line name as a text string and press the END key.
• Select "CT/VT ratio" to display the "CT/VT ratio" screen.
/ 6 C T / V T r a t i o
O C C T _
> 1 C T 4 0 0
2 C T 4 0 0
1 n C T 4 0 0 Not available for model 100, 300 series
2 n C T 1 0 0 Not available for model 100, 300 series
P V T 1 0 0 Not available for model 100, 200 series
V E V T 1 0 0 Available for model 500 series.
Note: The "CT/VT ratio" screen depends on the APPLCT and APPLVT setting.
• Enter the CT/VT ratio and press the ENTER key.

<1CT, 2CT, 1nCT, 2nCT>
1CT, 2CT, 1nCT, 2nCT are set the CT primary rated current. CT secondary rated current settings
are at CT1, CT2, CTn1 and CTn2.
<PVT, VEVT>
PVT and VEVT are setting the VT ratio of Phase VT and zero-phase VT.
CAUTION
Do not set the VT primary rated voltage. Set the VT ratio.
(VT ratio) = (VT primary rated voltage [V]) / (Relay rated voltage [V])
Setting the trip function

To set the scheme switches and protection elements, do the following.
• Select "Trip" on the "Group ∗" screen to display the "Trip" screen.
/ 5 T r i p
> S c h e m e s w
P r o t . e l e m e n t
 123 
6 F 2 T 0 1 7 9
Setting the scheme switch

• Select "Scheme sw" on the "Trip" screen to display the "Scheme sw" screen.
/ 6 S c h e m e s w
> A p p l i c a t i o n
D I F p r o t
R E F p r o t Not available for model 100, 300 series
V / f p r o t . Not available for model 100, 200 series
O C p r o t . .
E F p r o t .
N O C p r o t .
M i s c . p r o t .
O V p r o t . Not available for model 100, 200 series
U V p r o t . Not available for model 100, 200 series
F R Q p r o t . Not available for model 100, 200 series
M . T r i p
Setting the application

To set the application setting, do the following.
• Select "Application" on the " Scheme sw" screen to display the "Application" screen.
/ 7 A p p l i c a t i o n
M 1 O C 1 _
> M 1 O C 1 0
I E C / I E E E / U S / C
M 1 O C 2 0
M 2 O C 1 0
M 2 O C 2 0
M 1 E F 1 0
M 1 E F 2 0
M 2 E F 1 0
M 2 E F 2 0
M 1 N C 1 0
 124 
6 F 2 T 0 1 7 9
M 1 N C 2 0
M 2 N C 1 0
M 2 N C 2 0
M 1 O C V 0
M 2 O C V 0
<M∗OC∗>, <M∗EF∗>, <M∗NC∗>, <M∗OCV>

To set the 1OC1, 1OC2, 2OC1, 2OC2, 1EF1, 1EF2, 2EF1, 2EF2, 1NOC1, 1NOC2, 2NOC1,
2NOC2, 1OCV and 2OCV time delay characteristic type, do the following.
• Enter 0(=IEC) or 1(=IEEE) or 2(=US) or 3(=C: CON) and press the ENTER key.
Setting the DIF protection

The settings for the DIF protection are as follows:
• Select "DIF Prot." on the "Scheme sw" screen to display the "DIF prot." screen.
/ 7 D I F p r o t .
D I F E N _
> D I F E N 0
O f f / O n
H O C E N 0
O f f / O n
D I F E N 1 0
O f f / O N
D I F E N 2 0
O f f / O N
D I F T P M D 0
3 P O R / 2 P A N D / 1 P
2 f - l o c k 0
O f f / O N
5 f - l o c k 0
O f f / O n
<DIFEN>
• Enter 1(=On) to enable the DIF and press the ENTER key. If disabling the DIF, enter 0(=Off)
and press the ENTER key.
 125 
6 F 2 T 0 1 7 9
<HOCEN>
To set the HOC element, do the following.
• Enter 0(=Off) or 1(=On) and press the ENTER key.
<DIF1EN, DIF2EN>
To set the CB1 and CB2 operating by DIF function respectively, do the following.
<DIFTPMD>
To set the trip mode, do the following.
• Enter 0(=3POR) or 1(=2PAND) or 2(=1P) and press the ENTER key. If the “2PAND”
selected, the trip signal is not issued when only one phase element operates.
<2f-lock>, <5f-lock>
To set the 2f-lock and 5f-lock Characteristic, do the following.
• After setting, press the END key to display the following confirmation screen.
• Press the ENTER (=Y) key to change settings and return to the "Scheme sw" screen.
Setting the REF protection

The REF protection is not available fpr model 100, 300 series.
The settings for the REF protection are as follows:
• Select "REF Prot." on the "Scheme sw" screen to display the "REF prot." screen.
/ 7 R E F p r o t .
1 R E F S C H E M E _
> 1 R E F S C H E M E 0
L o w / H i g h
2 R E F S C H E M E 0
L o w / H i g h
1 R E F 1 E N 0
O f f / O n
1 R E F 2 E N 0
O f f / O n
2 R E F 1 E N 0
 126 
6 F 2 T 0 1 7 9
O f f / O N
2 R E F 2 E N 0
O f f / O N
R E F D E F 0
O f f / O N
1 R E F O C 1 0
O f f / O N
1 R E F O C 2 0
O f f / O n
2 R E F O C 1
O f f / O n
2 R E F O C 2
O f f / O n
<1REFSCHEME, 2REFSCHEME>
To set the REFSCHEME mode, do the following.
• Enter 0(=Low) or 1(=High) and press the ENTER key.
<1REF1EN, 1REF2EN, 2REF1EN, 2REF2EN>

• Enter 1(=On) to enable the REF and press the ENTER key. If disabling the REF, enter 0(=Off)
<REFDEF>
• Enter 1(=On) to enable the REF_DEF function and press the ENTER key. If disabling the
REF_DEF function, enter 0(=Off) and press the ENTER key.
<1REFOC1, 1REFOC2, 2REFOC1, 2REFOC2>

• Enter 1(=On) to enable the REFOC and press the ENTER key. If disabling the REFOC, enter
0(=Off) and press the ENTER key.
Setting the Overexcitation protection

The Overexcitation protection is not available for model 100, 300 series.
The settings for the Overexcitation protection are as follows:
 127 
6 F 2 T 0 1 7 9
• Select "V/f Prot." on the "Scheme sw" screen to display the "V/f prot." screen.
/ 7 V / f p r o t .
V / F E N 1 _
> V / F E N 1 0
O f f / O n
V / F E N 2 0
O f f / O n
V / F A 0
O f f / O N
<V/FEN1, V/FEN2>
• Enter 1(=On) to enable the V/f and press the ENTER key. If disabling the V/f, enter 0(=Off)
<V/FA>
• Enter 1(=On) to enable the V/f alarm block and press the ENTER key. If disabling the V/f
alarm block, enter 0(=Off) and press the ENTER key.
Setting the OC protection

The settings for the OC protection are as follows:
• Select "OC Prot." on the "Scheme sw" screen to display the "OC prot." screen.
/ 7 O C P r o t .
1 O C 1 E N _
> 1 O C 1 E N 1
O f f / O n
1 O C I 1 E N 0
O f f / O n
M 1 O C 1 C - I E C 0
This setting is displayed if [M1OC1] is 1(=IEC).
N I / V I / E I / L T I
M 1 O C 1 C - I E E E 0
This setting is displayed if [M1OC1] is 2(=IEEE).
M I / V I / E I
M 1 O C 1 C - U S 0
This setting is displayed if [M1OC1] is 3(=US).
C O 2 / C O 8
 128 
6 F 2 T 0 1 7 9
1 O C 1 R 0 This setting is displayed if [M1OC1] is 2(=IEEE) or

D E F / D E P 3(=US).
1 O C 1 - 2 F 0
N A / B l o c k
1 O C 2 E N 1
Same as 1OC1 element
1 O C T P 1
3 P O R / 2 O U T O F 2
2 O C 1 E N 1
2 O C 2 E N 1
2 O C T P 1
3 P O R / 2 O U T O F 2
<∗OC∗EN>
• Enter 1(=On) to enable the ∗OC∗ and press the ENTER key. If disabling the ∗OC∗, enter
<∗OCI∗EN>
• Enter 1(=On) to enable the ∗OCI∗ and press the ENTER key. If disabling the ∗OCI∗, enter
<M∗OC∗C>
To set the ∗OCI∗ Inverse Curve Type, do the following.
• If [M∗OC∗] is 1(=IEC), enter 0(=NI) or 1(=VI) or 2(=EI) or 3(=LTI) and press the ENTER
key.
• If [M∗OC∗] is 2(=IEEE), enter 0(=MI) or 1(=VI) or 2(=EI) and press the ENTER key.
• If [M∗OC∗] is 3(=US), enter 0(=CO2) or 1(=CO8) and press the ENTER key.
<∗OC∗R>
To set the Reset Characteristic, do the following.
• If [M∗OC∗] is 2(=IEEE) or 3(=US), enter 0(=DEF) or 1(=DEP) and press the ENTER key.
<∗OC∗-2F>
• Enter 1(=Block) to block the ∗OC∗ and ∗OCI∗ against the inrush current, and press the
ENTER key.
<∗OCTP>
 129 
6 F 2 T 0 1 7 9
• Enter 0(=3POR) or 1(=2OUTOF3) and press the ENTER key. If the “2OUTOF3” selected,
the trip signal is not issued when only one phase element operates.
Setting the EF protection

The settings for the EF protection are as follows:
• Select the "EF prot." on the "Scheme sw" screen to display the "EF prot." screen.
• Select "OC Prot." on the "Scheme sw" screen to display the "OC prot." screen.
/ 7 E F P r o t .
1 E F 1 E N _
> 1 E F 1 E N 1
O f f / O n
1 E F I 1 E N 0
O f f / O n
M 1 E F 1 C - I E C 0
This setting is displayed if [M1EF1] is 1(=IEC).
N I / V I / E I / L T I
M 1 E F 1 C - I E E E 0
This setting is displayed if [M1EF1] is 2(=IEEE).
M I / V I / E I
M 1 E F 1 C - U S 0
This setting is displayed if [M1EF1] is 3(=US).
C O 2 / C O 8
1 E F 1 R 0 This setting is displayed if [M1EF1] is 2(=IEEE) or

D E F / D E P 3(=US).
1 E F 1 - 2 F 0
N A / B l o c k
1 E F 2 E N 1
Same as 1EF1 element
2 E F 1 E N 1
2 E F 2 E N 1
 130 
6 F 2 T 0 1 7 9
<∗EF∗EN>
• Enter 1(=On) to enable the ∗EF∗ and press the ENTER key. If disabling the ∗EF∗, enter
<∗EFI∗EN>
• Enter 1(=On) to enable the ∗EFI∗ and press the ENTER key. If disabling the ∗EFI∗, enter
<M∗EF∗C>
To set the ∗EFI∗ Inverse Curve Type, do the following.
• If [M∗EF∗] is 1(=IEC), enter 0(=NI) or 1(=VI) or 2(=EI) or 3(=LTI) and press the ENTER
key.
• If [M∗EF∗] is 2(=IEEE), enter 0(=MI) or 1(=VI) or 2(=EI) and press the ENTER key.
• If [M∗EF∗] is 3(=US), enter 0(=CO2) or 1(=CO8) and press the ENTER key.
<∗EF∗R>
• If [M∗EF∗] is 2(=IEEE) or 3(=US), enter 0(=DEF) or 1(=DEP) and press the ENTER key.
<∗EF∗-2F>
• Enter 1(=Block) to block the ∗EF∗ and ∗EFI∗ against the inrush current, and press the
ENTER key.
Setting the NOC protection

The settings for the NOC protection are as follows:
• Select the "NOC prot." on the "Scheme sw" screen to display the "NOC prot." screen.
/ 7 N O C P r o t .
1 N C 1 E N _
> 1 N C 1 E N 1
O f f / O n
1 N C I 1 E N 0
O f f / O n
 131 
6 F 2 T 0 1 7 9
M 1 N C 1 C - I E C 0
This setting is displayed if [M1NC1] is 1(=IEC).
N I / V I / E I / L T I
M 1 N C 1 C - I E E E 0
This setting is displayed if [M1NC1] is 2(=IEEE).
M I / V I / E I
M 1 N C 1 C - U S 0
This setting is displayed if [M1NC1] is 3(=US).
C O 2 / C O 8
1 N C 1 R 0 This setting is displayed if [M1NC1] is 2(=IEEE) or

D E F / D E P 3(=US).
1 N C 1 - 2 F 0
N A / B l o c k
1 N C 2 E N 1
Same as 1NC1 element
2 N C 1 E N 1
2 N C 2 E N 1
<∗NC∗EN>
• Enter 1(=On) to enable the ∗NC∗ and press the ENTER key. If disabling the ∗NC∗, enter
<∗NCI∗EN>
• Enter 1(=On) to enable the ∗NCI∗ and press the ENTER key. If disabling the ∗NCI∗, enter
<M∗NC∗C>
To set the ∗NCI∗ Inverse Curve Type, do the following.
• If [M∗NC∗] is 1(=IEC), enter 0(=NI) or 1(=VI) or 2(=EI) or 3(=LTI) and press the ENTER
key.
• If [M∗NC∗] is 2(=IEEE), enter 0(=MI) or 1(=VI) or 2(=EI) and press the ENTER key.
• If [M∗NC∗] is 3(=US), enter 0(=CO2) or 1(=CO8) and press the ENTER key.
<∗NC∗R>
• If [M∗NC∗] is 2(=IEEE) or 3(=US), enter 0(=DEF) or 1(=DEP) and press the ENTER key.
<∗NC∗-2F>
• Enter 1(=Block) to block the ∗NC∗ and ∗NCI∗ against the inrush current, and press the
ENTER key.
 132 
6 F 2 T 0 1 7 9
Setting the Misc. protection

The settings for the miscellaneous protection are as follows:
• Select the "Misc. prot." on the "Scheme sw" screen to display the "Misc. prot." screen.
/ 7 M i s c P r o t .
O C V E N _
> O C V 3 P H 0 OCV function is not available for model 100 and 200
1 P P / 3 P H series.
O C V C O N T 0
O N E / B O T H
O C V R E P H 0 This setting is not displayed at model 500 series.

A B / B C / C A
1 O C V E N 0
O f f / O n
M 1 O C V C - I E C 0
This setting is displayed if [M1OCV] is 1(=IEC).
N I / V I / E I / L T I
M 1 O C V C - I E E E 0
This setting is displayed if [M1OCV is 2(=IEEE).
M I / V I / E I
M 1 O C V C - U S 0
This setting is displayed if [M1OCV] is 3(=US).
C O 2 / C O 8
M 1 O C V R 0 This setting is displayed if [M1OCV] is 2(=IEEE) or

D E F / D E P 3(=US).
1 O C V - 2 F 0
N A / B l o c k
1 O C V T P 0
3 P O R / 2 O U T O F 3
2 O C V E N 0
O f f / O n
M 2 O C V C - I E C 0 This setting is displayed if [M2OCV] is 1(=IEC).

N I / V I / E I / L T I
M 2 O C V C - I E E E 0 This setting is displayed if [M2OCV is 2(=IEEE).

M I / V I / E I
M 2 O C V C - U S 0 This setting is displayed if [M2OCV] is 3(=US).
 133 
6 F 2 T 0 1 7 9
C O 2 / C O 8
M 2 O C V R 0 This setting is displayed if [M2OCV] is 2(=IEEE) or

D E F / D E P 3(=US).
2 O C V - 2 F 0
N A / B l o c k
2 O C V T P 0
3 P O R / 2 O U T O F 3
T H M E N 0
O f f / O n
T H M A E N 0
O f f / O n
B T C 1 0
O f f / O n
B T C 2 0
O f f / O n
R T C 1 0
O f f / D I R / O C
R T C 2 0
O f f / D I R / O C
<OCV3PH>
To set the voltage input mode of OCV element, do the following.
• Enter 0(=1PP) or 1(=3PH) and press the ENTER key.
<OCVCONT>
To set the OCV element operating, do the following.
• Enter 0(=ONE; VT mounting side only) or 1(=BOTH; Both side) and press the ENTER key.
<1OCVEN, 2OCVEN>
To set the operation mode for OCV element, do the following.
• Enter 1(=Cont), or 2(=Rest) and press the ENTER key.
<M1OCVC, M2OCVC >

To set the OCV Inverse Curve type, do the following.
• If [M∗OCV] is 1(=IEC), enter 0(=NI) or 1(=VI) or 2(=EI) or 3(=LTI) and press the ENTER
key.
• If [M∗OCV] is 2(=IEEE), enter 0(=MI) or 1(=VI) or 2(=EI) and press the ENTER key.
• If [M∗OCV] is 3(=US), enter 0(=CO2) or 1(=CO8) and press the ENTER key.
 134 
6 F 2 T 0 1 7 9
<M1OCVR, M2OCVR>
• If [M∗OCV] is 2(=IEEE) or 3(=US), enter 0(=DEF) or 1(=DEP) and press the ENTER key.
<1OCV-2F, 2OCV-2F>
• Enter 1(=Block) to block the OCV against the inrush current, and press the ENTER key.
<1OCVTP, 2OCVTP>
• Enter 0(=3POR) or 1(=2OUTOF3) and press the ENTER key. If the “2OUTOF3” selected,
the trip signal is not issued when only one phase element operates.
<THMEN>
• Enter 1(=On) to enable the Thermal OL and press the ENTER key. If disabling the Thermal
OL, enter 0(=Off) and press the ENTER key.
<THMAEN>
• Enter 1(=On) to enable the Thermal Alarm and press the ENTER key. If disabling the Thermal
Alarm, enter 0(=Off) and press the ENTER key.
<BTC∗>
• Enter 1(=On) to set the Back-trip control and press the ENTER key. If not setting the
Back-trip control, enter 0(=Off) and press the ENTER key.
<RTC∗>
To set the Re-trip control, do the following.
• Enter 0(=Off) or 1(=Direct) or 2(=OC controlled) and press the ENTER key.
Setting the OV protection

The OV protection is not available for model 100, 300 series.
The settings for the OV protection are as follows:
• Select "OV" on the "Scheme sw" screen to display the "OV" screen.
 135 
6 F 2 T 0 1 7 9
/ 7 O V p r o t .
O V 1 E N _
> O V 1 E N 0
O f f / D T / I D M T / C
O V 2 E N 0
O f f / O n
<OV1EN>
To set the OV1 delay type, do the following.
• Enter 1 (=DT) or 2 (=IDMT) or 3 (=C: configurable curve) and press the ENTER key. If
disabling the OV1, enter 0 (=Off) and press the ENTER key.
<OV2EN>
• Enter 1 (=On) to enable the OV2, and press the ENTER key. If disabling the OV2, enter 0
(=Off) and press the ENTER key.
• Press the ENTER (= Y) key to change settings and return to the "Scheme sw" screen.
Setting the UV protection

The UV protection is not available fpr model 100, 300 series.
The settings for the UV protection are as follows:
• Select "UV" on the "Scheme sw" screen to display the "UV" screen.
/ 7 U V p r o t .
U V 1 E N _
> U V 1 E N 0
O f f / D T / I D M T / C
U V 2 E N 0
O F f / O n
V B L K E N 0
O f f / O n
<UV1EN>
To set the UV1 delay type, do the following.
• Enter 1 (=DT) or 2 (=IDMT) or 3 (=C: configurable curve) and press the ENTER key. If
 136 
6 F 2 T 0 1 7 9
disabling the UV1 or UV2, enter 0 (=Off) and press the ENTER key.
<UV2EN>
• Enter 1 (=On) to enable the UV2, and press the ENTER key. If disabling the UV2, enter 0
(=Off) and press the ENTER key.
<VBLKEN>
• Enter 1 (=On) to enable the UV blocking and press the ENTER key. If disabling the UV
blocking, enter 0 (=Off) and press the ENTER key.
Setting the FRQ protection
The settings for the FRQ (over/under frequency) protection are as follows:
• Select "FRQ" on the "Scheme sw" screen to display the "FRQ" screen.
/ 7 F R Q P r o t .
F R Q 1 E N _
> F R Q 1 E N 0
O f f / O F / U F
F R Q 2 E N 0
O f f / O F / U F
D F R Q 1 E N 0
O f f / R / D
D F R Q 2 E N 0
O f f / R / D
<FRQ∗EN>
To set the FRQ∗ scheme enable, do the following.
• Enter 1(=OF, overfrequency) or 2(=UF, underfrequency) and press the ENTER key. If
disabling the FRQ∗, enter 0(=Off) and press the ENTER key.
<DFRQ∗EN>
To set the FRQ∗ scheme enable, do the following.
• Enter 1(=R, frequency rise rate) or 2(=UF, frequency decay rate) and press the ENTER key. If
 137 
6 F 2 T 0 1 7 9
disabling the FRQ∗, enter 0(=Off) and press the ENTER key.
Setting the M.Trip function
The settings for tripping external devices element are as follows:
• Select "M.Trip" on the "Scheme sw" screen to display the "M.Trip" screen.
/ 7 M . T r i p .
M . T 1 - 1 _
> M . T 1 - 1 0
O f f / O n
M . T 1 - 2 0
O f f / O n
M . T 2 - 1 0
O f f / O n
M . T 2 - 2 0
O f f / O n
M . T 3 - 1 0
O f f / O n
M . T 3 - 2 0
O f f / O n
M . T 4 - 1 0
O f f / O n
M . T 4 - 2 0
O f f / O n
<M.T∗-∗>
• Enter 1 (=On) to enable the tripping external devices function and press the ENTER key. If
disabling the UV blocking, enter 0 (=Off) and press the ENTER key.
Setting the protection elements

To set the protection elements, do the following.
• Select "Prot. element" on the "Trip" screen to display the "Prot. element" screen.
 138 
6 F 2 T 0 1 7 9
/ 6 P r o t . e l e m e n t
> D I F P r o t .
R E F P r o t . Not available for model 100 and 300 series
V / f P r o t . Not available for model 100 and 200 series
O C P r o t .
E F P r o t .
N O C P r o t .
M i s c . P r o t .
O V P r o t . Not available for model 100 and 200 series
U V P r o t . Not available for model 100 and 200 series
F R Q P r o t . Not available for model 100 and 200 series
Setting the transformer parameters and Differencial protection function

To set the transformer parameter and differential protection function setting, do the following.
• Select "DIF prot." on the "Prot.element" screen to display the "DIF prot." screen.
/ 7 D I F p r o t .
i k _ p u
> i k 1 . 0 5 p u
p 1 8 0 %
p 2 6 0 %
k p 2 . 0 0 p u
k h 1 0 . 0 0 p u
T x C a p 1 0 0 . 0 M V A
V n 1 1 . 5 k V
V n 2 0 . 2 k V
y d _ P 1
y d _ s 2
v e c _ s 2 0 0
k 2 f 2 0 %
k 5 f 5 0 %
k t h 5 . 0 p u
T D I F 0 . 0 0 s
T D I F H S 1 0 . 0 0 s
For details of the transformer parameter setting, refer to 2.2.5.
• Enter the numerical value and press the ENTER key.
 139 
6 F 2 T 0 1 7 9
• Press the ENTER (=Y) key to change settings and return to the "Prot. element" screen.
Setting the transformer parameters and Restricted earth fault protection function
To set the transformer parameter and Restricted earth fault l protection function setting, do the
following.
• Select "REF prot." on the "Prot.element" screen to display the "REF prot." screen.
/ 7 R E F p r o t .
1 i k _ p u
> 1 i k 1 . 0 5 p u
1 p 2 8 0 %
1 k p 2 . 0 0 p u
T 1 R E F 0 . 0 0 s
2 i k 1 . 0 5 p u
2 p 2 8 0 %
2 k p 2 . 0 0 p u
T 2 R E F 0 . 0 0 s
1 R E F O C 1 1 . 0 0 0 p u
1 R E F O C 2 1 . 0 0 0 p u
T 1 R E F O C 1 1 0 . 0 0 s
T 1 R E F O C 2 5 . 0 0 s
2 R E F O C 1 1 . 0 0 0 p u
2 R E F O C 2 1 . 0 0 0 p u
T 2 R E F O C 1 1 0 . 0 0 s
T 2 R E F O C 2 5 . 0 0 s
 140 
6 F 2 T 0 1 7 9
Setting the V / f protection

To set the Overexitation protection function setting, do the following.
/ 7 V / f p r o t .
V _ V
> V 0 . 0 V
A 0 . 0 0 p u
L 0 . 1 5 p u
H 0 . 9 5 p u
L T 5 1 s
H T 1 3 s
R T 5 1 s
T V F H 1 0 0 s
T V F A 2 0 0 s
Setting the OC protection

• Select "OC prot." on the "Prot. element" screen to display the "OC prot." screen.
/ 7 O C P r o t .
1 O C 1 p u
> 1 O C 1 2 . 5 0 p u
1 O C I 1 1 . 5 0 p u
T 1 O C 1 1 . 0 0 s This setting is displayed if [M1OC1] is 0(=DT)

T 1 O C 1 M 1 . 5 0 0 This setting is displayed if [M1OC1] is 1(=IEC) , 2(=IEEE) or 3(=US).
T 1 O C 1 R 1 . 0 0 s This setting is displayed if [1OC1R] is 0(=DEF) .
T 1 O C 1 R M 1 . 0 0 0 This setting is displayed if [M1OC1] is 2(=IEEE) or 3(=US).
1 O C 1 - k 0 . 0 0 0 This setting is displayed if [M1OC1] is 4(=C)
1 O C 1 - α 0 . 0 0 ditto
1 O C 1 - C 0 . 0 0 0 ditto
1 O C 1 - k r 0 . 0 0 0 ditto
 141 
6 F 2 T 0 1 7 9
1 O C 1 - β 0 . 0 0 ditto
1 O C 2 3 . 0 0 p u
2 O C 1 5 . 0 0 p u
2 O C 2 1 0 . 0 0 p u
Setting the EF protection

• Select "EF prot." on the "Prot. element" screen to display the "EF prot." screen.
/ 7 E F P r o t .
1 E F 1 p u
> 1 E F 1 2 . 5 0 p u
1 E F I 1 1 . 5 0 p u
T 1 E F 1 1 . 0 0 s This setting is displayed if [M1EF1] is 0(=DT)

T 1 E F 1 M 1 . 5 0 0 This setting is displayed if [M1EF1] is 1(=IEC) , 2(=IEEE) or 3(=US).
T 1 E F 1 R 1 . 0 0 s This setting is displayed if [1EF1R] is 0(=DEF) .
T 1 E F 1 R M 1 . 0 0 0 This setting is displayed if [M1EF1] is 2(=IEEE) or 3(=US).
1 E F 1 - k 0 . 0 0 0 This setting is displayed if [M1EF1] is 4(=C)
1 E F 1 - α 0 . 0 0 ditto
1 E F 1 - C 0 . 0 0 0 ditto
1 E F 1 - k r 0 . 0 0 0 ditto
1 E F 1 - β 0 . 0 0 ditto
1 E F 2 3 . 0 0 p u
2 E F 1 5 . 0 0 p u
2 E F 2 1 0 . 0 0 p u
 142 
6 F 2 T 0 1 7 9
Setting the NOC protection

• Select "NOC prot." on the "Prot. element" screen to display the "NOC prot." screen.
/ 7 N O C P r o t .
1 N C 1 p u
> 1 N C 1 2 . 5 0 p u
1 N C I 1 1 . 5 0 p u
T 1 N C 1 1 . 0 0 s This setting is displayed if [M1NC1] is 0(=DT)

T 1 N C 1 M 1 . 5 0 0 This setting is displayed if [M1NC1] is 1(=IEC) , 2(=IEEE) or 3(=US).
T 1 N C 1 R 1 . 0 0 s This setting is displayed if [1NC1R] is 0(=DEF) .
T 1 N C 1 R M 1 . 0 0 0 This setting is displayed if [M1NC1] is 2(=IEEE) or 3(=US).
1 N C 1 - k 0 . 0 0 0 This setting is displayed if [M1NC1] is 4(=C)
1 N C 1 - α 0 . 0 0 ditto
1 N C 1 - C 0 . 0 0 0 ditto
1 N C 1 - k r 0 . 0 0 0 ditto
1 N C 1 - β 0 . 0 0 ditto
1 N C 2 3 . 0 0 p u
2 N C 1 5 . 0 0 p u
2 N C 2 1 0 . 0 0 p u
N C V 2 . 0 V
 143 
6 F 2 T 0 1 7 9
Setting the Misc. protection elements

• Select "Misc." on the "Prot. element" screen to display the "Misc." screen.
/ 7 M i s c P r o t .
1 O C V _ V
> 1 O C V 1 2 0 . 0 V
1 O C V I S 5 . 0 0 p u
T 1 O C V M 1 . 0 0 0
T 1 O C V R 3 0 0 . 0 s This setting is displayed if [M1OCV] is 1(=IEC) , 2(=IEEE) or 3(=US).

T 1 O C V M R 1 . 0 0 0 This setting is displayed if [1OCVR] is 0(=DEF)
1 O C V - k 0 . 0 0 0 This setting is displayed if [M1OCV] is 4(=C)
1 O C V - α 0 . 0 0 ditto
1 O C V - C 0 . 0 0 0 ditto
1 O C V - k r 0 . 0 0 0 ditto
1 O C V - β 0 . 0 0 ditto
2 O C V 1 2 0 . 0 V
2 O C V I S 5 . 0 0 p u
T 1 O C V M 1 . 0 0 0
T 1 O C V R 3 0 0 . 0 s This setting is displayed if [M2OCV] is 1(=IEC) , 2(=IEEE) or 3(=US).

T 1 O C V M R 1 . 0 0 0 This setting is displayed if [2OCVR] is 0(=DEF)
2 O C V - k 0 . 0 0 0 This setting is displayed if [M2OCV] is 4(=C)
2 O C V - α 0 . 0 0 ditto
2 O C V - C 0 . 0 0 0 ditto
2 O C V - k r 0 . 0 0 0 ditto
2 O C V - β 0 . 0 0 ditto
T H M 1 . 0 0 A
T H M 1 P 0 . 0 0 A
T T H M 1 0 . 0 m i n
T H M A 8 0 %
I C D 1 - 2 f 2 5 %
I C D 1 O C 0 . 8 0 p u
I C D 2 - 2 f 2 5 %
I C D 2 O C 1 . 5 0 p u
 144 
6 F 2 T 0 1 7 9
C B F 1 0 . 4 0 p u
T B T C 1 1 0 0 . 0 0 s
T R T C 1 0 . 0 0 s
C B F 2 0 . 4 0 p u
T B T C 2 0 . 0 0 s
T R T C 2 0 . 0 0 s
Setting the OV elements

• Select "OV prot." on the "Prot. element" screen to display the "OV prot." screen.
/ 7 O V P r o t .
O V 1 _ V
> O V 1 1 2 0 . 0 V OV1 Threshold setting.

T O V 1 1 . 0 0 s This setting is displayed if [OV1EN] is 1(=DT).
T O V 1 M 1 . 0 0 This setting is displayed if [OV1EN] is 2(=IDMT) or 3 (=C).
T O V 1 R 0 . 0 s
O V 1 D P R 9 5 % OV1 DO/PU ratio

O V 1 - k 1 . 0 0 This setting is displayed if [OV1EN] is 3 (=C).
O V 1 - α 1 . 0 0 ditto.
O V 1 - C 0 . 0 0 0 ditto.
O V 2 1 4 0 . 0 V OV2 Threshold setting.
T O V 2 1 . 0 0 s OV2 Definite time delay.
O V 2 D P R 9 5 % OV2 DO/PU ratio
 145 
6 F 2 T 0 1 7 9
• Press the ENTER (= Y) key to change settings and return to the "Prot. element" screen.
Setting the UV elements

• Select "UV" on the "Prot. element" screen to display the "UV" screen.
/ 7 U V P r o t .
U V 1 _ V
> U V 1 6 0 . 0 V UV1 Threshold setting.

T U V 1 1 . 0 0 s This setting is displayed if [UV1EN] is 1(=DT).
T U V 1 M 1 . 0 0 This setting is displayed if [UV1EN] is 2(=IDMT) or 3 (=C).
T U V 1 R 0 . 0 s This setting is displayed if [UV1EN] is 2(=IDMT) or 3 (=C).
U V 1 - k 1 . 0 0 This setting is displayed if [UV1EN] is 3 (=C).
U V 1 - α 1 . 0 0 dittio.
U V 1 - C 0 . 0 0 0 dittio.
U V 2 4 0 . 0 V UV2 Threshold setting.
T U V 2 1 . 0 0 s UV2 Definite time delay.
V B L K 1 0 . 0 V This setting is displayed if [vBLKEN] is 1 (=On).
Setting the FRQ elements

• Select "FRQ prot." on the "Prot. element" screen to display the "FRQ prot." screen.
/ 7 F R Q P r o t .
F R Q 1 _ H z
> F R Q 1 - 1 . 0 0 H z
T F R Q 1 1 . 0 0 s
F R Q 2 - 1 . 0 0 H z
T F R Q 2 1 . 0 0 s
F V B L K 2 0 . 0 V UV Blocking threshold
D F R Q 1 0 . 5 H z s
D F R Q 2 0 . 5 H z s
 146 
6 F 2 T 0 1 7 9
Setting group copy

To copy the settings of one group and overwrite them to another group, do the following:
• Select "Copy gp." on the "Protection" screen to display the "Copy A to B" screen.
/ 3 C ｏｐｙ A t o B
> A _
B _
• Enter the group number to be copied in line A and press the ENTER key.
• Enter the group number to be overwritten by the copy in line B and press the ENTER key.
4.2.6.8 Binary Input

The logic level of binary input signals can be inverted by setting before entering the scheme logic.
Inversion is used when the input contact cannot meet the requirements described in Table 3.2.2.
• Select "Binary I/P" on the "Set. (change)" sub-menu to display the "Binary I/P" screen.
/ 2 B i n a r y I / P
> B I S t a t u s
B I 1
B I 2
B I 3
B I 4
B I 5
B I 6
B I 7 Not available for model xx0 model
B I 1 0 Not available for model xx0 model
B I 1 3 Not available for model xx0 and xx1 model
 147 
6 F 2 T 0 1 7 9
Setting Binary Input Status

GRE160 can selected the binary input detection threshold voltage. The threshold voltage supports
control voltages of 24V, 48V, 110V and 220V.
BI1 and BI2 can be changed between three threshold voltages - 48 / 110 / 220V ( or 12 / 24 / 48V)
BI3 to BI6, BI12 or BI18 can be changed between two threshold voltages – 110 / 220V (or 24 / 48V)
Note: The threshold voltage of 48V (or 12V) of BI1 and BI2 is used for Trip Circuit Surpervision
using 2 Binary inputs. See section 3.3.3.
The threshold voltage of 48-220V and 12-48V correspond to individual relay models,
respectively.
To set the binary inputs threshold voltage, do the following:
• Select "BI Status" on the "Binary I/P" screen to display the "BI Status" screen.
/ 3 B I S t a t u s
B I T H R 1 _
> B I T H R 1 0
4 8 / 1 1 0 / 2 2 0
B I T H R 2 0
1 1 0 / 2 2 0
<BITHR1>
To set the Binary Input 1 and 2 threshold voltage, do the following.
• Enter 0(=48V) or 1(=110V) or 2(=220V) and press the ENTER key.
<BITHR2>
To set the Binary Input 3 to 6, 12 or 18 threshold voltage, do the following.
• Enter 0(=110V) or 1(=220V) and press the ENTER key.
Selection of Binary Input

• Select the input number (BI number) on the "Binary I/P" screen.
After setting, press the ENTER key to display the "BI∗" screen.
/ 3 B I ＊
> T i m e r s
F u n c t i o n s
 148 
6 F 2 T 0 1 7 9
Setting timers
• Select "Timers" on the "BI" screen to display the "Timers" screen.
/ 4 T i m e r s
B I ＊ P U D _ s
> B I ＊ P U D 0 . 0 0 s Pick-up delay setting

B I ＊ D O D 0 . 0 0 s Drop-off delay setting
• After setting, press the END key to return to the "BI∗" screen.
Setting Functions
• Select "Functions" on the "BI" screen to display the "Functions" screen.
/ 4 F u n c t i o n s
B I ＊ S N S _
> B I ＊ S N S 0
N o r m / I n v
• To set the Binary Input Sense, enter 0(=Normal) or 1(=Inverted) and press the ENTER key.
• After setting, press the END key to return to the "BI∗" screen.
Each binary input circuit is programmable by PLC function
4.2.6.9 Binary Output

All the binary outputs of the GRE160 except the relay failure signal are user-configurable. It is
possible to assign one signal or up to four ANDing or ORing signals to one output relay. Available
signals are listed in Appendix B.
It is also possible to attach Instantaneous or delayed or latched reset timing to these signals.
Appendix D shows the factory default settings.
CAUTION
When having changed the binary output settings, release the latch state on a digest screen by
pressing the RESET key for longer than 3 seconds.
To configure the binary output signals, do the following:
Selection of output relay

• Select "Binary O/P" on the "Set. (change)" screen to display the "Binary O/P" screen.
For Models 100, 200, 300, 400 and 500:
 149 
6 F 2 T 0 1 7 9
/ 2 B i n a r y O / P
> B O 1
B O 2
B O 3
B O 4
For Models 101, 201, 301, 401 and 501:

/ 2 B i n a r y O / P
> B O 1
B O 2
B O 3
B O 4
B O 5
B O 6
B O 7
B O 8
B O 9
B O 1 0
For Models 102, 202, 302, 402 and 502:

/ 2 B i n a r y O / P
> B O 1
B O 2
B O 3
B O 4
B O 5
B O 6
B O 7
B O 8
B O 9
B O 1 0
B O 1 1
B O 1 2
B O 1 3
B O 1 4
B O 1 5
B O 1 6
Note: The setting is required for all of the binary outputs. If any of the binary outputs are not used,
enter 0 to logic gates #1 to #6 in assigning signals.
 150 
6 F 2 T 0 1 7 9
• Select the output relay number (BO number) and press the ENTER key to display the "BO∗"
screen.
/ 3 B O *
> L o g i c / R e s e t
F u n c t i o n s
Setting the logic gate type and timer

• Select "Logic/Reset" to display the "Logic/Reset" screen.
/ 4 L o g i c / R e s e t
L o g i c _
> L o g i c 0
O R / A N D
R e s e t 0
I n s / D l / D w / L a t
• Enter 0(=OR) or 1(=AND) to use an OR gate or AND gate and press the ENTER key.
• Enter 0(=Instantaneous) or 1(=Delayed) or 2(=Dwell) or 3(=Latched) to select the reset timing

• Press the END key to return to the "BO∗" screen.

Note: To release the latch state, push the [RESET] key for longer than 3 seconds.
Assigning signals
• Select "Functions" on the "BO∗" screen to display the "Functions" screen.
I n ♯ 1 _
> I n ♯ 1
I n ♯ 2
I n ♯ 3
I n ♯ 4
I n ♯ 5
I n ♯ 6
T B O 0 . 2 0 s
• Assign signals to gates (In #1 to #6) by entering the number corresponding to each signal
referring to Appendix C. Do not assign the signal numbers 471 to 477 and 487 to 490 (signal
 151 
6 F 2 T 0 1 7 9
names: "BO1 OP" to "BO16 OP"). And set the delay time of timer TBO.
Note: If signals are not assigned to all the gates #1 to #6, enter 0 for the unassigned gate(s).
Repeat this process for the outputs to be configured.
4.2.6.10 LEDs
Six LEDs of the GRE160 are user-configurable. A configurable LED can be programmed to
indicate the OR combination of a maximum of 4 elements, the individual status of which can be
viewed on the LED screen as “Virtual LEDs.” The signals listed in Appendix C can be assigned to
each LED as follows.
CAUTION
When having changed the LED settings, it is necessary to release the latch state on a digest
screen by pressing the RESET key for longer than 3 seconds.
Selection of LEDs
• Select "LED" on the "Set. (change)" screen to display the "LED" screen.
/ 2 L E D
> L E D
V i r t u a l L E D
Selection of real LEDs

• Select "LED" on the "/2 LED" screen to display the "/3 LED" screen.
/ 3 L E D
> L E D 1
L E D 2
L E D 3
L E D 4
L E D 5
L E D 6
C B C L O S E D
• Select the LED number and press the ENTER key to display the "LED∗" screen.
/ 4 L E D ＊
F u n c t I o n s
L E D C o l o r
 152 
6 F 2 T 0 1 7 9
Setting the logic gate type and reset type

L o g i c _
> L o g i c 0
O R / A N D
R e s e t 0
I n s t / L a t c h
• Enter 0(=OR) or 1(=AND) to use an OR gate or AND gate and press the ENTER key.
• Enter 0(=Instantaneous) or 1(=Latched) to select the reset timing and press the ENTER key.
• Press the END key to return to the "LED∗" screen.

Note: To release the latch state, refer to Section 4.2.1.
Assigning signals
• Select "Functions" on the "LED∗" screen to display the "Functions" screen.
I n ♯ 1 _
> I n ♯ 1
I n ♯ 2
I n ♯ 3
I n ♯ 4
• Assign signals to gates (In #1 to #4) by entering the number corresponding to each signal
referring to Appendix C.
Note: If signals are not assigned to all the gates #1 to #4, enter 0 for the unassigned gate(s).

Setting the LEDs color

• Select "LED color" on the "LED∗ " screen or on the "CB CLOSED" screen to display the "LED
color" screen.
/ 5 L E D C o l o r
C o l o r _
> C o l o r 0
R / G / Y
 153 
6 F 2 T 0 1 7 9
• Select the LED colors of red, green or yellow.

Repeat this process for the LED colors to be configured.
Selection of virtual LEDs

• Select "Virtual LED" on the "/2 LED" screen to display the "Virtual LED" screen.
/ 3 V i r t u a l L E D
> I N D 1
I N D 2
• Select the IND number and press the ENTER key to display the "IND∗" screen.
/ 4 I N D ＊
> R e s e t
F u n c t i o n s
Setting the reset timing

• Select "Reset" to display the "Reset" screen.
/ 5 R e s e t
R e s e t _
> R e s e t 0
I n s t / L a t c h
• Enter 0(=Instantaneous) or 1(=Latched) to select the reset timing and press the ENTER key.
• Press the END key to return to the "IND∗" screen.

Note: To release the latch state, push the [RESET] key for longer than 3 seconds.
Assigning signals
• Select "Functions" on the "IND∗" screen to display the "Functions" screen.
B I T 1 _
> B I T 1
B I T 2
B I T 3
 154 
6 F 2 T 0 1 7 9
B I T 4
B I T 5
B I T 6
B I T 7
B I T 8
• Assign signals to bits (1 to 8) by entering the number corresponding to each signal referring to
Appendix C.
Note: If signals are not assigned to all the bits 1 to 8, enter 0 for the unassigned bit(s).
• Press the END key to return to the "IND∗" screen.

4.2.6.11 Control
The GRE160 can enable the control of two Circuit Breakers(CB1, CB2) open / close using the front
panel keys.
The interlock function can block the two Circuit Breaker(CB1, CB2) close command by an interlock
signal from a binary input signal or a communication command.
To set the control function and CB1 interlock function(interlock1) and CB2 interlock function
(interlock2), do the following:
• Select "Control" on the "Set. (change)" screen to display the "Control" screen.
/ 2 C o n t r o l
C o n t r o l _
> C o n t r o l 0
D i s a b l e / E n a b l e
I n t e r l o c k 1 0
I n t e r l o c k 2 0
• Enter 0(=Disable) or 1(=Enable) to select whether or not the control function is to be used and
• Enter 0(=Disable) or 1(=Enable) to select whether of not the interlock1 and interlock2 functions
are to be used and press the ENTER key.
Note: When the Control function is disabled, both the "Local" LED and the "Remote" LED are not
lit, and the sub-menu "Control" on the LCD is not displayed.
4.2.6.12 Frequency
The GRE160 is provided with a setting to select the system frequency i.e. 50Hz or 60Hz.
• Select "Frequency" on the "Set. (change)" screen to display the "Frequency" screen.
 155 
6 F 2 T 0 1 7 9
/ 2 F r e q u e n c y
F r e q u e n c y _
> F r e q u e n c y 0
5 0 H z / 6 0 H z
• Enter 0(=50Hz) or 1(=60Hz) to select the system frequency setting 50Hz or 60Hz and press the
ENTER key.
CAUTION
When having changed the system frequency settings, the GRE160 must reboot to enable the
setting change.
4.2.7 Control
The sub-menu "Control" enables the CB1 and CB2 control function using the front panel keys - ○ ,
｜ and L/R .
Note: When the Control function is disabled, both the "Local" LED and the "Remote" LED are not
lit, and the sub-menu "Control" on the LCD is not displayed.
4.2.7.1 Local / Remote Control

The "Local/Remote" function provides change of CB control hierarchy.
• Select "Control" on the "MAIN MENU" screen to display the "Control" screen.
/ 1 C o n t r o l
> P a s s w o r d ( C t r l )
L o c a l / R e m o t e
C B 1 c l o s e / o p e n
• Move the cursor to "Local/Remote" on LCD.
/ 1 C o n t r o l
P a s s w o r d ( C t r l )
> L o c a l / R e m o t e
• The L/R key is enabled to change the CB control hierarchy.
 156 
6 F 2 T 0 1 7 9
4.2.7.2 CB close / open Control

The "CB1 close/open" and "CB2 close/open" function provides CB1 and CB2 control.
• Move the cursor to "CB1 close/open" on the LCD.
/ 1 C o n t r o l
P a s s w o r d ( C t r l )
L o c a l / R e m o t e
> C B 1 c l o s e / o p e n
• The ｜ and ○ keys are enabled to control CB1 – close / open.

CB2 control is same as CB1 control.
4.2.7.3 Password
For the sake of security of control password protection can be set as follows:
• Select "Control" on the "MAIN MENU" screen to display the "Control" screen.
C o n t r o l
I n p u t [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜
C o n t r o l
R e t y p e [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜
"Unmatch passwd!"
Password trap
 157 
6 F 2 T 0 1 7 9
screens.
If "Set. (change)" is entered on the "MAIN MENU" screen, the password trap screen "Password" is
displayed. If the password is not entered correctly, it is not possible to move to the "Setting
(change)" sub-menu screens.
C o n t r o l
P a s s w o r d [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜

The "Test" screen is then displayed without having to enter a password.

Press the CANCEL and RESET keys together for one second on the "MAIN MENU" screen.
The password protection of the GRE160 is canceled. Set the password again.
4.2.8 Testing
The sub-menu "Test" provides such functions as disabling the automatic monitoring functions and
enables the forced operation of binary outputs. The password, if set, must be entered in order to
enter the test screens because the "Test" menu has password security protection. (See the section
4.2.6.2.) If the password trap is set, enter the password in the following screen.
T e s t
I n p u t [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜
Note: When operating the "Test" menu, the "IN SERVICE" LED is flickering. But if an alarm occurs
during the test, the flickering stops. The "IN SERVICE" LED flickers only in a testing state.
• Select "Test" on the top "MENU" screen to display the "Test" screen.
/ 1 T e s t
> P a s s w o r d ( T e s t )
S w i t h
B i n a r y O / P
• Select "Switch" to display the "Switch" screen.
 158 
6 F 2 T 0 1 7 9
Setting the switches

The automatic monitor function (A.M.F.) can be disabled by setting the switch [A.M.F] to "OFF".
Disabling the A.M.F. prevents tripping from being blocked even in the event of a failure in the items
being monitored by this function. It also prevents failures from being displayed on the "ALARM"
LED and LCD described in Section 4.2.1. No events related to A.M.F. are recorded, either.
Disabling A.M.F. is useful for blocking the output of unnecessary alarms during testing.
Note: Set the switch [A.M.F] to "Off" before applying the test inputs, when the A.M.F is disabled.
The switch [RESET] is used to test the THM and V/F elements. When the switch [RESET] is set to
"1", the time counting of inverse time characteristic can be forcibly reset.
While the switch [A.M.F] is set to "0" or [RESET] is set to "1", the red "TESTING" LED is lit for
alarm purposes.
Caution: Be sure to restore these switches after the tests are completed.
/ 2 S w i t h
A . M . F _
> A . M . F 1
O f f / O n
U V T D T 0
O f f / O n
R E S E T 0
O f f / O n
I E C T S T 0
O f f / O n
• Enter 0(=Off) to disable the A.M.F. and press the ENTER key.
• Enter 1(=On) for UVTDT to disable the UV block when testing UV elements and press the
ENTER key.
• Enter 1(=On) to set the reset delay time of the thermal overload element and overexitation
element to instantaneous reset for testing (RESET) and press the ENTER key.
• Enter 1(=On) for IECTST to transmit ‘test mode’ to the control system by IEC60870-5-103
communication when testing the local relay, and press the ENTER key.
• Press the END key to return to the "Test" screen.
4.2.8.2 Binary Output Relay
It is possible to forcibly operate all binary output relays for checking connections with external
devices. Forced operation can be performed on one or more binary outputs at a time.
• Select "Binary O/P" on the "Test" screen to display the "Binary O/P" screen. Then the LCD
displays the name of the output relay.
 159 
6 F 2 T 0 1 7 9
/ 2 B i n a r y O / P
B O 1 _
> B O 1 0
B O 2 0
B O 3 0
B O 4 0
D i S a b l e / E n a b l e
B O 5 0
B O 6 0
B O 1 6 0
F A I L 0
• Enter 1(=Enable) and press the ENTER key to operate the output relays forcibly.
• After completing the entries, press the END key. Then the LCD displays the screen shown
below.
O p e r a t e ?
E N T R Y = Y C A N C E L = N
• Press the ENTER key continuously to operate the assigned output relays.
• Release the ENTER key to reset the operation.

• Press the CANCEL key to return to the upper "Binary O/P" screen.
4.2.8.3 Password
For the sake of security of testing password protection can be set as follows:
• Select "Test" on the "MAIN MENU" screen to display the "Test" screen.
 160 
6 F 2 T 0 1 7 9
T e s t
I n p u t [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜
T e s t
R e t y p e [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜
"Unmatch passwd!"
Password trap
screens.
If "TEST" is entered on the "MAIN MENU" screen, the password trap screen "Password" is
displayed. If the password is not entered correctly, it is not possible to move to the "TEST"
sub-menu screens.
T e s t
P a s s w o r d [ _ ]
1 2 3 4 5 6 7 8 9 0 ＜

The "Test" screen is then displayed without having to enter a password.

Press the CANCEL and RESET keys together for one second on the "MAIN MENU" screen.
The screen goes off, and the password protection of the GRE160 is canceled. Set the password
again.
 161 
6 F 2 T 0 1 7 9
4.3 Personal Computer Interface

The relay can be operated from a personal computer using a USB port on the front panel.
On the personal computer, the following analysis and display of the fault currents are available in
addition to the items available on the LCD screen.
• Display of current and voltage waveforms: Oscillograph display
• Symmetrical component analysis: On arbitrary time span
• Harmonic analysis: On arbitrary time span
• Frequency analysis: On arbitrary time span
For details, see separate instruction manual "PC INTERFACE RSM100".
4.4 MODBUS Interface

The GRE160 supports the MODBUS communication protocol. This protocol is mainly used when
the relay communicates with a control system and is used to transfer the following measurement and
status data from the relay to the control system. (For details, see Appendix M.)
• Measurement data: current
• Status data: events, fault indications, counters, etc.
• Setting data
• Remote CB operation － Open / Close
• Time setting / synchronization
The protocol can be used through the RS485 port on the relay rear panel.
The relay supports two baud-rates 9.6kbps and 19.2kbps. These are selected by setting. See Section
4.2.6.4.
4.5 IEC 60870-5-103 Interface
The GRE160 supports the IEC60870-5-103 communication protocol. This protocol is mainly used
for relay communication when the relay communicates with a control system and is used to transfer
the following measurand and status data from the relay to the control system. (For details, see
Appendix M.)
• Measurand data: current, voltage, active power, reactive power, frequency
• Status data: events, fault indications, etc.
The protocol can be used through the RS485 port or the Fibre optic port on the relay rear panel.
The relay supports two baud-rates 9.6kbps and 19.2kbps. These are selected by setting. See Section
4.2.6.4.
The data transfer from the relay can be blocked by setting.
For the settings, see the Section 4.2.6.
4.6 IEC 61850 Communication _ Option

GRE160 can also support data communication according to the IEC 61850 standard with the
provision of an optional communication board. Station bus communication as specified in IEC
61850-8-1 facilitates integration of the relays within substation control and automation systems via
Ethernet LAN.
 162 
6 F 2 T 0 1 7 9
4.7 Clock Function

The clock function (Calendar clock) is used for time-tagging for the following purposes:
• Event records
• Disturbance records
• Fault records
The calendar clock can run locally or be synchronised with an external clock such as the binary time
standard input signal, RSM clock, IEC60870-5-103 or SNTP for IEC61850 etc. This can be
selected by setting (see 4.2.6.6.).
The “clock synchronise” function synchronises the relay internal clock to the BI (connected to PLC
input No.2576 SYNC_CLOCK) by the following method. Since the BI signal is an “ON” or “OFF”
signal which cannot express year-month-day and hour-minute-second etc, synchronising is achieved
by setting the number of milliseconds to zero. This method will give accurate timing if the
synchronising BI signal is input every second.
Synchronisation is triggered by an “OFF” to “ON” (rising edge) transition of the BI signal. When
the trigger is detected, the millisecond value of the internal clock is checked, and if the value is
between 0~499ms then it is rounded down. If it is between 500~999ms then it is rounded up (ie the
number of seconds is incremented).
n sec (n+1) sec

500ms
corrected to (n+1) sec
corrected to n sec
t
When the relays are connected with the RSM system as shown in Figure 4.4.1 and "RSM" is
selected in the time synchronisation setting, the calendar clock of each relay is synchronised with the
RSM clock. If the RSM clock is synchronised with the external time standard, then all of the relay
clocks are synchronised with the external time standard.
4.8 Special Mode

The GRE140 shifts to the following special mode by using a specific key operation.
• LCD contrast adjustment mode
• Light check mode
LCD contrast adjustment mode

When the LCD is not displayed or not displayed clearly, the contrast adjustment of LCD might not
be appropriate. To adjust the contrast of the LCD screen on any screen, do the following:
• Press ▼ and ▲ ,at same time for 3 seconds or more to shift to LCD contrast adjustment mode.
L C D C o n t r a s t
■ ■ ■ ■
 163 
6 F 2 T 0 1 7 9
• Press the
▼
or key to adjust the contrast.
LCD and LED check mode

To perform a LCD and LED check , do the following.
• Press the
▲
key for 3 seconds or more when the LCD is off.
• While pressing the
▲
key all LEDs are lit and white dots appear on the whole LCD screen.
The colors of configurable LEDs displayed (LED1-6) are the user setting color.
• Release the
▲
key , to finish the LCD and LED check mode.
 164 
6 F 2 T 0 1 7 9
5. Installation
5.1 Receipt of Relays
When relays are received, carry out the acceptance inspection immediately. In particular, check for
damage during transportation, and if any is found, contact the vendor.
Always store the relays in a clean, dry environment.
5.2 Relay Mounting

The relay case is designed for flush mounting using four mounting attachment kits.
Appendix F shows the case outlines.
127
5
14
117 13 5
Fig. 5.2.1 Outline of attachment kit
This attachment kits can be mounted on a panel of thickness 1 – 2.5mm when the M4x8 screws that
are included with the realy are used. When mounted on a panel of thickness 2.5-4.5mm, M4x10
screws and washers should be used.
5.2.1 Flush Mounting
For flush mounting the panel cut-out;

・Mount the case in the panel cut-out from the front of panel. ; See Fig.5.2.2.
・Use the mounting attachment kits set ; See Fig.5.2.3.
・Tighten the M4 screw of the attachment kits ; see Fig.5.2.3.
The allowed range for the fixing screws’ tightening torque is 1.0…1.4Nm.
Do not tighten the screws too tightly.
 165 
6 F 2 T 0 1 7 9
Fig. 5.2.2 Flush mounting the case into a panel cut-out
Fig. 5.2.3 Side view of GRE160 with the mounting attachment kit positions
 166 
6 F 2 T 0 1 7 9
5.3 Electrostatic Discharge

CAUTION
Do not remove the relay PCB from the relay case since electronic components on the modules are
very sensitive to electrostatic discharge.
5.4 Handling Precautions

A person's normal movements can easily generate electrostatic potential of several thousand volts.
Discharge of these voltages into semiconductor devices when handling electronic circuits can cause
serious damage, which often may not be immediately apparent but the reliability of the circuit will
have been reduced.
The electronic circuits are completely safe from electrostatic discharge when housed in the case. Do
not expose them to risk of damage.
5.5 External Connections

External connections are shown in Appendix G.
 167 
6 F 2 T 0 1 7 9
6. Commissioning and Maintenance

6.1 Outline of Commissioning Tests
The GRE160 is fully numerical and the hardware is continuously monitored.
Commissioning tests can be kept to a minimum and need only include hardware tests and
conjunctive tests. The function tests are at the user’s discretion.
In these tests, user interfaces on the front panel of the relay or local PC can be fully applied.
Test personnel must be familiar with general relay testing practices and safety precautions to avoid
personal injuries or equipment damage.
Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware defect.
Defects of hardware circuits other than the following can be detected by monitoring which circuits
function when the DC power is supplied.
User interfaces
Binary input circuits and output circuits
AC input circuits
Function tests
These tests are performed for the following functions that are fully software-based.
Measuring elements
Metering and recording
Conjunctive tests
The tests are performed after the relay is connected with the primary equipment and other external
equipment.
The following tests are included in these tests:

On load test: phase sequence check and polarity check
Tripping circuit test
6.2 Cautions
6.2.1 Safety Precautions
CAUTION
• When connecting the cable to the back of the relay, firmly fix it to the terminal block and attach
the cover provided on top of it.
• Before checking the interior of the relay, be sure to turn off the power.
Failure to observe any of the precautions above may cause electric shock or malfunction.
 168 
6 F 2 T 0 1 7 9
6.2.2 Cautions on Tests
CAUTION
• While the power is on, do not draw out/insert the relay unit.
• Before turning on the power, check the following:
- Make sure the polarity and voltage of the power supply are correct.
- Make sure the CT circuit is not open.
- Make sure the VT circuit is not short-circuited.
• Be careful that the transformer module is not damaged due to an overcurrent or overvoltage.
• If settings are changed for testing, remember to reset them to the original settings.
Failure to observe any of the precautions above may cause damage or malfunction of the relay.
6.3 Preparations
Test equipment
The following test equipment is required for the commissioning tests.
1 Single-phase voltage source
2 Single-phase current sources
1 Variable-frequency source
1 Combined fundamental and 2nd-harmonic adjustable current supply
1 Combined fundamental and 5th-harmonic adjustable current supply
1 DC power supply
1 DC voltmeter
1 AC voltmeter
1 Phase angle meter
2 AC ammeters
1 Frequency meter
1 Time counter, precision timer
1 PC (not essential)
Relay settings
Before starting the tests, it must be specified whether the tests will use the user’s settings or the
default settings.
For the default settings, see the following appendixes:

Appendix D Binary Output Default Setting List
Appendix H Relay Setting Sheet
Visual inspection
After unpacking the product, check for any damage to the relay case. If there is any damage, the
internal module might also have been affected. Contact the vendor.
Relay ratings
Check that the items described on the nameplate on the front of the relay conform to the user’s
specification. The items are: relay type and model, AC voltage, current and frequency ratings, and
auxiliary DC supply voltage rating.
 169 
6 F 2 T 0 1 7 9
Local PC
When using a local PC, connect it with the relay via the RS-232C port on the front of the relay.
RSM100 software is required to run the PC.
For the details, see the separate instruction manual "PC INTERFACE RSM100".
6.4 Hardware Tests

The tests can be performed without external wiring, but DC power supply and AC voltage and
current source are required.
6.4.1 User Interfaces
This test ensures that the LCD, LEDs and keys function correctly.
LCD ･ LED display

• Apply the rated supply voltage and check that the LCD is off and the "IN SERVICE" LED is lit
in green.
Note: If there is a failure, the LCD will display the "ERR: " screen when the supply voltage is applied.
• Press the
▲
key for 3 seconds or more and check that white dots appear on the whole screen and
all LEDs are lit.
Operation keys
• Press the ENTER key when the LCD is off and check that the LCD displays the "MAIN
MENU" screen. Press the END key to turn off the LCD.
• Press the ENTER key when the LCD is off and check that the LCD displays the "MAIN
MENU" screen. Press any keys and check that all keys operate.
 170 
6 F 2 T 0 1 7 9
6.4.2 Binary Input Circuit
The testing circuit is shown in Figure 6.4.1.
(a) for GRE160-100, 200, 300, 400, 500
(b) for GRE160-101, 201, 301, 401, 501
(c) for GRE160-102, 202, 302, 402, 502

Figure 6.4.1 Testing Binary Input Circuit
 171 
6 F 2 T 0 1 7 9
• Display the "Binary I/O" screen from the "Status" sub-menu.
/ 2 B i n a r y I / O
I P [ 0 0 0 0 0 0 ]
I P 2 [ 0 0 0 0 0 0 ] Not available for Model xx0

I P 3 [ 0 0 0 0 0 0 ] Not available for Models xx0 and xx1
O P [ 0 0 0 0 ]
O P 2 [ 0 0 0 0 0 0 ] Not available for Model xx0

O P 3 [ 0 0 0 0 0 0 ] Not available for Models xx0 and xx1
F A I L [ 0 ]
• Apply the rated DC voltage to terminals 13 - 14, 15 - 16 , 17, 18, 19, 20 - 22 of terminal block
TB6 , terminals 13 - 14, 15 - 16 , … , 23 - 24 of terminal block TB1 for model xx1 or xx2, and
terminals 13 - 14, 15 - 16 , … , 23 - 24 of terminal block TB3 for model xx2.
Check that the status display corresponding to the input signal (IP) changes from 0 to 1. (For
details of the binary input status display, see Section 4.2.4.2.)
6.4.3 Binary Output Circuit
This test can be performed by using the "Test" sub-menu and forcibly operating the relay drivers and
output relays. Operation of the output contacts is monitored at the output terminal. The output
contact and corresponding terminal number are shown in Appendix G.
• Select "Binary O/P" on the "Test" screen to display the "Binary O/P" screen. The LCD displays
the name of the output relay.
/ 2 B i n a r y O / P
B O 1 _
> B O 1 0
B O 2 0
B O 3 0
B O 4 0
B O 5 0
Not available for Model xx0
ditto
B O 1 0 0
ditto
B O 1 1 0
Not available for Models xx0 and xx1.
ditto
 172 
6 F 2 T 0 1 7 9
B O 1 6 0
ditto
F A I L 0
• Enter 1 and press the ENTER key.
• After completing the entries, press the END key. The LCD will display the screen shown
below. If 1 is entered for all the output relays, the following forcible operation can be performed
collectively.
O p e r a t e ?
E N T R Y = Y C A N C E L = N
• Press the ENTER key continuously to forcibly operate the output relays.
• Check that the output contacts operate at the terminal.

• Release the ENTER key to reset the operation
6.4.4 AC Input Circuits
This test can be performed by applying known values of voltage and current to the AC input circuits
and verifying that the values applied coincide with the values displayed on the LCD screen.
The testing circuits are shown in Figures 6.4.2. A three-phase voltage source and a single-phase
current source are required.
 173 
6 F 2 T 0 1 7 9
Figure 6.4.2 Testing AC Input Circuit (Model 500s)
• Check that the metering data is set to be expressed as secondary values on the "Metering switch"
screen.
"Settings" sub-menu → "Status" screen → "Metering switch" screen
If the setting is “Display Value = Primary”, change the setting in the "Metering switch" screen.
Remember to reset it to the initial setting after the test is finished.
• Open the "Metering" screen in the "Status" sub-menu.
"Status" sub-menu → "Metering" screen
• Apply AC rated voltages and currents and check that the displayed values are within ± 5% of the
input values.
6.5 Function Test

CAUTION
The function test may cause the output relays to operate including the tripping output relays.
Therefore, the test must be performed with tripping circuits disconnected.
6.5.1 Measuring Element
Measuring element characteristics are realized by the software, so it is possible to verify the overall
characteristics by checking representative points.
 174 
6 F 2 T 0 1 7 9
Operation of the element under test is observed by assigning the signal number to a configurable
LED or a binary output relay.
CAUTION
After testing, it is necessary to reset the settings used for testing to the original settings.
In case of a three-phase element (at model 500 series), it is sufficient to test for a representative
phase. The A-phase element is selected hereafter. Further, the [APPLCT] and [APPLVES] settings
are selected “3PN” and “3PN”.
Assigning signal to LED

• Select "LED" on the "Set. (change)" screen to display the "2/ LED" screen.
/ 2 L E D
> L E D
V i r t u a l L E D
• Select "LED" on the "/2 LED" screen to display the "/3 LED" screen.
/ 3 L E D
> L E D 1
L E D 2
L E D 3
L E D 4
L E D 5
L E D 6
C B C L O S E D
Note: The setting is required for all of the LEDs. If any of the LEDs are not used, enter 0 to logic gates
#1 to #4 in assigning signals.
Assigning signal to Binary Output Relay

• Select "Binary O/P" on the "Set. (change)" screen to display the "Binary O/P" screen.
Note: The setting is required for all of the binary outputs. If any of the binary outputs are not used,
enter 0 to logic gates In #1 to #4 in assigning signals.
• Select the output relay number (BO number) and press the ENTER key to display the "BO∗"
screen.
/ 3 B O ∗
F u n c t i o n s
 175 
6 F 2 T 0 1 7 9
L o g i c _
> L o g i c 0
O R / A N D
R e s e t 0
I n s / D l / D w / L a t
• Enter 0 (= OR) and press the ENTER key.
• Enter 0 (= Instantaneous) and press the ENTER key.
• Press the END key to return to the "BO∗" screen.
• Select "Functions" on the "BO∗" screen to display the "Functions" screen.
I n ♯ 1 _
> I n ♯ 1
_ _ _
I n ♯ 2
_ _ _
I n ♯ 3
_ _ _
I n ♯ 4
_ _ _
I n ♯ 5
_ _ _
I n ♯ 6
_ _ _
• Assign the gate In #1 to the number corresponding to the testing element by referring to
Appendix B, and assign other gates the value “0”.
6.5.1.1 Current differential element DIF

The current differential element is checked on the following items
• Operating current value
• Percentage restraining characteristic
• Operating time
Note: Set all the CT ratio matching settings (kct1 to kct2) to “1” and phase angle matching settings
(d1 to d2) to “0” in the testing described in 6.5.1.1 to 6.5.1.4, because the operating value
depends on the settings.
Operating current value

Minimum operating current value is checked by simulating a one-end infeed. Figure 6.5.1 shows a
testing circuit simulating an infeed from a primary winding.
 176 
6 F 2 T 0 1 7 9
Figure 6.5.1 Operating Current Value Test Circuit
The output signal of the testing element is assigned to a configurable LED.

The output signal numbers of the DIF elements are as follows:
Element Signal number
DIF-A 402
DIF-B 403
DIF-C 404
• Enter the signal number to observe the operation at the LED as shown in Section 6.5.1 and
• Apply a test current to A-phase current terminals and change the magnitude of the current
applied and measure the value at which the element DIF-A operates.
Check that the measured value is within 7% of the theoretical operating value.
Theoretical operating value = (CT secondary rated current) × (ik setting)
Percentage restraining characteristics

The percentage restraining characteristic is tested on the outflow current (Iout) and infeed current (Iin)
plane as shown in Figure 6.5.2. The characteristic shown in Figure 6.5.2 is equivalent to the one on
the differential current (Id) and restraining current (Ir) plane shown in Figure 2.11.1.
Iout
DF2
DF1
0 ik 2+p1 2−p1 Iin

2 kp + 4 ik
Figure 6.5.2 Current Differential Element (Iout - Iin Plane)
 177 
6 F 2 T 0 1 7 9
Figure 6.5.3 shows a testing circuit simulating an infeed from a primary winding and outflow from
a secondary winding.
Figure 6.5.3 Percentage Restraining Characteristic Test of DIF

• Enter the signal number to observe the operation at the LED as shown in Section 6.5.1 and
• Apply an infeed current to terminal TB4-1 and -2.

When the infeed current applied is larger than the setting of ik (pu) and smaller than
kp(2+p1)/2 + ik(2-p1)/4 (pu), characteristic DF1 is checked.
When the infeed current applied is larger than kp(2+ p1)/2 + ik(2- p1)/4 (pu), characteristic
DF2 is checked.
Note: When the default settings are applied, the critical infeed current which determines
DF1 checking or DF2 checking is 1.56×(CT secondary rated current).
• Apply an outflow current of the same magnitude and counterphase with the infeed current to
terminal TB5-1 and -2.
• Decrease the out flow current in magnitude and measure the values at which the element
operates.
• Check that the measured values are within 7% of the theoretical values.
For characteristic DF1, the theoretical outflow current is given by the following equation:
Iout = (2−p1)(Iin−ik)/(2+p1) (pu)
where, p1 = slope setting of DF1

ik = minimum operating current setting
When the default settings are applied, Iout = [(Iin−0.3) / 3]× (CT secondary rated current).
For characteristic DF2, the theoretical outflow current is given by the following equation.
Iout = [(2−p2)Iin −(2−p1)ik + 2(p2− p1)kp]/(2+ p2) (pu)
where, p2 = slope setting of DF2
kp = break point of DF1 and DF2
 178 
6 F 2 T 0 1 7 9
When the default settings are applied, Iout = 0.43× (CT secondary rated current).
Operating time
Figure 6.5.4 Operating Time Test
• Set a test current to 3 times of DIF operating current (= CT secondary rated current × ik setting).
• Apply the test current and measure the operating time.
• Check that the operating time is 40 ms or less.
6.5.1.2 2F element
Figure 6.5.5 Testing 2F Element

The output signal number of the 2F element is as follows:

2F 405
 179 
6 F 2 T 0 1 7 9
• Set the second harmonic restraint setting k2f to 15%(= default setting).
• Enter a signal number to observe the 2F output at the LED as shown in Section 6.5.1 and
• Set the fundamental frequency current I1 to 3 times of ik setting. Change the magnitude of the
second harmonic current I2 and measure the value at which the element operates.
• Calculate the percentage of the second harmonic by I2/I1 when the element operates. Check
that the percentage is within 7% of the k2f setting.
6.5.1.3 5F element
Figure 6.5.6 Testing 5F Element
The output signal number of the 5F element is as follows:

5F 409
• Set the fifth harmonic restraint setting k5f to 30%.(= default setting)
• Enter a signal number to observe the 5F output at the LED as shown in Section 6.5.1 and
• Set the fundamental frequency current I1 to 3 times of ik setting. Change the magnitude of the
fifth harmonic current I5 and measure the value at which the element operates.
• Calculate the percentage of the fifth harmonic by I5/I1 when the element operates. Check that
the percentage is within 7% of the k5f setting.
 180 
6 F 2 T 0 1 7 9
6.5.1.4 High-set overcurrent element HOC

Operating current value
The output signal numbers of the HOC elements are as follows:

HOC-A 414
HOC-B 415
HOC-C 416
• Enter a signal number 41 to observe the HOC-A output as shown in Section 6.5.1 and press
the ENTER key.
• Apply a test current to A-phase current terminals and change the magnitude of the current
applied and measure the value at which the element operates.
Check that the measured value is within 7% of the following value.
Operating value = (CT secondary rated current) × (kh setting)
Operating time
• Set a test current to 2 times of HOC operating current (= CT secondary rated current × kh
setting)
• Apply the test current and measure the operating time.
• Check that the operating time is 35 ms or less.
6.5.1.5 Restricted earth fault element REF

The restricted earth fault element is checked on the following items.
• Operating current value
• Percentage restraining characteristic
Note: Set all the CT ratio matching settings (1kct1 - 1kct2 to 2kct1 - 2kct2) to "1", because the
operating value depends on the settings.
Operation current value

Figure 6.5.7 Operating Current Value Test of REF_DIF element (Model 200s, 400s, 500s)
 181 
6 F 2 T 0 1 7 9
The test current input terminal number and output signal number of the REF_DIF element is as
follows:
Element Input terminal Output signal
number number
1REF_DIF TB4-7 and –8 420
2REF_DIF TB5-7 and –8 425
• Enter the signal number 29 to observe the 1REF_DIF output at the LED as shown in Section
6.5.1 and press the ENTER key.
• Apply a test current to TB4-7 and -8 and change the magnitude of the current applied and
measure the value at which the element operates.
Check that the measured value is within 15% of the theoretical operating value.
Theoretical operating value = (CT secondary rated current) × (1ik setting)
Percentage restraining characteristics
The percentage restraining characteristic is tested on the outflow current (lout) and infeed current (lin)
plane as shown in Figure 6.5.8. The characteristic shown in Figure 6.5.8 is equivalent to the one on
the differential current (ld) and restraining current (lr) plane shown in Figure 2.11.2.
Iout
DF2
DF1
Operating zone
0 ik [kp･p2 + (1- p1)ik]/(p2 – p1) Iin
Figure 6.5.8 REF_DIF Element (Iout - Iin Plane)
Figure 6.5.9 shows a testing circuit simulating infeed from a neutral circuit and outflow from a
primary winding.
 182 
6 F 2 T 0 1 7 9
Figure 6.5.9 Testing Restricted Earth Fault Element (Model 200s, 400s, 500s)
• Enter a signal number 29 to observe the 1REF_DIF output at the LED as shown in Section 6.5.1
• Apply an infeed current to terminal TB4-1 and -2.

When the infeed current applied is larger than the setting of ik (pu) and smaller than [kp⋅p2 +
(1−p1)ik]/(p2 − p1) (pu), characteristic DF1 is checked.
When the infeed current applied is larger than [kp⋅p2 + (1−p1)ik]/(p2 − p1) (pu), characteristic
DF2 is checked.
Note: When the default settings are applied, the critical infeed current which determines
DF1 checking or DF2 checking is 1.6×(CT secondary rated current).
• Apply an outflow current of the same magnitude and counterphase with the infeed current, to
terminal TB4-7 and -8.
• Decrease the outflow current in magnitude and measure the values at which the element operates.
• Check that the measured values are within 15% of the theoretical values.
For characteristic DF1, the theoretical outflow current is given by the following equation.
Iout = (1−p1)(Iin−ik) (pu)
where,
p1 = slope setting of DF1 (= 0.1 fixed)
ik = minimum operating current setting
When the default settings are applied, Iout = 0.9× (Iin – 0.5) × (CT secondary rated current). For
characteristic DF2, the theoretical outflow current is given by the following equation
Iout = (1−p2) Iin + p2×kp (pu)
where,
p2 = slope setting of DF2
kp = restraining current section setting of DF2
When the default settings are applied, Iout = 1.0 × (CT secondary rated current).
 183 
6 F 2 T 0 1 7 9
6.5.1.6 Definite time overcurrent elements OC, EF

Figure 6.5.10 Testing OC and EF (Model 200s, 400s, 500s)

1OC, 2OC 221, 237
1EF, 2EF 261, 265
Setting the OC or EF element on the "OC prot." or "EF prot." screen.
The testing procedure is as follows:

• Enter a signal number to observe the OC or EF output at the LED as shown in Section 6.5.1 and
• Apply a test current and change the magnitude of the current applied and measure the value at
which the element operates.
Check that the measured value is within ±5% of the theoretical operating value.
Theoretical operating value = (CT secondary rated current) × (OC or EF setting)
 184 
6 F 2 T 0 1 7 9
6.5.1.7 Inverse time overcurrent elements OCI, EFI

Figure 6.5.11 Testing OCI and EFI
One of the four inverse time characteristics can be set, and the output signal numbers are as follows:
1OCI, 2OCI 225, 241
1EFI, 2EFI 262, 266
Fix the time characteristic to test by setting the OCI or EFI on the "OC prot." or "EF prot." screen.

• Enter a signal number to observe the OCI or EFI output at the LED as shown in Section 6.5.1
• Apply a test current and measure the operating time. The magnitude of the test current should be
between 1.2 × Is to 20 × Is, where Is = (CT secondary rated current) × (OCI or EFI current
setting).
• Calculate the theoretical operating time using the characteristic equations shown in Section
2.11.4. Check that the measured operating time is within the error mentioned below.
6.5.1.8 Thermal overload element THM

 185 
6 F 2 T 0 1 7 9
Figure 6.5.12 Testing THM
Setting the THM element on the "Misc prot." screen.

The output signal of testing element is assigned to the LED.
The output signal numbers of the elements are as follows:
Element Signal No.
THM-TRIP 293
THM-ALARM 292
To test easily the thermal overload element, the scheme switch [RESET] in the "Switch" screen on
the "Test" menu is used.
• Set the scheme switch [RESET] to "ON".
• Enter the signal number to observe the operation at the LED as shown in Section 6.5.1.
• Apply a test current and measure the operating time. The magnitude of the test current should be
between 1.2 × Is to 10 × Is, where Is is the current setting.
CAUTION
After the setting of a test current, apply the test current after checking that the THM% has
become 0 on the "Metering" screen.
2.10.6. Check that the measured operating time is within 5%.
 186 
6 F 2 T 0 1 7 9
6.5.1.9 Frequency element FRQ

The frequency element is checked on the following items
• Operating frequency
• Undervoltage block
Operating frequency test

Figure 6.5.13 Testing Frequency Element (Model 300s, 400s, 500s)
The output signal numbers of the FRQ elements are as follows:

Element Signal No.
FRQ1 356
FRQ2 357
Setting the FRQ element on the "FRQ prot." screen.

• Enter a signal number to observe the FRQ output at the LED and press the ENTER key.
• Apply rated voltage and change the magnitude of the frequency applied and measure the
value at which the element operates. Check that the measured value is within ±0.03Hz of the
setting.
Undervoltage block test

• Apply rated voltage and change the magnitude of frequency to operate the element.
• Keep the frequency that the element is operating, and change the magnitude of the voltage
applied from the rated voltage to less than [FVBLK] setting voltage. And then, check that the
element resets.
6.5.1.10 Overexcitation element V/F

The overexcitation element is checked on the following items
• Operating value of definite time tripping and alarm characteristic
• Operating time of inverse time tripping characteristic
The output signal numbers of the V/F elements are as follows:
 187 
6 F 2 T 0 1 7 9
Element Signal number Remarks

V / f-T 431 Inverse time tripping
V / f-H 432 Definite time tripping
V / f-A 433 Definite time alarm
Operating value test for definite time tripping and alarm

Figure 6.5.14 Operating Value Test of V/F (Model 300s, 400s, 500s)
• Set V (rated voltage setting) to 100V.

• Enter a signal number 437 or 438 to observe the V/F output at the LED and press the
ENTER key.
• Apply a test voltage at rated frequency and increase the magnitude of the voltage applied and
measure the value at which an alarm signal or a trip signal is output.
Check that the measured values are within 2% of (V setting) × (A setting) for an alarm signal
and (V setting) × (H setting) for a trip signal.
Operating time characteristic test

Figure 6.5.15 Operating Time Characteristic Test of V/F (Model 300s, 400s, 500s)
 188 
6 F 2 T 0 1 7 9

• Enter a signal number 81 to observe the inverse time tripping output at monitoring jack A and
Note: Set the swich [Reset] to “Off”→ “On”→ “Off” to initialize a time count. See Section 4.2.7.1.
• Apply a test voltage at rated frequency and measure the operating time. The magnitude of the
test voltage should be between (V setting) × (L setting) and (V setting) × (H setting).
2.11.8 where V is the test voltage. Check that the measured operating time is from +15% to
−10% of the calculated value.
6.5.2 Protection Scheme
In the protection scheme tests, a dynamic test set is required to simulate power system pre-fault,
fault and post-fault conditions.
Tripping can be observed by monitoring the tripping command output relays when a simulated fault
is applied.
6.5.3 Metering and Recording
The metering function can be checked while testing the AC input circuit. See Section 6.4.4.
Fault recording can be checked while testing the protection schemes. Open the "Fault record" screen
and check that the descriptions are correct for the fault concerned.
Recording events are listed in Appendix D. There are internal events and external events from binary
input commands. Event recording for the external event can be checked by changing the status of
binary input command signals. Change the status in the same way as for the binary input circuit test
(see Section 6.4.2) and check that the description displayed on the "Event record" screen is correct.
Some of the internal events can be checked in the protection scheme tests.
Disturbance recording can be checked while testing the protection schemes. The LCD display only
shows the date and time when a disturbance is recorded. Open the "Disturbance record" screen and
check that the descriptions are correct.
Details can be displayed on a PC. Check that the descriptions on the PC are correct. For details on
how to obtain disturbance records on a PC, see the RSM100 Manual.
 189 
6 F 2 T 0 1 7 9
6.6 Conjunctive Tests

6.6.1 On Load Test
With the relay connected to the line which is carrying a load current, it is possible to check the
polarity of the voltage transformer and current transformer and the phase rotation with the metering
displays on the LCD screen.
• Open the "Auto-supervision" screen, check that no message appears.
• Open the following "Metering" screen from the "Status" sub-menu.
/ 3 M e t e r i n g
I a 1 * * * . * * k A
I b 1 * * * . * * k A
I c 1 * * * . * * k A
I a 2 * * . * * * A
I b 2 * * * . * * k A
I c 2 * * * . * * k A
I 1 1 * * . * * * A
I 2 1 * * * . * * k A
I 0 1 * * * . * * k A
I 1 2 * * * . * * k A
I 2 2 * * * . * * k A
I 0 2 * * * . * * k A
V a * * * . * * k V Available for model 500 series
V b * * * . * * k V Available for model 500 series
V c * * * . * * k V Available for model 500 series
V a b * * * . * * k V Available for model 500 series
V b c * * * . * * k V Available for model 500 series
V c a * * * . * * k V Available for model 500 series
V 1 * * * . * * k V Available for model 500 series
V 2 * * * . * * k V Available for model 500 series
V O * * * . * * k V Available for model 500 series
I 2 / I 1 1 * * . * *
I 2 / I 1 2 * * . * *
T H M * * * . * %
I d a * * * . * * p u
I d b * * * . * * p u
I d c * * * . * * p u
I r a * * * . * * p u Not available for model 100, 300 series
 190 
6 F 2 T 0 1 7 9
I r b * * * . * * p u Not available for model 100, 300 series
I r c * * * . * * p u Not available for model 100, 300 series
I d o 1 * * * . * * p u
I d o 2 * * * . * * p u
I r o 1 * * * . * * p u Not available for model 100, 300 series
I r o 2 * * * . * * p u Not available for model 100, 300 series
P F - * . * * * Available for model 500 series
P - * * * * * * k W Available for model 500 series
Q - * * * * * * k v a r Available for model 500 series
S - * * * * * * k V A Available for model 500 series
Note: The magnitude of voltage and current can be set in values on the primary side or on the
secondary side by the setting. (The default setting is the primary side.)
Phase angles are expressed taking that of the voltage input as the reference angle.
• Check that the phase rotation is correct.

• Verify the phase relation between voltage and current with a known load current direction.
6.6.2 Tripping Circuit Test
The tripping circuit including the circuit breaker is checked by forcibly operating the output relay
and monitoring the breaker that is tripped. Forcible operation of the output relay is performed on the
"Binary output" screen of the "Test" sub-menu as described in Section 6.4.3.
Tripping circuit
• Set the breaker to be closed.
• Select "Binary O/P" on the "Test" sub-menu screen to display the "Binary O/P" screen.
/ 2 B i n a r y O / P
B O 1 _
> B O 1 0
B O 2 0
B O 3 0
B O 4 0
B O 5 0
Not available for Model xx0
ditto
 191 
6 F 2 T 0 1 7 9
B O 1 0 0
ditto
B O 1 1 0
Not available for Models xx0 and xx1.
ditto
B O 1 6 0
ditto
F A I L 0
BO1 to BO16 are output relays with one normally open contact.
• Enter 1 for BO1 and press the ENTER key.
• Press the END key. The LCD will display the screen shown below.
O p e r a t e ?
• Continue to press the ENTER key to maintain the operation of binary output relay BO1 and
check that the A-phase breaker has tripped.
• Release the ENTER key to reset the operation.
• Repeat the above for BOs.
 192 
6 F 2 T 0 1 7 9
6.7 Maintenance
6.7.1 Regular Testing
The relay is almost completely self-supervised. The circuits which cannot be supervised are binary
input and output circuits and human interfaces.
Therefore regular testing can be minimized to checking the unsupervised circuits. The test
procedures are the same as described in Sections 6.4.1, 6.4.2 and 6.4.3.
6.7.2 Failure Tracing and Repair
Failures will be detected by automatic supervision or regular testing.

When a failure is detected by the supervision, a remote alarm is issued by the binary output relay
called FAIL and the failure is indicated on the front panel by the LED indicators or on the LCD
display. It is also recorded in the event record.
Failures detected by the supervision can be traced by checking the "Err: " screen on the LCD. Table
6.7.1 shows the LCD messages and failure locations.
The items marked with (1) have a higher probability of being the cause of failure than those items
marked with (2).
Table 6.7.1 LCD Message and Failure Location

Message Failure location
CB or
Relay Unit AC cable PLC data
cable
Err: SUM ×(Flash memory)
Err: ROM ×(ROM data)
Err: RAM ×(SRAM)
Err: CPU ×(CPU)
Err: Invalid ×
Err: NMI ×
Err: BRAM ×(Backup RAM)
Err: EEP ×(EEPROM)
Err: A/D ×(A/D converter)
Err: SP ×(Sampling)
Err: DC ×(DC power supply circuit)
Err: TC ×(Tripping circuit)(1) × (2)
Err: CT, Err: V0, Err: V2 × (AC input circuit)(1) × (2)
Err: CB × (Circuit breaker)(1) × (2)
Err: PLC ×(PLC data)
( ): Probable failure location in the relay unit including peripheral circuits.
If no message is shown on the LCD, this means that the failure location is either in the DC power
supply circuit or in the microprocessors. If the "ALARM" LED is off, the failure is in the DC power
supply circuit. If the LED is lit, the failure is in the microprocessors. Replace the relay unit in both
cases after checking if the correct DC voltage is applied to the relay.
If a failure is detected by either the automatic supervision functions or by regular testing, replace the
failed relay unit.
 193 
6 F 2 T 0 1 7 9
Note: When a failure or an abnormality is detected during regular testing, confirm the following
first:
- Test circuit connections are correct.
- Modules are securely inserted in position.
- Correct DC power supply voltage is applied.
- Correct AC inputs are applied.
- Test procedures comply with those stated in the manual.
6.7.3 Replacing Failed Modules

If the failure is identified to be in the relay unit and the user has a spare relay unit, the user can
recover the protection by replacing the failed relay unit.
Repair at site should be limited to relay unit replacement. Maintenance at the component level is not
recommended.
Check that the replacement relay unit has an identical Model Number and relay version (software
type form) as the relay that is to be replaced.
The Model Number is indicated on the front of the relay. For the relay version, see Section 4.2.5.1.
Replacing the relay unit

CAUTION After replacing the relay unit, check the settings including the data related to the
PLC, IEC103 and IEC61850, etc. are restored the original settings.
The procedure for relay withdrawal and insertion is as follows:

• Switch off the DC power supply.
WARNING Hazardous voltage may remain in the DC circuit immediately following the
switching off the DC power supply. It takes approximately 30 seconds for the
voltage to discharge.
• Disconnect the trip outputs.
• Short-circuit all AC current inputs. Open all AC voltage inputs.
• Remove the terminal blocks from the relay leaving the wiring.
• To remove the relay unit from the panel, remove the attachments screws.
• Insert the (spare) relay unit in the reverse procedure.
CAUTION To avoid risk of damage:
• When the attachment kits are removed, be careful to ensure that the relay does not to fall
from panel.
• The cover of the relay front panel is closed during operation.
6.7.4 Resumption of Service
After replacing the failed relay, take the following procedures to restore the relay to the service.
• Switch on the power supply and confirm that the "IN SERVICE" green LED is lit and the
"ALARM" red LED is not lit.
• Supply the AC inputs and reconnect the trip outputs.
6.7.5 Storage
The spare relay should be stored in a dry and clean room. Based on IEC Standard 60255-6 the
storage temperature should be −25°C to +70°C, but a temperature of 0°C to +40°C is recommended
for long-term storage.
 194 
6 F 2 T 0 1 7 9
7. Putting Relay into Service

The following procedure must be adhered to when putting the relay into service after finishing the
commissioning tests or maintenance tests.
• Check that all of the external connections are correct.
• Check the settings of all measuring elements, timers, scheme switches, recordings and the clock
are correct.
In particular, when settings are changed temporarily for testing, be sure to restore them.
• Clear any unnecessary records on faults, events and disturbances which are recorded during the
tests.
• Press the ▼ key and check that no failure messages are displayed on the "Auto-supervision"
screen.
• Check that the green "IN SERVICE" LED is lit.
 195 
6 F 2 T 0 1 7 9
Appendix A
Block Diagram
 196 
6 F 2 T 0 1 7 9
Scheme Logic No.1

DIFT1 TRIP-1
DIFT1 HOC TP1 TRIP OUTPUT
(#87) DIF ≥1 CONTACT aNo.1
Scheme
2f lock 1 & switches
for
5f lock 1 each element
(ON)
1REF1 +
1REF1(#87N) − (OFF)
&
REF_DEF 1REFOC1
1REFOC1(#87G)
1OC1
1OC1 (#50) t 0
0.00-300.00s 1OCI1
1OCI1(#51)
1EF1
1EF1 (#50N) t 0
0.00-300.00s 1EFI1
1EFI1(#51N)
1NOC1 Scheme Logic No.2
1NOC1 (#46N) t 0
≥1 DIFT2
0.00-300.00s 1NOCI1 TRIP-2 TRIP OUTPUT
1REF2 TP2
1NOCI1(#46N) CONTACT No.2
1REFOC2
2REF1 1OC2
2REF1(#87N)
& 1OCI2
REF_DEF Same as
1EF2
2REFOC1(#87G) No.1 circuit
1EFI2
2OC1 1NOC2
2OC1 (#50) t 0
1NOCI2
0.00-300.00s 2OCI1
2OCI1(#51)
2REF2
2EF1 2REFOC2
2EF1 (#50N) t 0
2OC2
0.00-300.00s 2EFI1 2OCI2
2EFI1(#51N) 2EF2
2NOC1 2EFI2
2NOC1 (#46N) t 0
2NOC1
0.00-300.00s 2NOCI1 2NOCI1
2NOCI1(#46N)
V/F1
V/F1 L
t 0 ≥1
(#59/81) H V/F2
OCV1 OCV2
0.00-300.00s
OCV1 Cont OV2
≥1 UV2
(#51V) Rest
OV1 CBF2
t 0 FRQ2
OV1 (#59)
0.00-300.00s
UV1 M.1.2-TRIP
t 0 M.2.2-TRIP
UV1 (#27)
M.3.2-TRIP
0.00-300.00s
CBF1 M.4.2-TRIP
t 0
CBF1 (#51BF)
0.00-300.00s
t 0 FRQ1
FRQ1 L
0.00-300.00s ≥1
(#81) H t 0
0.00-300.00s
M.1.1-TRIP
Ext.Mechanical Trip 1
M.2.1-TRIP
Ext.Mechanical Trip ２
M.3.1-TRIP
Ext.Mechanical Trip ３
M.4.1-TRIP
Ext.Mechanical Trip ４
: Relay Element : Binary input/output

Block Diagram of Transformer Differential Relay GRE160
Block Diagram of Transformer Differential Relay GRE160
 197 
6 F 2 T 0 1 7 9
Appendix B
Signal List
 198 
6 F 2 T 0 1 7 9
No. Signal Name Contents
0 CONSTANT_0 constant 0
1 CONSTANT_1 constant 1
2
3
4
5
6
7
8
9
10
11 1OC1-A 1OC1-A relay element output
12 1OC1-B 1OC1-B relay element output
13 1OC1-C 1OC1-C relay element output
14 1OC1-A_INST 1OC1-A relay element start
15 1OC1-B_INST 1OC1-B relay element start
16 1OC1-C_INST 1OC1-C relay element start
17 1OC1-IDMT-A 1OC1-A relay element output
18 1OC1-IDMT-B 1OC1-B relay element output
19 1OC1-IDMT-C 1OC1-C relay element output
47 1OC1-A_HS High speed output of 1OC1-A relay
48 1OC1-B_HS High speed output of 1OC1-B relay
 199 
6 F 2 T 0 1 7 9

49 1OC1-C_HS High speed output of 1OC1-C relay
50 2OC1-A_HS High speed output of 2OC1-A relay
51 2OC1-B_HS High speed output of 2OC1-B relay
52 2OC1-C_HS High speed output of 2OC1-C relay
53
54
55
56
57
58
59
60
61 1EF1 1EF1 relay element output
62 1EF1_INST 1EF1 relay element start
63 1EF1-IDMT 1EF1 relay element output
73
74 1EF_HS High speed output of 1EF relay
75 2EF_HS High speed output of 2EF relay
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100 ICD1-A Inrush Line current detector
 200 
6 F 2 T 0 1 7 9

101 ICD1-B Inrush Line current detector
102 ICD1-C Inrush Line current detector
103 ICD2-A Inrush Line current detector
104 ICD2-B Inrush Line current detector
105 ICD2-C Inrush Line current detector
106
107 THM-A THERMAL Alarm relay element output
108 THM-T THERMAL Trip relay element output
109
110 1NOC1 1NOC1 relay element output
111 1NOC1_INST 1NOC1 relay element start
112 1NOC1-IDMT 1NOC1 relay element output
122
123 CBF1-A CBF1-A relay element output
124 CBF1-B CBF1-B relay element output
125 CBF1-C CBF1-C relay element output
126 CBF2-A CBF2-A relay element output
127 CBF2-B CBF2-B relay element output
128 CBF2-C CBF2-C relay element output
129
130 1OC-A_DIST OC-A relay for disturbance record
131 1OC-B_DIST OC-B relay for disturbance record
132 1OC-C_DIST OC-C relay for disturbance record
133 1EF_DIST EF relay for disturbance record
134
135
136 2OC-A_DIST OC-A relay for disturbance record
137 2OC-B_DIST OC-B relay for disturbance record
138 2OC-C_DIST OC-C relay for disturbance record
139 2EF_DIST EF relay for disturbance record
140
141
142
143
144
145
146
147
148
149
150 OV1-A OV1-A relay element output
151 OV1-B OV1-B relay element output
152 OV1-C OV1-C relay element output
153 OV1-A_INST OV1-A relay element start
 201 
6 F 2 T 0 1 7 9

154 OV1-B_INST OV1-B relay element start
155 OV1-C_INST OV1-C relay element start
156 OV2-A OV2-A relay element output
157 OV2-B OV2-B relay element output
158 OV2-C OV2-C relay element output
159
160 UV1-A UV1-A relay element output
161 UV1-B UV1-B relay element output
162 UV1-C UV1-C relay element output
163 UV1-A_INST UV1-A relay element start
164 UV1-B_INST UV1-B relay element start
165 UV1-C_INST UV1-C relay element start
166 UV2-A UV2-A relay element output
167 UV2-B UV2-B relay element output
168 UV2-C UV2-C relay element output
169
170
171
172
173
174
175
176 UVBLK UV blocked element operating
177 FRQ1 FRQ1 relay element ouput
178 FRQ2 FRQ2 relay element ouput
179
180
181 FRQBLK FRQ blocked element operating
182
183
184 DFRQ1 DFRQ1 relay element ouput
185 DFRQ2 DFRQ2 relay element ouput
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
 202 
6 F 2 T 0 1 7 9

207
208
209 OV-A_DIST OV-A relay for disturbance record
210 OV-B_DIST OV-B relay for disturbance record
211 OV-C_DIST OV-C relay for disturbance record
212 UV-A_DIST UV-A relay for disturbance record
213 UV-B_DIST UV-B relay for disturbance record
214 UV-C_DIST UV-C relay for disturbance record
215
216
217
218
219
220
221 1OC1_TRIP 1OC1 trip command
222 1OC1-A_TRIP 1OC1 trip command (A Phase)
223 1OC1-B_TRIP 1OC1 trip command (B Phase)
224 1OC1-C_TRIP 1OC1 trip command (C Phase)
225 1OC1-IDMT_TRIP 1OCI1 trip command
226 1OC1-IDMT-A_TRIP 1OCI1 trip command (A Phase)
227 1OC1-IDMT-B_TRIP 1OCI1 trip command (B Phase)
228 1OC1-IDMT-C_TRIP 1OCI1 trip command (C Phase)
245 2OC2_TRIP 2OC2 alarm command
246 2OC2-A_TRIP 2OC2 alarm command (A Phase)
247 2OC2-B_TRIP 2OC2 alarm command (B Phase)
248 2OC2-C_TRIP 2OC2 alarm command (C Phase)
253
254
255
256
257
258
259
 203 
6 F 2 T 0 1 7 9

260
261 1EF1_TRIP 1EF1 trip command
262 1EF1-IDMT_TRIP 1EFI1 trip command
267 2EF2_TRIP 2EF2 alarm command
268 2EF2-IDMT_TRIP 2EFI2 alarm command
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292 THM_ALARM Thermal alarm command
293 THM_TRIP Thermal trip command
294
295 1NOC1_TRIP 1NOC1 trip command
296 1NOC1-IDMT_TRIP 1NOCI1 trip command
297 1NOC2_ALARM 1NOC2 trip command
303 CBF1_RETRIP CBF1 retrip command
304 CBF1_RETRIP-A CBF1 retrip command(A Phase)
305 CBF1_RETRIP-B CBF1 retrip command(B Phase)
306 CBF1_RETRIP-C CBF1 retrip command(C Phase)
307 CBF1_TRIP CBF1 back trip command
308 CBF1_TRIP-A CBF1 back trip command(A Phase)
309 CBF1_TRIP-B CBF1 back trip command(B Phase)
310 CBF1_TRIP-C CBF1 back trip command(C Phase)
311 CBF1_OP-A CBF1 start signal (A phase)
 204 
6 F 2 T 0 1 7 9

312 CBF1_OP-B CBF1 start signal (B phase)
313 CBF1_OP-C CBF1 start signal (C phase)
314 CBF2_RETRIP CBF2 retrip command
315 CBF2_RETRIP-A CBF2 retrip command(A Phase)
316 CBF2_RETRIP-B CBF2 retrip command(B Phase)
317 CBF2_RETRIP-C CBF2 retrip command(C Phase)
318 CBF2_TRIP CBF2 back trip command
319 CBF2_TRIP-A CBF2 back trip command(A Phase)
320 CBF2_TRIP-B CBF2 back trip command(B Phase)
321 CBF2_TRIP-C CBF2 back trip command(C Phase)
322 CBF2_OP-A CBF2 start signal (A phase)
323 CBF2_OP-B CBF2 start signal (B phase)
324 CBF2_OP-C CBF2 start signal (C phase)
325
326
327
328
329
330
331 OV1_TRIP OV1 trip command
332 OV1-A_TRIP OV1 trip command(Phase-A)
333 OV1-B_TRIP OV1 trip command(Phase-B)
334 OV1-C_TRIP OV1 trip command(Phase-C)
335 OV2_TRIP OV2 trip command
336 OV2-A_TRIP OV2 trip command(Phase-A)
337 OV2-B_TRIP OV2 trip command(Phase-B)
338 OV2-C_TRIP OV2 trip command(Phase-C)
339
340
341 UV1_TRIP UV1 trip command
342 UV1-A_TRIP UV1 trip command(Phase-A)
343 UV1-B_TRIP UV1 trip command(Phase-B)
344 UV1-C_TRIP UV1 trip command(Phase-C)
345 UV2_TRIP UV2 trip command
346 UV2-A_TRIP UV2 trip command(Phase-A)
347 UV2-B_TRIP UV2 trip command(Phase-B)
348 UV2-C_TRIP UV2 trip command(Phase-C)
349
350
351
352
353
354
355 FRQ_TRIP FRQ trip command
356 FRQ1_TRIP FRQ1 trip command
357 FRQ2_TRIP FRQ2 trip command
358
359
360 DFRQ1_TRIP DFRQ1 trip command
361 DFRQ2_TRIP DFRQ2 trip command
362
363
364
 205 
6 F 2 T 0 1 7 9

365
366
367
368
369 TRIP-1 1General trip command
370 TRIP-2 2General trip command
371 GEN.TRIP General trip command
372 GEN.TRIP-A General trip command (A Phase)
373 GEN.TRIP-B General trip command (B Phase)
374 GEN.TRIP-C General trip command (C Phase)
375 GEN.TRIP-N General trip command (N Phase)
376
377
378
379
380
381
382
383
384
385
386
387
388
389 CB1_CLOSE CB1 closed status
390 CB1_OPEN CB1 opened status
391 CB2_CLOSE CB2 closed status
392 CB2_OPEN CB2 opened status
393
394 DIF-NBLK-A
395 DIF-NBLK-B
396 DIF-NBLK-C
397 CT-SAT-A CT saturation detector (A-phase)
398 CT-SAT-B CT saturation detector (B-phase)
399 CT-SAT-C CT saturation detector (C-phase)
400 DIF-TP DIFT trip command (DIF or HOC)
401 DIF DIF trip command
402 DIF-A DIF element output (A-phase)
403 DIF-B DIF element output (B-phase)
404 DIF-C DIF element output (C-phase)
405 2f-LOCK Inrush cuurent detector for DIF
406 2f-A Inrush cuurent detector for DIF (A phase)
407 2f-B Inrush cuurent detector for DIF (B phase)
408 2f-C Inrush cuurent detector for DIF (C phase)
409 5f-LOCK 5f detector for DIF
410 5f-A 5f detector for DIF (A phase)
411 5f-B 5f detector for DIF (B phase)
412 5f-C 5f detector for DIF (C phase)
413 HOC HOC trip command
414 HOC-A HOC element output (A phase)
415 HOC-B HOC element output (B phase)
416 HOC-C HOC element output (C phase)
417 DIF1-TRIP DIF trip command 1
 206 
6 F 2 T 0 1 7 9

418 DIF2-TRIP DIF trip command 2
419
420 1REF-TP 1REF operation output
421 1REF 1REF element output
422 1REF1-TRIP 1REF trip command 1
424 2REF-TP 2REF operation command
425 2REF 2REF element output
428
429
430 V/F-TP V/F trip command
431 V/F-T V/F-T (Inverse time) element output
432 V/F-H V/F-H (High-set) element output
433 V/F-A V/F-A (Low-set) element output
434 TV/F-H V/F-H (High-set) timer output
435 TV/F-A V/F-A (Low-set) timer output
436 V/F-ALARM V/F-A trip command
437 V/F1-TRIP V/F trip command 1
438 V/F2-TRIP V/F trip command 2
439 V/F-L V/F-L element output
440 V/F-S V/F
441 V/F-LT V/F-LT element output
442
443 1OC1-OR 1OC1 relay (3PHASE OR)
447 1OC1_INST-OR 1OC1_INST relay (3PHASE OR)
451 1OC1-IDMT-OR 1OC1-IDMT relay (3PHASE OR)
455 CBF1-OR CBF1 relay (3PHASE OR)
456 CBF2-OR CBF2 relay (3PHASE OR)
457 OV1-OR OV1 relay (3PHASE OR)
458 OV2-OR OV2 relay (3PHASE OR)
459
460 OV1_INST-OR OV1_INST relay (3PHASE OR)
461
462 UV1-OR UV1 relay (3PHASE OR)
463 UV2-OR UV2 relay (3PHASE OR)
464
465
466 UV1_INST-OR UV1_INST relay (3PHASE OR)
467
468 ICD1-OR ICD1 (3PHASE OR)
469 ICD2-OR ICD2 (3PHASE OR)
470
 207 
6 F 2 T 0 1 7 9

471 BO1_OP Binary output 1
487
488
489
490 M.1-1-TRIP Mechanical Trip1-1
498
499
500 DIFT-DIF-TRIP DIFT-DIF TP
501 DIFT-HOC-TRIP DIFT-HOC TP
502 DIFT-TRIP DIFT TRIP
503 1REF-TRIP 1REF TRIP
504 2REF-TRIP 2REF TRIP
505 V/F-TRIP V/F TRIP
506 V/F-L-TRIP V/F-L TRIP
507 V/F-H-TRIP V/F-H TRIP
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
 208 
6 F 2 T 0 1 7 9

524
525
526
527
528
529
530
531
532 1OC1-A_RST 1OC1-A relay element definite time reset
533 1OC1-B_RST 1OC1-B relay element definite time reset
534 1OC1-C_RST 1OC1-C relay element definite time reset
544 1EF1_RST 1EF1 relay element definite time reset
548
549
550
551
552 1NOC1_RST 1NOC1 relay element definite time reset
556 OV1-A_RST OV1-A relay element definite time reset
557 OV1-B_RST OV1-B relay element definite time reset
558 OV1-C_RST OV1-C relay element definite time reset
559 UV1-A_RST UV1-A relay element definite time reset
560 UV1-B_RST UV1-B relay element definite time reset
561 UV1-C_RST UV1-C relay element definite time reset
562
563
564
565
566 UVBLK-A UV blocked element operating
567 UVBLK-B UV blocked element operating
568 UVBLK-C UV blocked element operating
569
570 M.1-TRIP Mechanical Trip1
574
575 1REFOC1 1REFOC1 element output
576 1REFOC1-OP 1REFOC1 operation output
 209 
6 F 2 T 0 1 7 9

577 1REFOC1-TRIP 1REFOC1 TRIP
587
588
589
590
591 1OCV-A 1OCV-A element output
592 1OCV-B 1OCV-B element output
593 1OCV-C 1OCV-C element output
594 1OCV_TRIP 1OCV TRIP
595 1OCV-A_TRIP 1OCV TRIP(A phase)
596 1OCV-B_TRIP 1OCV TRIP(B phase)
597 1OCV-C_TRIP 1OCV TRIP(C phase)
598 2OCV-A 2OCV-A element output
599 2OCV-B 2OCV-B element output
600 2OCV-C 2OCV-C element output
601 2OCV_TRIP 2OCV TRIP
602 2OCV-A_TRIP 2OCV TRIP(A phase)
603 2OCV-B_TRIP 2OCV TRIP(B phase)
604 2OCV-C_TRIP 2OCV TRIP(C phase)
605
606 1OCV-OR 1OCV element output
607 2OCV-OR 2OCV element output
608
609
610 1OC1-A_DEPRST 1OC1-A relay element IDMT dependent time reset
611 1OC1-B_DEPRST 1OC1-B relay element IDMT dependent time reset
612 1OC1-C_DEPRST 1OC1-C relay element IDMT dependent time reset
613 1EF1_DEPRST 1EF1 relay element IDMT dependent time reset
614
615 1NOC1_DEPRST 1NOC1 relay element IDMT dependent time reset
620
626
 210 
6 F 2 T 0 1 7 9

632
634
635
636
637
638
639
640 1OCV-A_INST 1OCV-A relay element start
641 1OCV-B_INST 1OCV-B relay element start
642 1OCV-C_INST 1OCV-C relay element start
643 1OCV-A_DEPRST 1OCV-A relay element IDMT dependent time reset
644 1OCV-B_DEPRST 1OCV-B relay element IDMT dependent time reset
645 1OCV-C_DEPRST 1OCV-C relay element IDMT dependent time reset
646 1OCV-A_DEFRST 1OCV-A relay element IDMT definite time reset
647 1OCV-B_DEFRST 1OCV-B relay element IDMT definite time reset
648 1OCV-C_DEFRST 1OCV-C relay element IDMT definite time reset
649 2OCV-A_INST 2OCV-A relay element start
650 2OCV-B_INST 2OCV-B relay element start
651 2OCV-C_INST 2OCV-C relay element start
652 2OCV-A_DEPRST 2OCV-A relay element IDMT dependent time reset
653 2OCV-B_DEPRST 2OCV-B relay element IDMT dependent time reset
654 2OCV-C_DEPRST 2OCV-C relay element IDMT dependent time reset
655 2OCV-A_DEFRST 2OCV-A relay element IDMT definite time reset
656 2OCV-B_DEFRST 2OCV-B relay element IDMT definite time reset
657 2OCV-C_DEFRST 2OCV-C relay element IDMT definite time reset
658
659
660
661
662
663
664
665
666
667
668
669
670
750
751
752
753
754
755
756
757
758
759
 211 
6 F 2 T 0 1 7 9

760
761
762
763
764
765
766
767
768 BI1_COMMAND Binary input signal BI1
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800 E_FAULT_L1 A phase earth fault signal for IEC103
801 E_FAULT_L2 B phase earth fault signal for IEC103
802 E_FAULT_L3 C phase earth fault signal for IEC103
803
804
805 PICKUP_L1 A phase element pick-up for IEC103
806 PICKUP_L2 B phase element pick-up for IEC103
807 PICKUP_L3 C phase element pick-up for IEC103
808
809
810
811
812
 212 
6 F 2 T 0 1 7 9

813
814
815
816
817
818 CBF_TP_RETP CBF trip or CBF retrip for IEC103
819
820
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040 FAULT_PHA_A fault_phase_A
1041 FAULT_PHA_B fault_phase_B
1042 FAULT_PHA_C fault_phase_C
1043 FAULT_PHA_N fault_phase_N
1044
1045
1046
1047
1048
1049
1050
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241 IEC_MDBLK monitor direction blocked
1242 IEC_TESTMODE IEC61870-5-103 testmode
1243 GROUP1_ACTIVE group1 active
1244 GROUP2_ACTIVE group2 active
1245
1246
1247
1248
1249
 213 
6 F 2 T 0 1 7 9

1250
1251 RLY_FAIL RELAY FAILURE
1252 RLY_OP_BLK RELAY OUTPUT BLOCK
1253 AMF_OFF SV BLOCK
1254
1255
1256
1257
1258 RELAY_FAIL-A Relay fail output
1259 IEC_RLY_FAIL-A Relay fail output for IEC60870-5-103
1260
1261 TRIP-H Trip signal hold
1262 CT1_ERR_UF CT1 error(unfiltered)
1263 CT2_ERR_UF CT2 error(unfiltered)
1264 V0_ERR_UF V0 error(unfiltered)
1265 V2_ERR_UF V2 error(unfiltered)
1266 CT1_ERR CT1 error
1267 CT2_ERR CT2 error
1268 V0_ERR V0 error
1269 V2_ERR V2 error
1270 TC1SV Trip circuit1 supervision failure
1271 TC2SV Trip circuit2 supervision failure
1272 CB1SV Circuit breaker1 status monitoring failure
1273 CB2SV Circuit breaker2 status monitoring failure
1274 TC1_ALARM Trip counter1 alarm
1275 TC2_ALARM Trip counter2 alarm
1276 OT1_ALARM Operate time1 alarm
1277 OT2_ALARM Operate time2 alarm
1278
1279 GEN_PICKUP General start/pick-up
1280
1281
1282
1283
1284 BI1_COM_UF Binary input signal BI1 (unfiltered)
1302
 214 
6 F 2 T 0 1 7 9

1303
1400
1401 LOCAL_OP_ACT local operation active
1402 REMOTE_OP_ACT remote operation active
1403 NORM_LED_ON IN-SERVICE LED ON
1404 ALM_LED_ON ALARM LED ON
1405 TRIP_LED_ON TRIP LED ON
1406 RYFAIL_LED_ON RELAY FAIL LED ON
1407
1408 PRG_LED_RESET Latched programmable LED RESET
1409 LED_RESET TRIP LED RESET
1410
1411
1412
1413 PROT_COM_ON IEC103 communication command
1414 PRG_LED1_ON PROGRAMMABLE LED1 ON
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430 LCD_IND. VirLCD indication(Virtual LED) command
1431 LCD_IND1. LCD indication1(Virtual LED) command
1432 LCD_IND2. LCD indication2(Virtual LED) command
1433
1434
1435 F.Record_CLR Fault record clear
1436 E.Record_CLR Event record clear
1437 D.Record_CLR Disturbance record clear
1438 Data_Lost Data clear by BU-RAM memory monitoring error
1439 TP_COUNT1_CLR Trip counter1 cleared
1440 TP_COUNT2_CLR Trip counter2 cleared
1441
1442 DEMAND_CLR Demand cleared
1443
1444
1445 PLC_data_CHG PLC data change
1446 IEC103_data_CHG IEC-103 data change
1447 IEC850_data_CHG IEC-850 data change
1448 Sys.set_change System setting change
1449 Rly.set_change Relay setting change
 215 
6 F 2 T 0 1 7 9

1450 Grp.set_change Group setting change
1451
1452
1453
1454
1455
1456 KEY-VIEW VIEW key status (1:pressed)
1457 KEY-RESET RESET key status (2:pressed)
1458 KEY-ENTER ENTER key status (3:pressed)
1459 KEY-END END key status (4:pressed)
1460 KEY-CANCEL CANCEL key status (5:pressed)
1461
1462
1463
1464
1465
1466 RTC_err RTC stopped
1467
1468
1469
1470 PLC_err PLC stopeed
1471
1472 SUM_err Program ROM checksum error
1473
1474 SRAM_err SRAM memory monitoring error
1475 BU_RAM_err BU-RAM memory monitoring error
1476
1477 EEPROM_err EEPROM memory monitoring error
1478
1479 A/D_err A/D accuracy checking error
1480 CPU_err Program error
1481
1482 Tsk_run_err Tsk stopped
1483 Sampling_err Sampling error
1484 DIO1_err DIO1 card connection error
1485 DIO2_err DIO2 card connection error
1486
1487 ROM_data_err 8M Romdata error
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500 Set._LOCAL Setting LOCAl
1501 Set._REMOTE Setting REMOTE
1502 LOCAL_OP_CMD1 LOCAL OPEN COMMAND1
 216 
6 F 2 T 0 1 7 9

1503 LOCAL_CL_CMD1 LOCAL CLOSE COMMAND1
1504 RMT_OP_CMD1_B REMOTE OPEN COMMAND1(BI)
1505 RMT_CL_CMD1_B REMOTE CLOSE COMMAND1(BI)
1506 RMT_OP_CMD1_C REMOTE OPEN COMMAND1(COMM)
1507 RMT_CL_CMD1_C REMOTE CLOSE COMMAND1(COMM)
1508 CTRL_LOCK1_B CONTROL LOCK1(BI)
1509 CTRL_LOCK1_C CONTROL LOCK1(COMM)
1510 CB1_OPEN_OP CB1 OPEN OPERATE
1511 CB1_CLOSE_OP CB1 CLOSE OPERATE
1512 LOCAL_OP_CMD2 LOCAL OPEN COMMAND2
1513 LOCAL_CL_CMD2 LOCAL CLOSE COMMAND2
1514 RMT_OP_CMD2_B REMOTE OPEN COMMAND2(BI)
1515 RMT_CL_CMD2_B REMOTE CLOSE COMMAND2(BI)
1516 RMT_OP_CMD2_C REMOTE OPEN COMMAND2(COMM)
1517 RMT_CL_CMD2_C REMOTE CLOSE COMMAND2(COMM)
1518 CTRL_LOCK2_B CONTROL LOCK2(BI)
1519 CTRL_LOCK2_C CONTROL LOCK2(COMM)
1520 CB2_OPEN_OP CB2 OPEN OPERATE
1521 CB2_CLOSE_OP CB2 CLOSE OPERATE
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536 1OC1_BLOCK OC trip block command
1537 1OC2_BLOCK ditto
1540
1541
1542
1543
1544 1EF1_BLOCK EF trip block command
1545 1EF2_BLOCK ditto
1548
1549
1550
1551
1552
1553
1554
 217 
6 F 2 T 0 1 7 9

1555
1556
1557
1558
1559
1560 1NOC1_BLOCK NOC trip block command
1561 1NOC2_BLOCK ditto
1564
1565
1566
1567
1568
1569
1570 CBF1_BLOCK CBF1 trip block command
1571 CBF2_BLOCK CBF2 trip block command
1572 THM_BLOCK THM trip block command
1573 THMA_BLOCK ditto
1574
1575
1576 DFRQ1_BLOCK DFRQ trip block command
1577 DFRQ2_BLOCK ditto
1578
1579 DIF_BLOCK
1580 1REF_BLOCK
1581 2REF_BLOCK
1582 V/F_BLOCK
1583 V/F-A_BLOCK
1584 OV1_BLOCK OV trip block command
1585 OV2_BLOCK ditto
1586
1587
1588 UV1_BLOCK UV trip block command
1589 UV2_BLOCK ditto
1590
1591
1592 1OCV_BLOCK
1593 2OCV_BLOCK
1594
1595
1596
1597
1598
1599
1600 FRQ1_BLOCK FRQ trip block command
1601 FRQ2_BLOCK ditto
1602
1603
1604
1605
 218 
6 F 2 T 0 1 7 9

1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628 EXT_TRIP-A External trip commamd (A Phase)
1629 EXT_TRIP-B External trip commamd (B Phase)
1630 EXT_TRIP-C External trip commamd (C Phase)
1631 EXT_TRIP External trip commamd
1632 TC1_FAIL Trip circuit1 Fail Alarm commamd
1633 CB1_N/O_CONT CB1 N/O contact commamd
1634 CB1_N/C_CONT CB1 N/C contact commamd
1635 TC2_FAIL Trip circuit2 Fail Alarm commamd
1636 CB2_N/O_CONT CB2 N/O contact commamd
1637 CB2_N/C_CONT CB2 N/C contact commamd
1638
1639 IND.RESET Indication reset command
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656 CBF1_INIT-A CBF1 initiation command (Phase A)
 219 
6 F 2 T 0 1 7 9

1657 CBF1_INIT-B ditto
1658 CBF1_INIT-C ditto
1659 CBF1_INIT CBF1 initiation command
1660 CBF2_INIT-A CBF2 initiation command (Phase A)
1661 CBF2_INIT-B ditto
1662 CBF2_INIT-C ditto
1663 CBF2_INIT CBF2 initiation command
1664 TP1_COUNT-A Trip counter count up command
1665 TP1_COUNT-B ditto
1666 TP1_COUNT-C ditto
1667 TP1_COUNT ditto
1668 TP2_COUNT-A Trip counter count up command
1669 TP2_COUNT-B ditto
1670 TP2_COUNT-C ditto
1671 TP2_COUNT ditto
1672
1673 OT1_ALARM-A Operating1 alarm start commnad
1674 OT1_ALARM-B ditto
1675 OT1_ALARM-C ditto
1676 OT2_ALARM-A Operating2 alarm start commnad
1677 OT2_ALARM-B ditto
1678 OT2_ALARM-C ditto
1679
1680 FRQ_S1_TRIP Frequency scheme trip command (Stage1)
1681 FRQ_S2_TRIP Frequency scheme trip command (Stage2)
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696 DIF-A_BLOCK DIF-A trip block command
1697 DIF-B_BLOCK ditto
1698 DIF-C_BLOCK ditto
1699
1700 EXT-MEC.TP1 External Mechanical TRIP1
1701 EXT-MEC.TP2 ditto
1704 MEC.TP1-BLK Mechanical trip1 block command
1705 MEC.TP2-BLK ditto
 220 
6 F 2 T 0 1 7 9

1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
2300
2301
2302
2303
CONTROL_LOCK1_B
2304 CONTROL LOCK1(BI)
I
2305 REMOTE_OP_CMD1 REMOTE OPEN COMMAND1
2306 REMOTE_CL_CMD1 REMOTE CLOSE COMMAND1
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
CONTROL_LOCK2_B
2320 CONTROL LOCK2(BI)
I
2321 REMOTE_OP_CMD2 REMOTE OPEN COMMAND2
2322 REMOTE_CL_CMD2 REMOTE CLOSE COMMAND2
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
 221 
6 F 2 T 0 1 7 9

2334
2335
2336
2337
2338
2339
2340
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560 DISP.ALARM1 Indicate the alarm display
2561 DISP.ALARM2 ditto
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576 SYNC_CLOCK Synchronise clock commamd
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
 222 
6 F 2 T 0 1 7 9

2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610 ALARM_LED_SET Alarm LED set
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624 F.RECORD1 Fault record stored command 1
2628
2629 EVENT1
2630 EVENT2
2631 EVENT3
2632 D.RECORD1 Disturbance record stored command 1
2636
2637
2638
2639
2640 SET.GROUP1 Active setting group changed command (Change to group1)
2641 SET.GROUP2 Active setting group changed command (Change to group2)
2642
 223 
6 F 2 T 0 1 7 9

2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656 CON_TPMD1 User configurable trip mode in fault record
2657 CON_TPMD2 ditto
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686 PROT_COM_RECV Protection inactivate command received
2687
2688 TPLED_RST_RECV TRIP LED reset command received
2689
2690 OP_CMD1_RECV CB1 open command received
2691 CL_CMD1_RECV CB1 close command received
2692 LOCK_CMD1_RECV CB1 control lock command received
2693 OP_ENABLE CB1,CB2 operation enable
 224 
6 F 2 T 0 1 7 9

2694 OP_CMD2_RECV CB2 open command received
2695 CL_CMD2_RECV CB2 close command received
2696 LOCK_CMD2_RECV CB2 control lock command received
2697
2698
2699
2700
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816 TEMP001
2817 TEMP002
2818 TEMP003
2819 TEMP004
2820 TEMP005
2821 TEMP006
2822 TEMP007
2823 TEMP008
2824 TEMP009
2825 TEMP010
2826 TEMP011
2827 TEMP012
2828 TEMP013
2829 TEMP014
2830 TEMP015
2831 TEMP016
2832 TEMP017
2833 TEMP018
2834 TEMP019
2835 TEMP020
2836 TEMP021
2837 TEMP022
2838 TEMP023
2839 TEMP024
2840 TEMP025
2841 TEMP026
 225 
6 F 2 T 0 1 7 9

2842 TEMP027
2843 TEMP028
2844 TEMP029
2845 TEMP030
2846 TEMP031
2847 TEMP032
2848 TEMP033
2849 TEMP034
2850 TEMP035
2851 TEMP036
2852 TEMP037
2853 TEMP038
2854 TEMP039
2855 TEMP040
2856 TEMP041
2857 TEMP042
2858 TEMP043
2859 TEMP044
2860 TEMP045
2861 TEMP046
2862 TEMP047
2863 TEMP048
2864 TEMP049
2865 TEMP050
2866 TEMP051
2867 TEMP052
2868 TEMP053
2869 TEMP054
2870 TEMP055
2871 TEMP056
2872 TEMP057
2873 TEMP058
2874 TEMP059
2875 TEMP060
2876 TEMP061
2877 TEMP062
2878 TEMP063
2879 TEMP064
2880 TEMP065
2881 TEMP066
2882 TEMP067
2883 TEMP068
2884 TEMP069
2885 TEMP070
2886 TEMP071
2887 TEMP072
2888 TEMP073
2889 TEMP074
2890 TEMP075
2891 TEMP076
2892 TEMP077
 226 
6 F 2 T 0 1 7 9

2893 TEMP078
2894 TEMP079
2895 TEMP080
2896 TEMP081
2897 TEMP082
2898 TEMP083
2899 TEMP084
2900 TEMP085
2901 TEMP086
2902 TEMP087
2903 TEMP088
2904 TEMP089
2905 TEMP090
2906 TEMP091
2907 TEMP092
2908 TEMP093
2909 TEMP094
2910 TEMP095
2911 TEMP096
2912 TEMP097
2913 TEMP098
2914 TEMP099
2915 TEMP100
2916 TEMP101
2917 TEMP102
2918 TEMP103
2919 TEMP104
2920 TEMP105
2921 TEMP106
2922 TEMP107
2923 TEMP108
2924 TEMP109
2925 TEMP110
2926 TEMP111
2927 TEMP112
2928 TEMP113
2929 TEMP114
2930 TEMP115
2931 TEMP116
2932 TEMP117
2933 TEMP118
2934 TEMP119
2935 TEMP120
2936 TEMP121
2937 TEMP122
2938 TEMP123
2939 TEMP124
2940 TEMP125
2941 TEMP126
2942 TEMP127
2943 TEMP128
 227 
6 F 2 T 0 1 7 9

2944 TEMP129
2945 TEMP130
2946 TEMP131
2947 TEMP132
2948 TEMP133
2949 TEMP134
2950 TEMP135
2951 TEMP136
2952 TEMP137
2953 TEMP138
2954 TEMP139
2955 TEMP140
2956 TEMP141
2957 TEMP142
2958 TEMP143
2959 TEMP144
2960 TEMP145
2961 TEMP146
2962 TEMP147
2963 TEMP148
2964 TEMP149
2965 TEMP150
2966 TEMP151
2967 TEMP152
2968 TEMP153
2969 TEMP154
2970 TEMP155
2971 TEMP156
2972 TEMP157
2973 TEMP158
2974 TEMP159
2975 TEMP160
2976 TEMP161
2977 TEMP162
2978 TEMP163
2979 TEMP164
2980 TEMP165
2981 TEMP166
2982 TEMP167
2983 TEMP168
2984 TEMP169
2985 TEMP170
2986 TEMP171
2987 TEMP172
2988 TEMP173
2989 TEMP174
2990 TEMP175
2991 TEMP176
2992 TEMP177
2993 TEMP178
2994 TEMP179
 228 
6 F 2 T 0 1 7 9

2995 TEMP180
2996 TEMP181
2997 TEMP182
2998 TEMP183
2999 TEMP184
3000 TEMP185
3001 TEMP186
3002 TEMP187
3003 TEMP188
3004 TEMP189
3005 TEMP190
3006 TEMP191
3007 TEMP192
3008 TEMP193
3009 TEMP194
3010 TEMP195
3011 TEMP196
3012 TEMP197
3013 TEMP198
3014 TEMP199
3015 TEMP200
3016 TEMP201
3017 TEMP202
3018 TEMP203
3019 TEMP204
3020 TEMP205
3021 TEMP206
3022 TEMP207
3023 TEMP208
3024 TEMP209
3025 TEMP210
3026 TEMP211
3027 TEMP212
3028 TEMP213
3029 TEMP214
3030 TEMP215
3031 TEMP216
3032 TEMP217
3033 TEMP218
3034 TEMP219
3035 TEMP220
3036 TEMP221
3037 TEMP222
3038 TEMP223
3039 TEMP224
3040 TEMP225
3041 TEMP226
3042 TEMP227
3043 TEMP228
3044 TEMP229
3045 TEMP230
 229 
6 F 2 T 0 1 7 9

3046 TEMP231
3047 TEMP232
3048 TEMP233
3049 TEMP234
3050 TEMP235
3051 TEMP236
3052 TEMP237
3053 TEMP238
3054 TEMP239
3055 TEMP240
3056 TEMP241
3057 TEMP242
3058 TEMP243
3059 TEMP244
3060 TEMP245
3061 TEMP246
3062 TEMP247
3063 TEMP248
3064 TEMP249
3065 TEMP250
3066 TEMP251
3067 TEMP252
3068 TEMP253
3069 TEMP254
3070 TEMP255
3071 TEMP256
 230 
6 F 2 T 0 1 7 9
Appendix C
Programmable Reset Characteristics
 231 
6 F 2 T 0 1 7 9
Programmable Reset Characteristics

The overcurrent stages for phase and earth faults, OC and EF, each have a programmable reset feature.
Resetting may be instantaneous, definite time delayed, or, in the case of IEEE/US curves, inverse time
delayed.
Instantaneous resetting is normally applied in multi-shot auto-reclosing schemes, to ensure correct grading
between relays at various points in the scheme. On the other hand, the inverse reset characteristic is
particularly useful to provide correct co-ordination with an upstream induction disc type overcurrent relay.
The definite time delayed reset characteristic may be used to provide faster clearance of intermittent
(‘pecking’ or ‘flashing’) fault conditions. An example of where such phenomena may be experienced is in
plastic insulated cables, where the fault energy melts the cable insulation and temporarily extinguishes the
fault, after which the insulation again breaks down and the process repeats.
An inverse time overcurrent protection with instantaneous resetting cannot detect this condition until the
fault becomes permanent, thereby allowing a succession of such breakdowns to occur, with associated
damage to plant and danger to personnel. If a definite time reset delay of, for example, 60 seconds is applied,
on the other hand, the inverse time element does not reset immediately after each successive fault
occurrence. Instead, with each new fault inception, it continues to integrate from the point reached during
the previous breakdown, and therefore operates before the condition becomes permanent. Figure A-1
illustrates this theory.
Intermittent
Fault Condition
TRIP LEVEL
Inverse Time Relay

with Instantaneous
Reset
RX
RX
Inverse Time Relay

with Definite Time
Reset
Delayed Reset
Figure B-1
 232 
6 F 2 T 0 1 7 9
Appendix D
Binary Output Default Setting List
 233 
6 F 2 T 0 1 7 9
Relay BO Terminal Signal Contents Setting

Model No. No. Name
Signal No. Logic Reset
(OR:0, (Inst:0, Del:1
AND:1) DW:2 Latch:3)
TB6:
GRE160 BO1 1-2 NON Off (Link to CB1 Close SW) 0 0 1
-100 BO2 3-4 GENERAL TRIP Relay trip (General) 371 0 1
-200 TB5 (Link to CB1 Open SW)
-300 BO3 11 – 12 NON Off (Link to CB2 Close SW) 0 0 1
-400 BO4 13 – 14 GENERAL TRIP Relay trip (General) 371 0 1
R.F. 9 - 10 Relay fail
TB6:
-301 BO3 11 – 12 NON Off (Link to CB2 Close SW) 0 0 1
-401 BO4 13 – 14 GENERAL TRIP Relay trip (General) 371 0 1
R.F. 9 - 10 Relay fail
TB1:
BO5 1–2 GENERAL TRIP Relay trip (General) 371 0 1
BO7 5–6 NON Off 0 0 1
BO8 7–8 NON Off 0 0 1
BO9 9 – 10 NON Off 0 0 1
BO10 11 – 12 NON Off 0 0 1
TB6:
-302 BO3 11 – 12 GENERAL ALARM Off (Link to CB2 Close SW) 371 0 1
-402 BO4 13 – 14 NON Relay trip (General) 0 0 1
R.F. 9 – 10 Relay fail
TB1:
BO7 5–6 NON Off 0 0 1
BO8 7–8 NON Off 0 0 1
BO9 9 – 10 NON Off 0 0 1
BO10 11 – 12 NON Off 0 0 1
TB3;
BO11 1–2 NON Off 0 0 1
BO12 3–4 NON Off 0 0 1
BO13 5–6 NON Off 0 0 1
BO14 7–8 NON Off 0 0 1
BO15 9 – 10 GENERAL TRIP Relay trip (General) 371 0 1
BO16 11 – 12 GENERAL TRIP Relay trip (General) 371 0 1
 234 
6 F 2 T 0 1 7 9
Appendix E
Details of Relay Menu and
LCD & Keypad Operation
 235 
6 F 2 T 0 1 7 9
MAIN MENU
Record
Status
Set. (view)
Set. (change)
Control
Test
/1 Record
Fault
Event
Disturbance
Counter
/2 Fault /3 Fault /4 Fault #1

View record 16/Jul/2012
Clear #1 16/Jul/2012 18:13:57.031
18:13:57.031 DIFT
Refer to Section
4.2.3.1. Phase ABC
Clear records?
END=Y CANCEL=N
/2 Event /3 Event
View record
Clear 16/Jul/2012 480
DIFT trip On
Refer to Section
4.2.3.2.
Clear records?
END=Y CANCEL=N
/2 Disturbance /3 Disturbance
View record
Clear #1 16/Jul/2012
18:13:57.401
Refer to Section
4.2.3.3.
Clear records?
END=Y CANCEL=N
a-1 b-1
 236 
6 F 2 T 0 1 7 9
a-1 b-1
/2 Counter /3 Counter
View record Trips1 *****
Clear Trips Trips1 A *****
Clear Trips A Trips1 B *****
Clear Trips B Trips1 C *****
Clear Trips C Trips2 *****
Trips2 A *****
Refer to Section Trips2 B *****
4.2.3.4. Trips2 C *****
Clear Trips1?
END=Y CANCEL=N
Clear Trips1 A?
END=Y CANCEL=N
Clear Trips1 B?
END=Y CANCEL=N
Clear Trips1 C?
END=Y CANCEL=N
Clear Trips2?
END=Y CANCEL=N
Clear Trips2 A?
END=Y CANCEL=N
Clear Trips2 B?
END=Y CANCEL=N
Clear Trips2 C?
END=Y CANCEL=N
a-1
 237 
6 F 2 T 0 1 7 9
a-1
/1 Status /2 Metering /3 Metering

Metering Metering Ia1 **.** kA
Binary I/O Demand
Relay element /3 Demand
Time sync. Ia1max **.** kA
Clock adjust. /2 Binary I/O
LCD contrast IP [0000 00 ]
Refer to Section 4.2.4.
/2 Ry element
DIF#1[000000000]
/2 Time sync.
*BI: Act.
/2 12/Nov/2012
22:56:19 [L]
/2 LCD contrast
/1 Set. (view)
Version
Description
Comms
Record
Status
Protection
Binary I/P
Binary O/P Refer to Section 4.2.5
LED
/2 Version GRE160-400A-10
Relay type -10
Software
Main Software
GSP***-06-*
/2 Description
Plant name
∗∗∗∗∗∗∗∗∗∗∗∗∗∗
Description
Alarm1 Text ∗∗∗∗∗∗
Alarm2 Text
/2 Comms /3 Addr.
Addr. Modbus 2
Switch
/3 Switch
RS485BR 1
a-1, b-1
 238 
6 F 2 T 0 1 7 9
a-1 b-1
/2 Record
Fault
Disturbance
Counter
/3 Fault
Phase mode
/3 Disturbance /4 Time/starter
Time/starter Time1 2.0s
Scheme sw
/4 Scheme sw
TRIP1 0
/3 Counter /4 Scheme sw
Scheme sw TC1SPEN
Alarm set
/4 Alarm set
TC1ALM 10000
/2 Status /3 Metering
Metering Display 1
Time sync.
/3 Time sync.
Time sync 0
/2 Act. gp. =*
Common
Group1
Group2
/3 Common
APPLCT 1
/3 Group1
Parameter
Trip
a-1 b-1 c-1 d-1
 239 
6 F 2 T 0 1 7 9
a-1 b-1 c-1 d-1
/4 Parameter ∗∗∗∗∗∗∗∗∗∗∗∗∗∗
Line name ∗∗∗∗∗∗
CT/VT ratio
/5 CT/VT ratio
1CT 400
/6 Application
M1OC1 0
/4 Trip
Scheme sw /6 DIF prot.
Prot.element DIFEN 1
/5 Scheme sw /6 REF prot.

Application 1REFSCHEME 1
DIF prot.
REF prot. /6 V/f prot.
V/f prot. V/f EN 1
OC. prot.
EF prot. /6 OC prot.
NOC prot. 1OC1EN 1
Misc prot.
/6 EF prot.
OV prot.
1EF1EN 1
UV prot.
FRQ prot.
/6 NOC prot.
M.Trip
1NC1EN 1
/6 Misc prot.
OCV3PH 1
/6 OV prot.
OV1EN 1
/6 UV prot.
UV1EN 1
/6 FRQ prot.
FRQ1EN 1
/6 M.Trip
M.T1-1 1
a-1 b-1 C-1 e-1
 240 
6 F 2 T 0 1 7 9
a-1 b-1 c-1 e-1

/6 DIF prot.
ik 1.00pu
/6 Prot.element /6 REF prot.

DIF prot. 1ik 2.50pu
REF prot.
V/f prot. /6 V/f prot.
V 120.0V
OC prot.
EF prot. /6 OC prot.
NOC prot. 1OC1 5.00pu
Misc prot.
OV prot. /6 EF prot.
UV prot. 1EF1 5.00pu
FRQ prot.
/6 NOC prot.
1NC1 5.00pu
/6 Misc prot.
OCV1 120.0V
/6 OV prot.
OV1 120.0V
/6 UV prot.
UV1 80.0V
/6 FRQ prot.
FRQ1 -10.00Hz
a-1 b-1 C-1
 241 
6 F 2 T 0 1 7 9
a-1 b-1 c-1
/3 Group2
Parameter
/2 Binary I/P /3 BI Status

BI Status BITHR1 0
BI1
BI2 /3 BI1 /4 Timers
Timer BI1PUD 0.00s
Functions
/4 Functions
BI1SNS 0
/2 Binary O/P
BO1 AND, INS
∗∗∗∗, ∗∗∗∗, ∗∗∗∗
BO2 AND, INS
∗∗∗∗, ∗∗∗∗, ∗∗∗∗
BO16 OR, L
∗∗∗∗, ∗∗∗∗, ∗∗∗∗
TBO1 0.20s
TBO16 0.20s
/2 LED /3 LED
LED LED1 OR, I R
Virtual LED
/3 Virtual LED /4 LED1
IND1 BIT1 I,O
IND2
/4 LED2
/2 Control BIT1 I,O
Control 0
Interlock
/2 Frequency
a-1 b-1
 242 
6 F 2 T 0 1 7 9
a-1
/1 Set.(change)
Password : Password trap
Description Password [_ ]
Comms 1234567890←
Record : Confirmation trap
Status Change settings?

Protection ENTER=Y CANCEL=N
Binary I/P
Binary O/P
LED
Control
Frequency
Set.(change) Set.(change)
Input [_ ] Retype [_ ]
1234567890← 1234567890←
Refer to Section 4.2.6.2.
/2 Description _
Plant name ABCDEFG
Description
Alarm1 Text _
: ABCDEFG
Alarm4 Text
/3 Addr.
/2 Comms
Addr.
/3 Switch
Switch
Refer to Section
4.2.6.4.
/2 Record /3 Fault
Fault Phase mode
Disturbance
Counter /3 Disturbance /4 Time/starter
Time/starter
Refer to Section
4.2.6.5. Scheme sw
/4 Scheme sw
/3 Counter /4 Scheme sw
Scheme sw
Alarm set
/4 Alarm set
a-1 b-2
 243 
6 F 2 T 0 1 7 9
a-1 b-2
/2 Status /3 Metering
Metering
Time sync.
/3 Time sync.
/2 Protection
Change act. gp.
Change set.
Refer to Section
Copy gp. 4.2.6.7.
/3 Change act.
gp.
/3 Act gp.=1
Common
Group1
Group2
/4 Common
/4 Group1
Parameter
Trip
/5 Parameter _
Line name ABCDEFG
CT/VT ratio
/6 CT/VT ratio
a 1 b 2 c 2 d 2 e 2
 244 
6 F 2 T 0 1 7 9
/5 Trip
Scheme sw
Prot.element
/6 Scheme sw /7 Application
Application
DIF prot.
REF prot. /7 DIF prot.
V/f prot.
OC prot.
EF prot. /7 REF prot.
NOC prot.
Misc prot.
OV prot. /7 V/f prot.
UV prot.
FRQ prot. /7 OC prot.
M.Trip
/7 EF prot.
/7 NOC prot.
/7 Misc prot.
/7 OV prot.
/7 UV prot.
/7 FRQ prot.
/7 M.Trip
 245 
6 F 2 T 0 1 7 9
a-1 b-2 c-2 d-2
/4 Group2
Parameter
/3 Copy A to B
A _
B _
/2 Binary I/P /3 BI1 /4 Timers

BI1 Timers
BI2 Functions
BI3 /4 Functions
BI4
/3 BI*
BI17 Timers
BI18 Functions
/2 Binary O/P /3 BO1 /4 Logic/Reset

BO1 Logic/Reset
BO2 Functions
/4 Functions
/3 BO16
BO15 Logic/Reset
BO16 Functions
Refer to Section
4.2.6.9.
/2 LED
LED
Refer to Section
Virtual LED 4.2.6.10.
/3 LED /4 LED1 /5 Logic/Reset

LED1
Logic/Reset
Functions /5 Functions
LED6
CB CLOSED /4 LED6
Logic/Reset /5 LED Color
/4 CB CLOSED /5 LED Color

a-1 b-2 c-3
LED Color
 246 
6 F 2 T 0 1 7 9
a-1 b-2 c-3
/3 Virtual LED /4 IND1 /5 Reset

IND1 Reset
IND2 Functions
/5 Functions
/2 Control
/4 IND2
Control 1
Disable/Enable Reset
Interlock1 0 Functions
Disable/Enable
Interlock2 0
Disable/Enable
/2 Frequency
Frequency 0
50Hz/60Hz
/1 Control Control Control

Password(Ctrl) Input [_ ] Retype [_ ]
Local/Remote 1234567890← 1234567890←
CB1 close/open
CB2 close/open
/1 Test Test Test

Password(Test) Input [_ ] Retype [_ ]
Switch 1234567890← 1234567890←
Binary O/P
Refer to Section 4.2.7. /2 Switch
: Password trap A M F 1
Password [_ ] /2 Binary O/P Operate?
1234567890← ENTER=Y CANCEL=N
 247 
6 F 2 T 0 1 7 9
Appendix F
Case Outline
 248 
6 F 2 T 0 1 7 9
177
298
17 127 36
Front View Side View
160
292
　ｆor Optional 4 holes-φ4
Communication Port
Rear View 　ｆor Panel mount Jig
Panel cut-out
TB6 TB5 TB4 TB3 TB2 TB1

1 2
3 4 1 2 1 2 1 2 1 2 1 2
3 4 3 4
5 6 3 4 3 4 3 4
7 8 5 6 5 6
5 6 5 6 7 8 5 6 7 8
9 10
11 12 7 8 7 8 9 10 7 8 9 10
13 14 9 10 9 10 11 12 9 10 11 12
11 　 12 11 　 12 13 14 13 14
15 16
15 16
11 12
17 18 13　　14 13　　14 15 16
17 18 13　 14 17 18
19 20 15　　16 15　　16
21 22 19 20 19 20
23 24 21 22 21 22
23 24 23 24
for Communication Port
Terminal block
Case Outline
 249 
6 F 2 T 0 1 7 9
Appendix G
External Connections
 250 
6 F 2 T 0 1 7 9
GRE160 – 102A
*BO7 to BO10 and BO13 to BO16 are NOT applicable for direct CB coil connection.
**Analogue current input ports are shorted when the terminal block is removed.
(1-2, 3-4, 5-6)
Typical External Connection of GRE160 – 102A
 251 
6 F 2 T 0 1 7 9
GRE160 – 201A
*BO7 to BO10 are NOT applicable for direct CB coil connection.

(1-2, 3-4, 5-6, 7-8)
 252 
6 F 2 T 0 1 7 9
GRE160 – 302A
*BO7 to BO10 and BO13 to BO16 are NOT applicable for direct CB coil connection.
(1-2, 3-4, 5-6)
 253 
6 F 2 T 0 1 7 9
GRE160 – 401A
*BO7 to BO10 are NOT applicable for direct CB coil connection.

(1-2, 3-4, 5-6, 7-8)
 254 
6 F 2 T 0 1 7 9
GRE160 – 500A
(1-2, 3-4, 5-6, 7-8)
 255 
6 F 2 T 0 1 7 9
Appendix H
Relay Setting Sheet
1. Relay Identification
2. Contacts Setting
3. Relay and Protection Scheme Setting Sheet
 256 
6 F 2 T 0 1 7 9
Relay Setting Sheets

1. Relay Identification Date:
Relay type Serial Number
Frequency CT rating
VT rating dc supply voltage
Password Active setting group
2. Contacts Setting
(1) BO BO1
BO2
BO3
BO4
BO5
BO6
BO7
BO8
BO9
BO10
BO11
BO12
BO13
BO14
BO15
BO16
(2) BI BI1
BI 2
BI 3
BI 4
BI 5
BI 6
BI 7
BI 8
BI 9
BI 10
BI 11
BI 12
BI 13
BI 14
BI 15
BI 16
BI 17
+ BI 18
 257 
6 F 2 T 0 1 7 9
3. Relay and Protection Scheme Setting Sheet
Default Value
No. Name Range Unit Contents
Model Model Model Model Model
100A 200A 300A 400A 500A
1 Active gp. 1-2 － Active setting group 1 1 1 1 1
2 APPLCT Off - On － Application setting of CT On On On On On
3 APPLVT Off - On － Application setting of VT -- -- On On On
4 APPLVE Off - On － Application setting of Ve -- -- -- -- Off
5 CT1 1A - 5A － CT1 Rating 1A 1A 1A 1A 1A
6 CT2 1A - 5A － CT2 Rating 1A 1A 1A 1A 1A
7 CT1POL Object - Outside － CT1 Polarity Object Object Object Object Object
8 CT2POL Object - Outside － CT2 Polarity Object Object Object Object Object
9 CTn1 1A - 5A CTn1 Rating --(1A) 1A --(1A) 1A 1A
10 CTn2 1A - 5A CTn2 Rating --(1A) 1A --(1A) 1A 1A
11 VTLOC pre - sec － Voltage Location --(pre) --(pre) pre pre pre
Off - ALM&BLK - CT1 AC input imbalance Super
12 CT1SVEN － ALM ALM ALM ALM ALM
ALM Visor Enable
Off - ALM&BLK - CT2 AC input imbalance Super
13 CT2SVEN ALM ALM ALM ALM ALM
ALM Visor Enable
Off - ALM&BLK -
14 V0SVEN － V0 Super Visor Enable ALM ALM ALM ALM ALM
ALM
Off - ALM&BLK -
15 V2SVEN － V2 Super Visor Enable ALM ALM ALM ALM ALM
ALM
TRIP LED lighting control at alarm
16 AOLED Off - On － On On On On On
output
18 1CT 1 - 30000 － CT1 ratio 400 400 400 400 400
19 2CT 1 - 30000 － CT2 ratio 400 400 400 400 400
20 1nCT 1 - 30000 － CT1n ratio -- 200 -- 200 200
21 2nCT 1 - 30000 － CT2n ratio -- 200 -- 200 200
22 PVT 1 - 20000 － Phase VT ratio -- -- 100 100 100
23 VEVT 1 - 20000 － Ve VT ratio -- -- -- -- 100
IEC - IEEE –
24 M1OC1 － 1OC1 Delay Type IEC IEC IEC IEC IEC
US - C
IEC - IEEE –
US - C
IEC - IEEE –
US - C
IEC - IEEE –
US - C
IEC - IEEE –
28 M1EF1 － 1EF1 Delay Type IEC IEC IEC IEC IEC
US - C
IEC - IEEE –
US - C
IEC - IEEE –
US - C
IEC - IEEE –
US - C
IEC - IEEE –
32 M1NC1 － 1NOC1 Delay Type IEC IEC IEC IEC IEC
US - C
IEC - IEEE –
US - C
IEC - IEEE –
US - C
IEC - IEEE –
US - C
IEC - IEEE –
36 M1OCV － OCV1 Delay Type -- -- IEC IEC IEC
US - C
IEC - IEEE –
37 M2OCV － OCV2 Delay Type -- -- IEC IEC IEC
US - C
38 DIF DIFEN Off - On － DIF Enable On On On On On
39 DIF HOCEN Off - On － HOC Enable On On On On On
40 DIF DIFEN1 Off - On － DIF1 Enable On On On On On
41 DIF DIFEN2 Off - On － DIF2 Enable On On On On On
DIFT 3POR - 2PAND -
42 DIF － DIF trip mode 2PAND 2PAND 3POR 3POR 3POR
PMD 1P
43 DIF 2f-lock Off - On － 2f restraint On On On On On
 258 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
44 DIF 5f-lock Off - On － 5f restraint On On On On On
45 DIF CTSEN Off - On － On On On On On
1REF
46 REF Low - High － 1REF Scheme -- Low -- Low Low
SCHEME
2REF
47 REF Low - High － 2REF Scheme -- Low -- Low Low
SCHEME
1REF1
48 REF Off - On － 1REF1 Enable -- Off -- Off Off
EN
1REF2
EN
2REF1
EN
2REF2
EN
Directional checking function of
52 REF REFDEF Off - On － -- Off -- Off Off
REF
1REF
53 REF Off - On － 1REFOC1 Enable -- Off -- Off Off
OC1
1REF
OC2
2REF
OC1
2REF
OC2
57 V/f V/FEN1 Off - On － V/F1 Enable -- -- Off Off Off
58 V/f V/FEN2 Off - On － V/F2 Enable -- -- Off Off Off
59 V/f V/FA Off - On － V/F Alarm Enable -- -- Off Off Off
60 OC 1OC1EN Off - On － 1OC1 Enable On On On On On
61 OC 1OCI1EN Off - On － 1OCI1 Enable Off Off Off Off Off
M1OC1C
62 OC NI - VI - EI - LTI － 1OCI1 IEC Inverse Curve Type NI NI NI NI NI
-IEC
M1OC1C
63 OC MI - VI - EI － 1OCI1 IEEE Inverse Curve Type MI MI MI MI MI
-IEEE
M1OC1C
64 OC CO2 - CO8 － 1OCI1 US Inverse Curve Type CO2 CO2 CO2 CO2 CO2
-US
65 OC 1OC1R DEF - DEP － 1OCI1 Reset Characteristic DEF DEF DEF DEF DEF
66 OC 1OC1-2F NA - Block － 1OC1 2f Block Enable NA NA NA NA NA
67 OC 1OC2EN Off - On － 1OC2 Enable Off Off Off Off Off
M1OC2C
-IEC
M1OC2C
-IEEE
M1OC2C
-US
3POR -
74 OC 1OCTP － 1OC trip mode 3POR 3POR 3POR 3POR 3POR
2OUTOF3
75 OC 2OC1EN Off - On － 2OC1 Enable Off Off Off Off Off
M2OC1C
-IEC
M2OC1C
-IEEE
M2OC1C
-US
82 OC 2OC2EN Off - On － 2OC2 Enable On On On On On
M2OC2C
-IEC
M2OC2C
-IEEE
M2OC2C
-US
 259 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
3POR -
89 OC 2OCTP － 2OC trip mode 3POR 3POR 3POR 3POR 3POR
2OUTOF3
90 EF 1EF1EN Off - On - POP － 1EF1 Enable On On On On On
91 EF 1EFI1EN Off - On - POP － 1EFI1 Enable Off Off Off Off Off
M1EF1C-
92 EF NI - VI - EI - LTI － 1EFI1 IEC Inverse Curve Type NI NI NI NI NI
IEC
M1EF1C-
93 EF MI - VI - EI － 1EFI1 IEEE Inverse Curve Type MI MI MI MI MI
IEEE
M1EF1C-
94 EF CO2 - CO8 － 1EFI1 US Inverse Curve Type CO2 CO2 CO2 CO2 CO2
US
95 EF 1EF1R DEF - DEP － 1EFI1 Reset Characteristic DEF DEF DEF DEF DEF
96 EF 1EF1-2F NA - Block － 1EF1 2f Block Enable NA NA NA NA NA
97 EF 1EF2EN Off - On - POP － 1EF2 Enable Off Off Off Off Off
M1EF2C-
IEC
M1EF2C-
IEEE
M1EF2C-
US
104 EF 2EF1EN Off - On - POP － 2EF1 Enable Off Off Off Off Off
M2EF1C-
IEC
M2EF1C-
IEEE
M2EF1C-
US
111 EF 2EF2EN Off - On - POP － 2EF2 Enable On On On On On
M2EF2C-
IEC
M2EF2C-
IEEE
M2EF2C-
US
118 NOC 1NC1EN Off - On － 1NC1 Enable Off Off Off Off Off
119 NOC 1NCI1EN Off - On － 1NCI1 Enable Off Off Off Off Off
M1NC1C
120 NOC NI - VI - EI - LTI － 1NCI1 IEC Inverse Curve Type NI NI NI NI NI
-IEC
M1NC1C
121 NOC MI - VI - EI － 1NCI1 IEEE Inverse Curve Type MI MI MI MI MI
-IEEE
M1NC1C
122 NOC CO2 - CO8 － 1NCI1 US Inverse Curve Type CO2 CO2 CO2 CO2 CO2
-US
123 NOC 1NC1R DEF - DEP － 1NCI1 Reset Characteristic DEF DEF DEF DEF DEF
124 NOC 1NC1-2F NA - Block － 1NC1 2f Block Enable NA NA NA NA NA
M1NC2C
-IEC
M1NC2C
-IEEE
M1NC2C
-US
 260 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
M2NC1C
-IEC
M2NC1C
-IEEE
M2NC1C
-US
M2NC2C
-IEC
M2NC2C
-IEEE
M2NC2C
-US
146 OCV OCV3PH 1PP - 3PH － Voltage phase number -- -- 1PP 1PP --
OCV
147 OCV ONE - BOTH － OCV control side -- -- One One One
CONT
OCV
148 OCV AB - BC - CA － OCV Reference phase -- -- AB AB --
REPH
149 OCV 1OCVEN Off - Cont - Rest － OCV1 Enable -- -- Off Off Off
M1OCVC
150 OCV NI - VI - EI - LTI － OCV IEC Inverse Curve Type -- -- NI NI NI
-IEC
M1OCVC
151 OCV MI - VI - EI － OCV IEEE Inverse Curve Type -- -- MI MI MI
-IEEE
M1OCVC
152 OCV CO2 - CO8 － OCV US Inverse Curve Type -- -- CO2 CO2 CO2
-US
153 OCV M1OCVR DEF - DEP － OCV Reset Characteristic -- -- DEF DEF DEF
154 OCV 1OCV-2F NA - Block － OCV 2f Block Enable -- -- NA NA NA
3POR -
155 OCV 1OCVTP － OCV trip mode -- -- 3POR 3POR 3POR
2OUTOF3
156 OCV 2OCVEN Off - Cont - Rest － OCV1 Enable -- -- Off Off Off
M2OCVC
157 OCV NI - VI - EI - LTI － OCV IEC Inverse Curve Type -- -- NI NI NI
-IEC
M2OCVC
158 OCV MI - VI - EI － OCV IEEE Inverse Curve Type -- -- MI MI MI
-IEEE
M2OCVC
159 OCV CO2 - CO8 － OCV US Inverse Curve Type -- -- CO2 CO2 CO2
-US
160 OCV M2OCVR DEF - DEP － OCV Reset Characteristic -- -- DEF DEF DEF
161 OCV 2OCV-2F NA - Block － OCV 2f Block Enable -- -- NA NA NA
3POR -
162 OCV 2OCVTP － OCV trip mode -- -- 3POR 3POR 3POR
2OUTOF3
163 THM THMEN Off - On － Thermal OL Enable Off Off Off Off Off
164 THM THMAEN Off - On － Thermal Alarm Enable Off Off Off Off Off
165 CBF BTC1 Off - On － Back-trip control1 Off Off Off Off Off
166 CBF BTC2 Off - On － Back-trip control2 Off Off Off Off Off
167 CBF RTC1 Off - DIR - OC － Re-trip control1 Off Off Off Off Off
168 CBF RTC2 Off - DIR - OC － Re-trip control2 Off Off Off Off Off
Off - DT –
169 OV OV1EN － OV1 Enable -- -- DT DT DT
IDMT - C
Off - DT –
170 OV OV2EN － OV2 Enable -- -- Off Off Off
IDMT - C
Off - DT –
171 UV UV1EN － UV1 Enable -- -- DT DT DT
IDMT - C
Off - DT –
172 UV UV2EN － UV2 Enable -- -- Off Off Off
IDMT - C
173 UV VBLKEN Off - On － UV Block Enable -- -- Off Off Off
174 FRQ FRQ1EN Off - OF - UF － FRQ1 Enable -- -- Off Off Off
175 FRQ FRQ2EN Off - OF - UF － FRQ2 Enable -- -- Off Off Off
 261 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
DFRQ1
176 DFRQ Off - R - D － DFRQ1 Enable -- -- Off Off Off
EN
DFRQ2
177 DFRQ Off - R - D － DFRQ2 Enable -- -- Off Off Off
EN
178 M.T1-1 Off - On － Mechanical trip1-1 On On On On On
182 M.T3-1 Off - On － Mechanical trip3-1 Off Off Off Off Off
186 DIF ik 0.10 - 1.00 PU Minimum operating current 0.30 0.30 0.30 0.30 0.30
187 DIF p1 10 - 100 % % slope of small current region 100 100 100 100 100
188 DIF p2 10 - 200 % % slope of large current region 200 200 200 200 200
189 DIF kp 1.00 - 20.00 PU Break point of DIF characteristic 1.00 1.00 1.00 1.00 1.00
190 DIF kh 2.00 - 20.00 PU hige-set current 4.00 4.00 4.00 4.00 4.00
191 DIF TxCap 0.1 - 3000.0 MVA capacity of transformer 40.0 40.0 40.0 40.0 40.0
192 DIF Vn1 0.4 - 500.0 kV rated voltage of primary winding 132 132 132 132 132
rated voltage of secondary
193 DIF Vn2 0.4 - 500.0 kV 66 66 66 66 66
winding
194 DIF yd_p 1-2 － Primary winding 1 1 1 1 1
195 DIF yd_s 1-2 － Secondary winding 1 1 1 1 1
196 DIF vec_s 0 - 11 － Phase angel(Secondary) 0 0 0 0 0
197 DIF k2f 10 - 50 % 2f restraint 15 15 15 15 15
198 DIF k5f 10 - 50 % 5f restraint 30 30 30 30 30
199 DIF TDIF 0.00 - 10.00 s DIF Definite time setting 0.00 0.00 0.00 0.00 0.00
200 DIF TDIFHS 0.00 - 10.00 s DIFHS Definite time setting 0.00 0.00 0.00 0.00 0.00
Minimum operating current for
201 REF 1ik 0.05 - 2.50 PU -- 0.05 -- 0.05 0.05
REF1
202 REF 1p2 50 - 100 % Percent slope for REF1 -- 100 -- 100 100
Break point of REF1
203 REF 1kp 0.50 - 10.00 PU -- 1.00 -- 1.00 1.00
characteristic
204 REF T1REF 0.00 - 10.00 s REF1 delay trip timer -- 0.00 -- 0.00 0.00
205 REF 2ik 0.05 - 2.50 PU -- 0.05 -- 0.05 0.05
REF2
206 REF 2p2 50 - 100 % Percent slope for REF2 -- 100 -- 100 100
Break point of REF2
207 REF 2kp 0.50 - 10.00 PU -- 1.00 -- 1.00 1.00
characteristic
208 REF T2REF 0.00 - 10.00 s REF2 delay trip timer -- 0.00 -- 0.00 0.00
209 REF 1REFOC1 0.01 - 1.00 PU -- 0.200 -- 0.200 0.200
1REFOC1
Minimum operating currenty for
210 REF 1REFOC2 0.01 - 1.00 PU -- 0.150 -- 0.150 0.150
1REFOC2
T1REF
211 REF 0.00 - 10.00 s 1REFOC1 delay trip timer -- 0.05 -- 0.05 0.05
OC1
T1REF
OC2
213 REF 2REFOC1 0.01 - 1.00 PU -- 0.200 -- 0.200 0.200
2REFOC1
214 REF 2REFOC2 0.01 - 1.00 PU -- 0.150 -- 0.150 0.150
2REFOC2
T2REF
OC1
T2REF
OC2
217 V/f V 100.0 - 120.0 V Voltage -- -- 100.0 100.0 100.0
218 V/f A 1.03 - 1.30 PU Alarm level -- -- 1.03 1.03 1.03
219 V/f L 1.05 - 1.30 PU Low level -- -- 1.05 1.05 1.05
220 V/f H 1.10 - 1.40 PU High level -- -- 1.40 1.40 1.40
221 V/f LT 1 - 600 s Inverse time delay for high level -- -- 600 600 600
 262 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
222 V/f HT 1 - 600 s Inverse time delay fir low level -- -- 1 1 1
223 V/f RT 60 - 3600 s Radiant heat time -- -- 250 250 250
224 V/f TVFH 1 - 600 s Delay time for high level -- -- 10 10 10
225 V/f TVFA 1 - 600 s Delay time for alarm level -- -- 10 10 10
226 OC 1OC1 0.10 - 20.00 PU 1OC1 Threshold setting 1.00 1.00 1.00 1.00 1.00
227 OC 1OCI1 0.10 - 5.00 PU 1OCI1 Threshold setting 1.00 1.00 1.00 1.00 1.00
228 OC T1OC1 0.00 - 300.00 s 1OC1 Definite time setting 0.00 0.00 0.00 0.00 0.00
229 OC T1OC1M 0.010 - 15.000 － 1OC1 Time multiplier setting 1.000 1.000 1.000 1.000 1.000
230 OC T1OC1R 0.0 - 300.0 s 1OC1 Definite time reset delay 0.0 0.0 0.0 0.0 0.0
T1OC1 1OC1 Dependent time reset time
231 OC 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
RM multiplier
Configurable IDMT Curve setting
232 OC 1OC1-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 1OC1
233 OC 1OC1-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
234 OC 1OC1-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
235 OC 1OC1-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
236 OC 1OC1-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
242 OC 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
RM multiplier
243 OC 1OC2-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 1OC2
244 OC 1OC2-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
245 OC 1OC2-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
246 OC 1OC2-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
247 OC 1OC2-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
253 OC 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
RM multiplier
254 OC 2OC1-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 2OC1
255 OC 2OC1-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
256 OC 2OC1-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
257 OC 2OC1-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
258 OC 2OC1-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
264 OC 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
RM multiplier
265 OC 2OC2-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 2OC2
266 OC 2OC2-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
267 OC 2OC2-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
268 OC 2OC2-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
269 OC 2OC2-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
 263 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
270 EF 1EF1 0.10 - 20.00 PU 1EF1 Threshold setting 0.30 0.30 0.30 0.30 0.30
271 EF 1EFI1 0.10 -5.00 PU 1EFI1 Threshold setting 0.30 0.30 0.30 0.30 0.30
272 EF T1EF1 0.00 - 300.00 s 1EF1 Definite time setting 0.00 0.00 0.00 0.00 0.00
273 EF T1EF1M 0.010 - 15.000 s 1EF1 Time multiplier setting 1.000 1.000 1.000 1.000 1.000
274 EF T1EF1R 0.0 - 300.0 － 1EF1 Definite time reset delay 0.0 0.0 0.0 0.0 0.0
1EF1 Dependent time reset time
275 EF T1EF1RM 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
multiplier
276 EF 1EF1-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 1EF1
277 EF 1EF1-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
278 EF 1EF1-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
279 EF 1EF1-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
280 EF 1EF1-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
282 EF 1EFI2 0.10 - 5.00 PU 1EFI2 Threshold setting 3.00 3.00 3.00 3.00 3.00
284 EF T1EF2M 0.010 - 15.000 － 1EF2 Time multiplier setting 1.000 1.000 1.000 1.000 1.000
285 EF T1EF2R 0.0 - 300.0 s 1EF2 Definite time reset delay 0.0 0.0 0.0 0.0 0.0
286 EF T1EF2RM 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
multiplier
287 EF 1EF2-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 1EF2
288 EF 1EF2-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
289 EF 1EF2-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
290 EF 1EF2-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
291 EF 1EF2-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
297 EF T2EF1RM 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
multiplier
298 EF 2EF1-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 2EF1
299 EF 2EF1-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
300 EF 2EF1-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
301 EF 2EF1-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
302 EF 2EF1-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
308 EF T2EF2RM 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
multiplier
309 EF 2EF2-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 2EF2
310 EF 2EF2-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
311 EF 2EF2-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
312 EF 2EF2-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
313 EF 2EF2-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
314 NOC 1NC1 0.10 - 20.00 PU 1NOC1 Threshold setting 0.40 0.40 0.40 0.40 0.40
315 NOC 1NCI1 0.10 - 5.00 PU 1NOCI1 Threshold setting 0.40 0.40 0.40 0.40 0.40
316 NOC T1NC1 0.00 - 300.00 s 1NOC1 Definite time setting 0.00 0.00 0.00 0.00 0.00
317 NOC T1NC1M 0.010 - 15.000 － 1NOC1 Time multiplier setting 1.000 1.000 1.000 1.000 1.000
318 NOC T1NC1R 0.0 - 300.0 s 1NOC1 Definite time reset delay 0.0 0.0 0.0 0.0 0.0
 264 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
T1NC1 1NOC1 Dependent time reset
319 NOC 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
RM time multiplier
320 NOC 1NC1-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 1NOC1
321 NOC 1NC1-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
322 NOC 1NC1-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
323 NOC 1NC1-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
324 NOC 1NC1-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
330 NOC 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
RM time multiplier
331 NOC 1NC2-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 1NOC2
332 NOC 1NC2-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
333 NOC 1NC2-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
334 NOC 1NC2-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
335 NOC 1NC2-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
341 NOC 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
RM time multiplier
342 NOC 2NC1-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 2NOC1
343 NOC 2NC1-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
344 NOC 2NC1-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
345 NOC 2NC1-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
346 NOC 2NC1-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
352 NOC 0.010 - 15.000 － 1.000 1.000 1.000 1.000 1.000
RM time multiplier
353 NOC 2NC2-k 0.00 - 300.00 － 0.14 0.14 0.14 0.14 0.14
of 2NOC2
354 NOC 2NC2-α 0.01 - 5.00 － ditto 0.02 0.02 0.02 0.02 0.02
355 NOC 2NC2-C 0.000 - 5.000 － ditto 0.000 0.000 0.000 0.000 0.000
356 NOC 2NC2-kr 0.00 - 300.00 － ditto 2.00 2.00 2.00 2.00 2.00
357 NOC 2NC2-β 0.01 - 5.00 － ditto 2.00 2.00 2.00 2.00 2.00
358 OCV 1OCV 10.00 - 120.00 V OCV Threshold setting -- -- 70.00 70.00 70.00
359 OCV 1OCVIS 0.10 - 5.00 PU OCV Threshold setting -- -- 1.00 1.00 1.00
360 OCV T1OCVM 0.010 - 15.000 － OCV Time multiplier setting -- -- 1.00 1.00 1.00
361 OCV T1OCVR 0.0 - 300.0 s OCV Definite time reset delay -- -- 0.0 0.0 0.0
T1OCV OCV Dependent time reset time
362 OCV 0.010 - 15.000 － -- -- 1.000 1.000 1.000
RM multiplier
363 OCV 1OCV-k 0.00 - 300.00 － -- -- 0.14 0.14 0.14
of OCV
364 OCV 1OCV-α 0.01 - 5.00 － ditto -- -- 0.02 0.02 0.02
365 OCV 1OCV-C 0.000 - 5.000 － ditto -- -- 0.000 0.000 0.000
366 OCV 1OCV-kr 0.00 - 300.00 － ditto -- -- 2.00 2.00 2.00
 265 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
367 OCV 1OCV-β 0.01 - 5.00 － ditto -- -- 2.00 2.00 2.00
368 OCV 2OCV 10.00 - 120.00 V OCV Threshold setting -- -- 70.00 70.00 70.00
369 OCV 2OCVIS 0.10 - 5.00 PU OCV Threshold setting -- -- 1.00 1.00 1.00
370 OCV T2OCVM 0.010 - 15.000 － OCV Time multiplier setting -- -- 1.000 1.000 1.000
371 OCV T2OCVR 0.0 - 300.0 s OCV Definite time reset delay -- -- 0.0 0.0 0.0
T2OCV OCV Dependent time reset time
372 OCV 0.010 - 15.000 － -- -- 1.000 1.000 1.000
RM multiplier
373 OCV 2OCV-k 0.00 - 300.00 － -- -- 0.14 0.14 0.14
of OCV
374 OCV 2OCV-α 0.01 - 5.00 － ditto -- -- 0.02 0.02 0.02
375 OCV 2OCV-C 0.000 - 5.000 － ditto -- -- 0.000 0.000 0.000
376 OCV 2OCV-kr 0.00 - 300.00 － ditto -- -- 2.00 2.00 2.00
377 OCV 2OCV-β 0.01 - 5.00 － ditto -- -- 2.00 2.00 2.00
378 THM THM 0.40 - 2.50 PU Thermal overload setting 1.00 1.00 1.00 1.00 1.00
379 THM THMIP 0.00 - 1.00 PU Pre Current value 0.00 0.00 0.00 0.00 0.00
380 THM TTHM 0.5 - 500.0 s Thermal Time Constant 10.0 10.0 10.0 10.0 10.0
381 THM THMA 50 - 99 % Thermal alarm setting 80 80 80 80 80
382 ICD ICD1-2f 10 - 50 % Sensitivity of 2f 15 15 15 15 15
383 ICD ICD1OC 1.00 - 5.00 PU Threshold of fundamental current 1.00 1.00 1.00 1.00 1.00
384 ICD ICD2-2f 10 - 50 % Sensitivity of 2f 15 15 15 15 15
385 ICD ICD2OC 1.00 - 5.00 PU Threshold of fundamental current 1.00 1.00 1.00 1.00 1.00
386 CBF CBF1 0.10 - 2.00 PU CBF Threshold setting 0.50 0.50 0.50 0.50 0.50
387 CBF TBTC1 0.00 - 300.00 s Back trip Definite time setting 1.00 1.00 1.00 1.00 1.00
388 CBF TRTC1 0.00 - 300.00 s Re-trip Definite time setting 0.50 0.50 0.50 0.50 0.50
389 CBF CBF2 0.10 - 2.00 PU CBF Threshold setting 0.50 0.50 0.50 0.50 0.50
390 CBF TBTC2 0.00 - 300.00 s Back trip Definite time setting 1.00 1.00 1.00 1.00 1.00
391 CBF TRTC2 0.00 - 300.00 s Re-trip Definite time setting 0.50 0.50 0.50 0.50 0.50
392 OV OV1 10.00 - 200.00 V OV1 Threshold setting -- -- 120.0 120.0 120.0
393 OV TOV1 0.00 - 300.00 s OV1 Definite time setting -- -- 0.10 0.10 0.10
394 OV TOV1M 0.05 - 100.00 － OV1 Time multiplier setting -- -- 10.00 10.00 10.00
395 OV TOV1R 0.0 - 300.0 s OV1 Definite time reset delay -- -- 0.0 0.0 0.0
396 OV OV1DPR 10 - 98 % OV1 DO/PU ratio -- -- 95 95 95
397 OV OV1-k 0.00 - 300.00 － -- -- 1.00 1.00 1.00
of OV1
398 OV OV1-α 0.01 - 5.00 － ditto -- -- 1.00 1.00 1.00
399 OV OV1-C 0.000 - 5.000 － ditto -- -- 0.000 0.000 0.000
400 OV OV2 10.0 - 200.0 V OV2 Threshold setting -- -- 140.0 140.0 140.0
401 OV TOV2 0.00 - 300.00 s OV2 Definite time setting -- -- 0.10 0.10 0.10
402 OV OV2DPR 10 - 98 % OV2 DO/PU ratio -- -- 95 95 95
403 UV UV1 5.0 - 130.0 V UV1 Threshold setting -- -- 20.0 20.0 20.0
404 UV TUV1 0.00 - 300.00 s UV1 Definite time setting -- -- 0.00 0.00 0.00
405 UV TUV1M 0.05 - 100.00 － UV1 Time multiplier setting -- -- 10.00 10.00 10.00
406 UV TUV1R 0.0 - 300.00 s UV1 Definite time reset delay -- -- 0.0 0.0 0.0
407 UV UV1-k 0.00 - 300.00 － -- -- 1.00 1.00 1.00
of UV1
408 UV UV1-α 0.01 - 5.00 － ditto -- -- 1.00 1.00 1.00
409 UV UV1-C 0.000 - 5.000 － ditto -- -- 0.000 0.000 0.000
410 UV UV2 5.0 - 130.0 V UV2 Threshold setting -- -- 15.0 15.0 15.0
411 UV TUV2 0.00 - 300.00 s UV2 Definite time setting -- -- 0.00 0.00 0.00
412 UV VBLK 5.0 - 20.0 V UV Blocking threshold -- -- 10.0 10.0 10.0
413 FRQ FRQ1 -10.00 - 10.00 Hz FRQ1 Threshold setting -- -- -1.00 -1.00 -1.00
414 FRQ TFRQ1 0.00 - 300.00 s FRQ1 Definite time setting -- -- 1.00 1.00 1.00
415 FRQ FRQ2 -10.00 - 10.00 Hz FRQ2 Threshold setting -- -- -1.00 -1.00 -1.00
416 FRQ TFRQ2 0.00 - 300.00 s FRQ2 Definite time setting -- -- 1.00 1.00 1.00
 266 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
417 FRQ FVBLK 40.0 - 100.0 V UV Blocking threshold -- -- 40.0 40.0 40.0
418 DFRQ DFRQ1 0.1 - 15.0 Hzs DFRQ1 Threshold setting. -- -- 0.5 0.5 0.5
419 DFRQ DFRQ2 0.1 - 15.0 Hzs DFRQ2 Threshold setting. -- -- 0.5 0.5 0.5
Number of bi-trigger (on/off)
586 Rec BITRN 0 - 128 － 100 100 100 100 100
events
Phase Phase indication of Fault Operati Operati Operati Operati Operati
587 Rec Operating - Fault －
mode recording ng ng ng ng ng
588 Rec EV1 0 - 3071 － Event record signal No 768 768 768 768 768
589 Rec EV2 0 - 3071 － ditto 769 769 769 769 769
590 Rec EV3 0 - 3071 － ditto 770 770 770 770 770
591 Rec EV4 0 - 3071 － ditto 771 771 771 771 771
592 Rec EV5 0 - 3071 － ditto 772 772 772 772 772
593 Rec EV6 0 - 3071 － ditto 773 773 773 773 773
594 Rec EV7 0 - 3071 － ditto 0 0 (774) (774) (774)

595 Rec EV8 0 - 3071 － ditto 0 0 (775) (775) (775)
596 Rec EV9 0 - 3071 － ditto 0 0 (776) (776) (776)
597 Rec EV10 0 - 3071 － ditto 0 0 (777) (777) (777)
598 Rec EV11 0 - 3071 － ditto 0 0 (778) (778) (778)

599 Rec EV12 0 - 3071 － ditto 0 0 (779) (779) (779)
600 Rec EV13 0 - 3071 － ditto 0 0 ((780)) ((780)) ((780))
601 Rec EV14 0 - 3071 － ditto 0 0 ((781)) ((781)) ((781))

602 Rec EV15 0 - 3071 － ditto 0 0 ((782)) ((782)) ((782))
603 Rec EV16 0 - 3071 － ditto 0 0 ((783)) ((783)) ((783))
604 Rec EV17 0 - 3071 － ditto 0 0 ((784)) ((784)) ((784))

605 Rec EV18 0 - 3071 － ditto 0 0 ((785)) ((785)) ((785))
606 Rec EV19 0 - 3071 － ditto 570 570 570 570 570
607 Rec EV20 0 - 3071 － ditto 571 571 571 571 571
608 Rec EV21 0 - 3071 － ditto 572 572 572 572 572
609 Rec EV22 0 - 3071 － ditto 573 573 573 573 573
610 Rec EV23 0 - 3071 － ditto 371 371 371 371 371
611 Rec EV24 0 - 3071 － ditto 1639 1639 1639 1639 1639
612 Rec EV25 0 - 3071 － ditto 2629 2629 2629 2629 2629
613 Rec EV26 0 - 3071 － ditto 2630 2630 2630 2630 2630
614 Rec EV27 0 - 3071 － ditto 2631 2631 2631 2631 2631
615 Rec EV28 0 - 3071 － ditto 1251 1251 1251 1251 1251
616 Rec EV29 0 - 3071 － ditto 1266 1266 1266 1266 1266
617 Rec EV30 0 - 3071 － ditto 1267 1267 1267 1267 1267
618 Rec EV31 0 - 3071 － ditto 0 0 0 0 0

619 Rec EV32 0 - 3071 － ditto 0 0 0 0 0
620 Rec EV33 0 - 3071 － ditto 0 0 0 0 0

621 Rec EV34 0 - 3071 － ditto 0 0 0 0 0
622 Rec EV35 0 - 3071 － ditto 0 0 0 0 0

623 Rec EV36 0 - 3071 － ditto 0 0 0 0 0
624 Rec EV37 0 - 3071 － ditto 0 0 0 0 0
625 Rec EV38 0 - 3071 － ditto 0 0 0 0 0
626 Rec EV39 0 - 3071 － ditto 0 0 0 0 0

627 Rec EV40 0 - 3071 － ditto 0 0 0 0 0
628 Rec EV41 0 - 3071 － ditto 0 0 0 0 0
 267 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
629 Rec EV42 0 - 3071 － ditto 0 0 0 0 0
630 Rec EV43 0 - 3071 － ditto 0 0 0 0 0
631 Rec EV44 0 - 3071 － ditto 0 0 0 0 0
632 Rec EV45 0 - 3071 － ditto 0 0 0 0 0
633 Rec EV46 0 - 3071 － ditto 0 0 0 0 0
634 Rec EV47 0 - 3071 － ditto 0 0 0 0 0

635 Rec EV48 0 - 3071 － ditto 0 0 0 0 0
636 Rec EV49 0 - 3071 － ditto 1258 1258 1258 1258 1258
637 Rec EV50 0 - 3071 － ditto 1438 1438 1438 1438 1438
638 Rec EV51 0 - 3071 － ditto 0 0 0 0 0

639 Rec EV52 0 - 3071 － ditto 0 0 0 0 0
640 Rec EV53 0 - 3071 － ditto 0 0 0 0 0

641 Rec EV54 0 - 3071 － ditto 0 0 0 0 0
642 Rec EV55 0 - 3071 － ditto 0 0 0 0 0
643 Rec EV56 0 - 3071 － ditto 0 0 0 0 0

644 Rec EV57 0 - 3071 － ditto 0 0 0 0 0
645 Rec EV58 0 - 3071 － ditto 0 0 0 0 0

646 Rec EV59 0 - 3071 － ditto 0 0 0 0 0
647 Rec EV60 0 - 3071 － ditto 0 0 0 0 0
648 Rec EV61 0 - 3071 － ditto 0 0 0 0 0

649 Rec EV62 0 - 3071 － ditto 0 0 0 0 0
650 Rec EV63 0 - 3071 － ditto 0 0 0 0 0
651 Rec EV64 0 - 3071 － ditto 0 0 0 0 0
652 Rec EV65 0 - 3071 － ditto 0 0 0 0 0

653 Rec EV66 0 - 3071 － ditto 0 0 0 0 0
654 Rec EV67 0 - 3071 － ditto 0 0 0 0 0
655 Rec EV68 0 - 3071 － ditto 0 0 0 0 0

656 Rec EV69 0 - 3071 － ditto 0 0 0 0 0
657 Rec EV70 0 - 3071 － ditto 0 0 0 0 0

658 Rec EV71 0 - 3071 － ditto 0 0 0 0 0
659 Rec EV72 0 - 3071 － ditto 0 0 0 0 0
660 Rec EV73 0 - 3071 － ditto 0 0 0 0 0

661 Rec EV74 0 - 3071 － ditto 0 0 0 0 0
662 Rec EV75 0 - 3071 － ditto 0 0 0 0 0
663 Rec EV76 0 - 3071 － ditto 0 0 0 0 0

664 Rec EV77 0 - 3071 － ditto 0 0 0 0 0
665 Rec EV78 0 - 3071 － ditto 0 0 0 0 0
666 Rec EV79 0 - 3071 － ditto 0 0 0 0 0

667 Rec EV80 0 - 3071 － ditto 0 0 0 0 0
668 Rec EV81 0 - 3071 － ditto 0 0 0 0 0
669 Rec EV82 0 - 3071 － ditto 0 0 0 0 0

670 Rec EV83 0 - 3071 － ditto 0 0 0 0 0
671 Rec EV84 0 - 3071 － ditto 0 0 0 0 0

672 Rec EV85 0 - 3071 － ditto 0 0 0 0 0
673 Rec EV86 0 - 3071 － ditto 0 0 0 0 0
674 Rec EV87 0 - 3071 － ditto 0 0 0 0 0
 268 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
675 Rec EV88 0 - 3071 － ditto 0 0 0 0 0
676 Rec EV89 0 - 3071 － ditto 471 471 471 471 471
677 Rec EV90 0 - 3071 － ditto 472 472 472 472 472
678 Rec EV91 0 - 3071 － ditto 473 473 473 473 473
679 Rec EV92 0 - 3071 － ditto 474 474 474 474 474
680 Rec EV93 0 - 3071 － ditto 0 0 (475) (475) (475)

681 Rec EV94 0 - 3071 － ditto 0 0 (476) (476) (476)
682 Rec EV95 0 - 3071 － ditto 0 0 (477) (477) (477)
683 Rec EV96 0 - 3071 － ditto 0 0 (478) (478) (478)
684 Rec EV97 0 - 3071 － ditto 0 0 (479) (479) (479)

685 Rec EV98 0 - 3071 － ditto 0 0 (480) (480) (480)
686 Rec EV99 0 - 3071 － ditto 0 0 ((481)) ((481)) ((481))

687 Rec EV100 0 - 3071 － ditto 0 0 ((482)) ((482)) ((482))
688 Rec EV101 0 - 3071 － ditto 0 0 ((483)) ((483)) ((483))
689 Rec EV102 0 - 3071 － ditto 0 0 ((484)) ((484)) ((484))

690 Rec EV103 0 - 3071 － ditto 0 0 ((485)) ((485)) ((485))
691 Rec EV104 0 - 3071 － ditto 0 0 ((486)) ((486)) ((486))

692 Rec EV105 0 - 3071 － ditto 0 0 0 0 0
693 Rec EV106 0 - 3071 － ditto 0 0 0 0 0
694 Rec EV107 0 - 3071 － ditto 2640 2640 2640 2640 2640
695 Rec EV108 0 - 3071 － ditto 2641 2641 2641 2641 2641
696 Rec EV109 0 - 3071 － ditto 1448 1448 1448 1448 1448
697 Rec EV110 0 - 3071 － ditto 1449 1449 1449 1449 1449
698 Rec EV111 0 - 3071 － ditto 1450 1450 1450 1450 1450
699 Rec EV112 0 - 3071 － ditto 0 0 0 0 0
700 Rec EV113 0 - 3071 － ditto 0 0 0 0 0
701 Rec EV114 0 - 3071 － ditto 0 0 0 0 0

702 Rec EV115 0 - 3071 － ditto 0 0 0 0 0
703 Rec EV116 0 - 3071 － ditto 0 0 0 0 0

704 Rec EV117 0 - 3071 － ditto 0 0 0 0 0
705 Rec EV118 0 - 3071 － ditto 0 0 0 0 0
706 Rec EV119 0 - 3071 － ditto 1445 1445 1445 1445 1445
707 Rec EV120 0 - 3071 － ditto 0 0 0 0 0
708 Rec EV121 0 - 3071 － ditto 1409 1409 1409 1409 1409
709 Rec EV122 0 - 3071 － ditto 1435 1435 1435 1435 1435
710 Rec EV123 0 - 3071 － ditto 1436 1436 1436 1436 1436
711 Rec EV124 0 - 3071 － ditto 1437 1437 1437 1437 1437
712 Rec EV125 0 - 3071 － ditto 0 0 0 0 0

713 Rec EV126 0 - 3071 － ditto 0 0 0 0 0
714 Rec EV127 0 - 3071 － ditto 0 0 0 0 0
715 Rec EV128 0 - 3071 － ditto 1442 1442 1442 1442 1442
716 D-Rec Time1 0.1 - 4.9 s Disturbance record previous time 0.3 0.3 0.3 0.3 0.3
717 D-Rec Time2 0.1 - 4.9 s Disturbance record after time 2.0 2.0 2.0 2.0 2.0
718 D-Rec 1OCPS 0.10 - 20.00 pu Disturbance record initiation 2.00 2.00 2.00 2.00 2.00
719 D-Rec 2OCPS 0.10 - 20.00 pu ditto 2.00 2.00 2.00 2.00 2.00
720 D-Rec 1OCPG 0.05 - 20.00 pu ditto 0.60 0.60 0.60 0.60 0.60
 269 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
721 D-Rec 2OCPG 0.05 - 20.00 pu ditto 0.60 0.60 0.60 0.60 0.60
722 D-Rec OV 10.0 - 200.0 V ditto -- -- 120.0 120.0 120.0
723 D-Rec UV 5.0 - 130.0 V ditto -- -- 60.0 60.0 60.0
Disturbance record trigger use or
724 D-Rec TRIP1 Off - On － On On On On On
not
725 D-Rec TRIP2 Off - On － ditto On On On On On
726 D-Rec 1OCPS Off - On － ditto On On On On On
727 D-Rec 2OCPS Off - On － ditto On On On On On
728 D-Rec 1OCPG Off - On － ditto On On On On On
729 D-Rec 2OCPG Off - On － ditto On On On On On
730 D-Rec 2F Off - On － ditto On On On On On
731 D-Rec 5F Off - On － ditto On On On On On
732 D-Rec EVENT1 Off - On － ditto On On On On On
735 D-Rec OV Off - On － ditto -- -- On On On
736 D-Rec UV Off - On － ditto -- -- On On On
737 D-Rec SIG1 0 - 3071 － Signal No 369 369 369 369 369
738 D-Rec SIG2 0 - 3071 － ditto 370 370 370 370 370
739 D-Rec SIG3 0 - 3071 － ditto 500 500 500 500 500
740 D-Rec SIG4 0 - 3071 － ditto 501 501 501 501 501
741 D-Rec SIG5 0 - 3071 － ditto 405 405 405 405 405
742 D-Rec SIG6 0 - 3071 － ditto 409 409 409 409 409
743 D-Rec SIG7 0 - 3071 － ditto 0 503 503 503 503
744 D-Rec SIG8 0 - 3071 － ditto 0 504 504 504 504
745 D-Rec SIG9 0 - 3071 － ditto 221 221 221 221 221
746 D-Rec SIG10 0 - 3071 － ditto 229 229 229 229 229
747 D-Rec SIG11 0 - 3071 － ditto 237 237 237 237 237
748 D-Rec SIG12 0 - 3071 － ditto 245 245 245 245 245
749 D-Rec SIG13 0 - 3071 － ditto 225 225 225 225 225
750 D-Rec SIG14 0 - 3071 － ditto 233 233 233 233 233
751 D-Rec SIG15 0 - 3071 － ditto 241 241 241 241 241
752 D-Rec SIG16 0 - 3071 － ditto 249 249 249 249 249
753 D-Rec SIG17 0 - 3071 － ditto 261 261 261 261 261
754 D-Rec SIG18 0 - 3071 － ditto 263 263 263 263 263
755 D-Rec SIG19 0 - 3071 － ditto 265 265 265 265 265
756 D-Rec SIG20 0 - 3071 － ditto 267 267 267 267 267
757 D-Rec SIG21 0 - 3071 － ditto 262 262 262 262 262
758 D-Rec SIG22 0 - 3071 － ditto 264 264 264 264 264
759 D-Rec SIG23 0 - 3071 － ditto 266 266 266 266 266
760 D-Rec SIG24 0 - 3071 － ditto 268 268 268 268 268
761 D-Rec SIG25 0 - 3071 － ditto 0 0 356 356 356
762 D-Rec SIG26 0 - 3071 － ditto 0 0 357 357 357
763 D-Rec SIG27 0 - 3071 － ditto 293 293 293 293 293
764 D-Rec SIG28 0 - 3071 － ditto 570 570 570 570 570
765 D-Rec SIG29 0 - 3071 － ditto 571 571 571 571 571
766 D-Rec SIG30 0 - 3071 － ditto 572 572 572 572 572
767 D-Rec SIG31 0 - 3071 － ditto 573 573 573 573 573
768 D-Rec SIG32 0 - 3071 － ditto 0 0 0 0 0
769 Cnt TC1SPEN Off - On - Opt-On － Trip Circuit1 Supervision Enable Off Off Off Off Off
770 Cnt TC2SPEN Off - On - Opt-On － Trip Circuit2 Supervision Enable Off Off Off Off Off
CB1SM
771 Cnt Off - On － CB1 condition super visor enable Off Off Off Off Off
EN
 270 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
CB2SM
772 Cnt Off - On － CB2 condition super visor enable Off Off Off Off Off
EN
773 Cnt TC1AEN Off - On － Trip Counter1 Alarm Enable Off Off Off Off Off
774 Cnt TC2AEN Off - On － Trip Counter2 Alarm Enable Off Off Off Off Off
775 Cnt OPT1AEN Off - On － Operate Time1 Alarm Enable Off Off Off Off Off
776 Cnt OPT2AEN Off - On － Operate Time2 Alarm Enable Off Off Off Off Off
777 Cnt TC1ALM 1 - 10000 － Trip Count1 Alarm Threshold 10000 10000 10000 10000 10000
778 Cnt TC2ALM 1 - 10000 － Trip Count2 Alarm Threshold 10000 10000 10000 10000 10000
779 Cnt OPT1ALM 100 - 5000 ms Operate Time1 Alarm Threshold 1000 1000 1000 1000 1000
780 Cnt OPT2ALM 100 - 5000 ms Operate Time2 Alarm Threshold 1000 1000 1000 1000 1000
781 Status Display Pri - Sec - Pri-A － Metering Pri Pri Pri Pri Pri
782 Status Power Send - Receive － Metering -- -- -- -- Send
783 Status Current Lag - Lead － Metering -- -- -- -- Lead
Time Off-BI-Modbus- Time sync
784 Status － Off Off Off Off Off
sync. IRIG-IEC103
785 BI1 BITHR1 V1 - V2 - V3 － Binary Input Threshold setting1 V2 V2 V2 V2 V2
786 BI1 BITHR2 V1 - V2 － Binary Input Threshold setting2 V1 V1 V1 V1 V1
787 BI1 BI1PUD 0.00 - 300.00 s Binary Input Drop-off delay 0.00 0.00 0.00 0.00 0.00
788 BI1 BI1DOD 0.00 - 300.00 s Binary Input Sense 0.00 0.00 0.00 0.00 0.00
789 BI1 BI1SNS Norm - Inv － Binary Input Pick-up delay Norm Norm Norm Norm Norm
805 BI7 BI7PUD 0.00 - 300.00 s Binary Input Drop-off delay (0.00) (0.00) (0.00) (0.00) (0.00)
806 BI7 BI7DOD 0.00 - 300.00 s Binary Input Sense (0.00) (0.00) (0.00) (0.00) (0.00)
807 BI7 BI7SNS Norm - Inv － Binary Input Pick-up delay (Norm) (Norm) (Norm) (Norm) (Norm)
 271 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
841 BO1 Logic OR - AND － Logic gate OR OR OR OR OR
842 BO1 Reset Ins - Dl - Dw - Lat － Reset application Dl Dl Dl Dl Dl
843 BO1 In#1 0 - 3071 － Output signal 0 0 0 0 0
844 BO1 In#2 0 - 3071 － ditto 0 0 0 0 0
845 BO1 In#3 0 - 3071 － ditto 0 0 0 0 0
846 BO1 In#4 0 - 3071 － ditto 0 0 0 0 0
847 BO1 In#5 0 - 3071 － ditto 0 0 0 0 0
848 BO1 In#6 0 - 3071 － ditto 0 0 0 0 0
849 BO1 TBO 0.00 - 10.00 s Dl/Dw timer 0.2 0.2 0.2 0.2 0.2
853 BO2 In#2 0 - 3071 － ditto 0 0 0 0 0
854 BO2 In#3 0 - 3071 － ditto 0 0 0 0 0
855 BO2 In#4 0 - 3071 － ditto 0 0 0 0 0
856 BO2 In#5 0 - 3071 － ditto 0 0 0 0 0
857 BO2 In#6 0 - 3071 － ditto 0 0 0 0 0
862 BO3 In#2 0 - 3071 － ditto 0 0 0 0 0
863 BO3 In#3 0 - 3071 － ditto 0 0 0 0 0
864 BO3 In#4 0 - 3071 － ditto 0 0 0 0 0
865 BO3 In#5 0 - 3071 － ditto 0 0 0 0 0
866 BO3 In#6 0 - 3071 － ditto 0 0 0 0 0
871 BO4 In#2 0 - 3071 － ditto 0 0 0 0 0
872 BO4 In#3 0 - 3071 － ditto 0 0 0 0 0
 272 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
873 BO4 In#4 0 - 3071 － ditto 0 0 0 0 0
874 BO4 In#5 0 - 3071 － ditto 0 0 0 0 0
875 BO4 In#6 0 - 3071 － ditto 0 0 0 0 0
877 BO4 Logic OR - AND － Logic gate (OR) (OR) (OR) (OR) (OR)
878 BO5 Reset Ins - Dl - Dw - Lat － Reset application (Dl) (Dl) (Dl) (Dl) (Dl)
879 BO5 In#1 0 - 3071 － Output signal (371) (371) (371) (371) (371)
880 BO5 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
881 BO5 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
882 BO5 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
883 BO5 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
884 BO5 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
885 BO5 TBO 0.00 - 10.00 s Dl/Dw timer (0.2) (0.2) (0.2) (0.2) (0.2)
889 BO6 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
890 BO6 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
891 BO6 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
892 BO6 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
893 BO6 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
898 BO7 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
899 BO7 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
900 BO7 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
901 BO7 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
902 BO7 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
907 BO8 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
908 BO8 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
909 BO8 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
910 BO8 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
911 BO8 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
916 BO9 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
917 BO9 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
918 BO9 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
919 BO9 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
920 BO9 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
 273 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
925 BO10 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
926 BO10 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
927 BO10 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
928 BO10 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
929 BO10 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
934 BO11 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
935 BO11 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
936 BO11 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
937 BO11 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
938 BO11 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
943 BO12 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
944 BO12 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
945 BO12 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
946 BO12 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
947 BO12 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
952 BO13 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
953 BO13 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
954 BO13 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
955 BO13 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
956 BO13 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
961 BO14 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
962 BO14 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
963 BO14 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
964 BO14 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
965 BO14 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
970 BO15 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
971 BO15 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
972 BO15 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
973 BO15 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
974 BO15 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
 274 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
979 BO16 In#2 0 - 3071 － ditto (0) (0) (0) (0) (0)
980 BO16 In#3 0 - 3071 － ditto (0) (0) (0) (0) (0)
981 BO16 In#4 0 - 3071 － ditto (0) (0) (0) (0) (0)
982 BO16 In#5 0 - 3071 － ditto (0) (0) (0) (0) (0)
983 BO16 In#6 0 - 3071 － ditto (0) (0) (0) (0) (0)
985 LED1 Logic OR - AND － LED1 Logic Gate Type OR OR OR OR OR
986 LED1 Reset Inst - Latch － LED1 Reset operation Inst Inst Inst Inst Inst
987 LED1 In #1 0 - 3071 － LED1 Functions 0 0 0 0 0
988 LED1 In #2 0 - 3071 － ditto 0 0 0 0 0
989 LED1 In #3 0 - 3071 － ditto 0 0 0 0 0
990 LED1 In #4 0 - 3071 － ditto 0 0 0 0 0
994 LED2 In #2 0 - 3071 － ditto 0 0 0 0 0
995 LED2 In #3 0 - 3071 － ditto 0 0 0 0 0
996 LED2 In #4 0 - 3071 － ditto 0 0 0 0 0
1000 LED3 In #2 0 - 3071 － ditto 0 0 0 0 0
1001 LED3 In #3 0 - 3071 － ditto 0 0 0 0 0
1002 LED3 In #4 0 - 3071 － ditto 0 0 0 0 0
1006 LED4 In #2 0 - 3071 － ditto 0 0 0 0 0
1007 LED4 In #3 0 - 3071 － ditto 0 0 0 0 0
1008 LED4 In #4 0 - 3071 － ditto 0 0 0 0 0
1012 LED5 In #2 0 - 3071 － ditto 0 0 0 0 0
1013 LED5 In #3 0 - 3071 － ditto 0 0 0 0 0
1014 LED5 In #4 0 - 3071 － ditto 0 0 0 0 0
1018 LED6 In #2 0 - 3071 － ditto 0 0 0 0 0
1019 LED6 In #3 0 - 3071 － ditto 0 0 0 0 0
1020 LED6 In #4 0 - 3071 － ditto 0 0 0 0 0
1021 LED1 Color R/G/Y － LED1 Color
R R R R R
R R R R R
R R R R R
R R R R R
R R R R R
 275 
6 F 2 T 0 1 7 9
Default Value
100A 200A 300A 400A 500A
R R R R R
1027 LED Color R/G/Y － CB LED Color
R R R R R
1028 V-LED Reset Inst - Latch － Virtual LED1 Reset operation Inst Inst Inst Inst Inst
1029 V-LED BIT1 0 - 3071 － Virtual LED1 Functions 0 0 0 0 0
1030 V-LED BIT2 0 - 3071 － ditto 0 0 0 0 0
1031 V-LED BIT3 0 - 3071 － ditto 0 0 0 0 0
1032 V-LED BIT4 0 - 3071 － ditto 0 0 0 0 0
1033 V-LED BIT5 0 - 3071 － ditto 0 0 0 0 0
1034 V-LED BIT6 0 - 3071 － ditto 0 0 0 0 0
1035 V-LED BIT7 0 - 3071 － ditto 0 0 0 0 0
1036 V-LED BIT8 0 - 3071 － ditto 0 0 0 0 0
1037 V-LED Reset Inst - Latch － Virtual LED2 Reset operation Inst Inst Inst Inst Inst
1038 V-LED BIT1 0 - 3071 － Virtual LED2 Functions 0 0 0 0 0
1039 V-LED BIT2 0 - 3071 － ditto 0 0 0 0 0
1040 V-LED BIT3 0 - 3071 － ditto 0 0 0 0 0
1041 V-LED BIT4 0 - 3071 － ditto 0 0 0 0 0
1042 V-LED BIT5 0 - 3071 － ditto 0 0 0 0 0
1043 V-LED BIT6 0 - 3071 － ditto 0 0 0 0 0
1044 V-LED BIT7 0 - 3071 － ditto 0 0 0 0 0
1045 V-LED BIT8 0 - 3071 － ditto 0 0 0 0 0
1046 Comms Modbus 1 - 247 － Relay ID No. for Modbus 1 1 1 1 1

1047 Comms Modbus2 1 - 247 － Relay ID No. for Modbus2 1 1 1 1 1
1048 Comms IEC 0 - 254 － Station address for IEC103 1 1 1 1 1
1049 Comms IEC2 0 - 254 － Station address for IEC103 2 1 1 1 1 1
1050 Comms RS485BR 9.6 - 19.2 － Baud rate for RS485 Port1 19.2 19.2 19.2 19.2 19.2
RS485 Baud rate for RS485 Port2
1051 Comms 9.6 - 19.2 － 19.2 19.2 19.2 19.2 19.2
BR2
1052 Comms IECBLK Normal - Blocked － Monitor direction blocked Normal Normal Normal Normal Normal
Off - Modbus - Protocol on RS485 Port1
1053 Comms RS485P － Modbus Modbus Modbus Modbus Modbus
IEC103
Off - Modbus -
1054 Comms RS485P2 － Protocol on RS485 Port2 Modbus Modbus Modbus Modbus Modbus
IEC103
Off-Modbus-DNP
1055 Comms EtherP － Protocol on Ethernet1 Modbus Modbus Modbus Modbus Modbus
-IEC61850
Off-Modbus-DNP
1056 Comms EtherP2 － Protocol on Ethernet2 Modbus Modbus Modbus Modbus Modbus
-IEC61850
1057 Test A.M.F. Off - On － Automatic monitoring function On On On On On
Disable / Enable VBLK in UV trip
1058 Test UVTST Off - On － -- -- Off Off Off
scheme.
Forcibly Reset of Thermal-θ
1059 Test RESET Off - On － Off Off Off Off Off
value.
1060 Test IECTST Off - On － IEC103 Test Mode Off Off Off Off Off
 276 
6 F 2 T 0 1 7 9
Appendix I
Commissioning Test Sheet (sample)
1. Relay identification
2. Preliminary check
3. Hardware test
3.1 User interface check
3.2 Binary input/Binary output circuit check
3.3 AC input circuit check
4. Function test
4.1 Percentage current differential element DIF test
4.2 2F-lock element check
4.4 High-set overcurrent element HOC test
4.5 Restricted earth fault element REF test
4.6 Overcurrent element test
4.7 Thermal overload element THR test
4.8 Frequency element FRQ test
4.9 Overexcitation element V/F test
5. Protection scheme test
6. Metering and recording check
7. Conjunctive test
 277 
6 F 2 T 0 1 7 9
1. Relay identification
Type Serial number

Model System frequency
Station Date
Circuit Engineer
Protection scheme Witness
Active settings group number
2. Preliminary check
Ratings
CT shorting contacts
DC power supply
Power up
Wiring
Relay inoperative
alarm contact
Calendar and clock
3. Hardware check
3.1 User interface check
3.2 Binary input/Binary output circuit check
Binary input circuit

Binary output circuit
3.3 AC input circuit check
 278 
6 F 2 T 0 1 7 9
4. Function test
4.1 Percentage current differential element DIF test
(1) Minimum operating value test
Tap setting Measured current
(2) Percentage restraining characteristic test
Tap setting I1 Measured current (I2)
× Ik
× Ik
(3) Operating time test
Tap setting Test current Measured time
4.4 High-set overcurrent element HOC test
(1) Minimum operating value test
Tap setting Measured current
Tap setting Test current Measured time
4.5 Restricted earth fault element REF test
Tap setting Ia Measured current (In)
× Ik
× Ik
 279 
6 F 2 T 0 1 7 9
4.6 Overcurrent element test
(1) OC element
Element Tap setting Measured current

OC
(2) EF element
Element Tap setting Measured current

EF
(3) OCI element
Element Test current Measured operating time

OCI 2 × Is
20 × Is
Is: Setting value
(4) EFI element

EFI 2 × Is
20 × Is
4.7 Thermal overload element THR test

THR
4.8 Frequency element FRQ test
(1) Frequency
Element Setting Measured frequency

FRQ-1
FRQ-2
DFRQ-1
DFRQ-2
 280 
6 F 2 T 0 1 7 9
(2) Undervoltage block
Setting Measured voltage
4.9 Overexcitation element V/F test
(1) Operating value test
Element Setting Measured voltage

V/F
Test voltage Measured operating time
5. Protection scheme test
Scheme Results
6. Metering and recording check
7. Conjunctive test
Scheme Results
On load
Tripping circuit
 281 
6 F 2 T 0 1 7 9
Appendix J
Return Repair Form
 282 
6 F 2 T 0 1 7 9
RETURN / REPAIR FORM

Please fill in this form and return it to Toshiba Corporation with the GRE160 to be repaired.
TOSHIBA CORPORATION Fuchu Complex

1, Toshiba-cho, Fuchu-shi, Tokyo, Japan
For: Power Systems Protection & Control Department
Quality Assurance Section
Type: GRE160 Model:

(Example: Type: GRE160 Model: 402A- 10-10 )
Product No.:
Serial No. :
Date:
1. Why the relay is being returned ?

 mal-operation
 does not operate
 increased error
 investigation
 others
2. Fault records, event records or disturbance records stored in the relay and relay settings are
very helpful information to investigate the incident.
So please inform us the information concerned in the incident with CD, or filling up the Fault
Record sheet and Relay Setting sheet attached.
 283 
6 F 2 T 0 1 7 9
Fault Record
Date/Month/Year Time / / / : : .
(Example: 04/ Nov./ 2012 15:09:58.442)
Faulty phase:
Prefault values (CT ratio: kA/: A, VT ratio: kV/: V)

Ia1: kA or A∠ ° Ia2: kA or A∠ °
Ib1: kA or A∠ ° Ib2: kA or A∠ °
Ic1: kA or A∠ ° Ic2: kA or A∠ °
I11: kA or A∠ ° I12: kA or A∠ °
I21: kA or A∠ ° I22: kA or A∠ °
I01: kA or A∠ ° I02: kA or A∠ °
In1: kA or A∠ ° In2: kA or A∠ °
Ia3: kA or A∠ °
Ib3: kA or A∠ °
Ic3: kA or A∠ °
I13: kA or A∠ °
I23: kA or A∠ °
I03: kA or A∠ °
In3: kA or A∠ °
V: kV or V∠ °
Ida: kA or A Id01: kA or A
Idb: kA or A Id02: kA or A
Idc: kA or A Id03: kA or A
Fault values (CT ratio: kA/: A, VT ratio: kV/: V)

Ia1: kA or A∠ ° Ia2: kA or A∠ °
Ib1: kA or A∠ ° Ib2: kA or A∠ °
Ic1: kA or A∠ ° Ic2: kA or A∠ °
I11: kA or A∠ ° I12: kA or A∠ °
I21: kA or A∠ ° I22: kA or A∠ °
I01: kA or A∠ ° I02: kA or A∠ °
In1: kA or A∠ ° In2: kA or A∠ °
Ia3: kA or A∠ °
Ib3: kA or A∠ °
Ic3: kA or A∠ °
I13: kA or A∠ °
I23: kA or A∠ °
I03: kA or A∠ °
In3: kA or A∠ °
V: kV or V∠ °
Ida: kA or A Id01: kA or A
Idb: kA or A Id02: kA or A
Idc: kA or A Id03: kA or A
 284 
6 F 2 T 0 1 7 9
3. What was the message on the LCD display at the time of the incident.
4. Please write the detail of the incident.
5. Date of the incident occurred.

Day/ Month/ Year: / / /
(Example: 10/ July/ 2012)
6. Please write any comments on the GRE160, including the document.
 285 
6 F 2 T 0 1 7 9
Customer
Name:
Company Name:
Address:
Telephone No.:
Facsimile No.:
Signature:
 286 
6 F 2 T 0 1 7 9
Appendix K
Technical Data
 287 
6 F 2 T 0 1 7 9
TECHNICAL DATA
Ratings
AC current In (primary and secondary): 1A / 5A (combined)
AC voltage Vn: 100-240V
Frequency: 50/60Hz
Auxiliary supply: 110 – 250Vdc / 100-220Vac
(Operative range: 88 – 300Vdc / 80 – 264Vac)
48－110Vdc (Operative range: 38.4 – 132Vdc)
24 – 48Vdc (Operative range: 19.2 – 60.0Vdc)
Superimposed AC ripple on DC supply: maximum 12%
DC supply interruption: maximum 50ms at 110V
Binary input circuit DC voltage: For alarm indication
110-250Vdc (Operative range: 88 - 300Vdc)
48-110Vdc (Operative range: 38.4 – 132Vdc)
24-48Vdc (Operative range: 19.2 – 57.6Vdc)
For trip circuit supervision
Operative range: ≥38.4V (for 110Vdc rating)
≥88V (for 220/250Vdc rating)
≥19.2V (for 48Vdc rating)
≥9.6V (for 24Vdc rating)
Overload Ratings
AC current inputs: 4 times rated current continuous
100 times rated current for 1 second 2 times rated continuous
AC voltage inputs: 2 times rated voltage continuous
Burden
AC phase current inputs: ≤ 0.3VA
AC earth current inputs: ≤ 0.3VA
AC voltage inputs: ≤ 0.1VA (at rated voltage)
Power supply: ≤ 10W (quiescent)
≤ 15W (maximum)
Binary input circuit: ≤ 0.5W per input at 220Vdc
Current differential protection (87T)
Minimum operate current (ik) OFF, 0.10 - 1.00pu in 0.01pu steps
Slope 1 (p1) for DF1 10 - 100% in 1% steps
Slope 2 (p2) for DF2 10 - 200% in 1% steps
kp 1.00 - 20.00pu in 0.01pu steps
Vector group compensation (d1 – d2) 0 to 11 (0 to 330deg in 30deg steps)
CT ratio (primary) 1 – 30000A in 1A steps
CT ratio (secondary) 1 – 30000A in 1A steps
Transformer Capacity 0.1 – 3000.0MVA in 0.1MVA steps
Voltage rating (primary) 0.4 – 500.0kV in 0.1kV steps
Voltage rating (secondary) 0.4 – 500.0kV in 0.1kV steps
Inrush setting (2nd harmonic ratio) (k2f) 10 to 50% in 1% steps
Overexcitation setting 10 to 100% in 1% steps
(5th harmonic ratio) (k5f)
Operating time typical 35ms (including BO operation time)
 288 
6 F 2 T 0 1 7 9
High-set differential overcurrent protection

Overcurrent (kh) OFF, 2.00 - 20.00pu in 0.01pu steps
Operating time typical 25ms (including BO operation time)
Restricted earth fault element (64/87G)
Minimum operating current OFF, 0.05 - 2.50pu in 0.01pu steps
Slope 1 (primary; 1p1, secondary; 2p1) 10 % (fixed)
Slope 2 (primary; 1p2, secondary; 2p2) 50 - 100% in 1% steps
1kp, 2kp (primary and secondary) 0.50 - 2.00pu in 0.01pu steps
CT ratio (primary;CT1, secondary;CT2) 1 – 30000A in 1A steps
CT ratio for neutral point 1 – 30000A in 1A steps
(primary ;CTn1, secondary ;CTn2)
Phase Overcurrent Protection (50P/N, 51P/N)
Definite time overcurrent element
Pick up level (OC, EF) OFF, 0.10 - 20.00pu in 0.10pu steps
Delay time (TOC, TEF) 0.00 - 300.00s in 0.01s steps
Reset time delay(TOCR,TEFR) 0.0 - 300.0s in 0.1s steps
Inverse time overcurrent element

Pick up level (OCI, EFI) OFF, 0.10 - 5.00pu in 0.01pu steps
Time multiplier (TOCM, TEFM) 0.010 – 15.000 in 0.001 steps
Reset Time multiplier (TOCRM, TEFRM) 0.010 – 15.000 in 0.001 steps
Delay type IDMTL (IEC 60255-151): IEC NI, IEC VI, IEC EI, UK LTI, IEEE MI,
IEEE VI, IEEE EI, US CO8 I, US CO2 STI
Thermal Overload Protection (49)

Iθ = k.IFLC (Thermal setting): OFF, 0.40 to 2.50pu in 0.01pu steps
Previous load current (IP) for testing 0.00 – 1.00pu in 0.01pu steps
Time constant (τ): 0.5 - 500.0mins in 0.1min steps
Thermal alarm: OFF, 50% to 100% in 1% steps
Negative Phase Sequence Protection (46)
Definite time overcurrent element
Pick up level (NC) OFF, 0.10 - 20.00pu in 0.10pu steps
Delay time (TNC) 0.00 - 300.00s in 0.01s steps
Reset time delay(TNCR) 0.0 - 300.0s in 0.1s steps
Inverse time overcurrent element

Pick up level (NCI) OFF, 0.10 - 5.00pu in 0.01pu steps
Time multiplier (TNCM) 0.010 - 1.500 in 0.001 steps
Reset Time multiplier (TNCRM) 0.010 - 1.500 in 0.001 steps
Delay type IDMTL (IEC 60255-151): IEC NI, IEC VI, IEC EI, UK LTI, IEEE MI,
IEEE VI, IEEE EI, US CO8 I, US CO2 STI
 289 
6 F 2 T 0 1 7 9
CBF Protection (50BF)

CBF threshold: OFF, 0.10 - 2.00pu in 0.01pu steps
CBF stage 1 DTL: 0.00 - 300.00s in 0.01s steps
CBF stage 2 DTL: 0.00 - 300.00s in 0.01s steps
Undervoltage Protection (27)
1st, 2nd Undervoltage thresholds OFF, 5.0 - 130.0V in 0.1V steps
st
Delay type (1 threshold only): DTL, IDMTL(complied with IEC 60255-127)
DTL delay 0.00 - 300.00s in 0.01s steps
IDMTL Time Multiplier Setting TMS: 0.05 – 100.00 in 0.01 steps
Reset delay 0.0 – 300.0s in 0.1s steps
Undervoltage block 5.0 - 20.0V in 0.1V steps
Overvoltage Protection (59)
1st, 2nd Overvoltage thresholds OFF, 10.0 to 200.0V in 0.1V steps
st
Delay type (1 threshold only): DTL, IDMTL(complied with IEC 60255-127)
DTL delay 0.00 to 300.00s in 0.01s steps
DO/PU ratio 10 – 98% in 1% steps
Reset Delay: 0.0 – 300.0s in 0.1s steps
Overexcitation Protection (24)
Pickup voltage 100.0 - 120.0V in 0.1V steps
Alarm level (A) 1.03 - 1.30pu in 0.01pu steps
High level (H) 1.10 - 1.40pu in 0.01pu steps
Low level (L) 1.05 - 1.30pu in 0.01pu steps
LT (Definite time) 1 - 600s in 1s steps
HT (Definite time) 1 - 600s in 1s steps
TVFH (Definite time) 1 - 600s in 1s steps
TVFA (Definite time) 1 - 600s in 1s steps
Start time less than 130ms
RT (Definite time) 60 - 3600s in 1s steps
Voltage Restraint Protection (51V)
Voltage threshold (OCV) 10.0 - 120.0V in 0.1V steps
Pick up level (OCVIS) 0.10 - 5.00pu in 0.01pu steps (available at OCVEN=Cont)
Time multiplier (TOCVM) 0.010 – 15.000 in 0.001 steps
Reset time(TOCVR) 0.0 – 300.0s in 0.1s steps
Reset Time multiplier (TOCVRM) 0.010 – 15.000 in 0.001 steps
Delay type IEC NI, IEC VI, IEC EI, UK LTI, IEEE MI, IEEE VI, IEEE EI,
US CO8 I, US CO2 STI
Frequency Protection (81U/O)
Overfrequency 50.00 to 60.00Hz in 0.01Hz steps (50Hz setting)
60.00 to 70.00Hz in 0.01Hz steps (60Hz setting)
 290 
6 F 2 T 0 1 7 9
Underfrequency 40.00 to 50.00Hz in 0.01Hz steps (50Hz setting)

50.00 to 60.00Hz in 0.01Hz steps (60Hz setting)
Delay time 0.00 to 300.00s in 0.01s steps
Frequency rate-of-change +0.1 to +15.0Hz/s in 0.1Hz/s steps
-0.1 to -15.0Hz/s in 0.1Hz/s steps
Operating time less than 100ms
Undervoltage blocking 40.0 - 100.0V in 0.1V steps
Accuracy
Current differential element: pick-up 100% of setting ±5%
Time-overcurrent protection: pick-up 100% of setting ± 5% (GS>0.2A)
Inverse Time Delays: IEC60255-151, ±5% or 50ms (2 ≤ G/GS ≤ 20)
GT = 1.1GS
GD = 20GS (GS ≤ 10A), 200A (GS > 10A)
≤50ms (DT, TMS=0s)
Instantaneous Time Delays ±5%
Voltage protection
Frequency protection: pick-up ±5%
Overexitation protection ±2% of pick-up voltage (frequency range 2%)
Front Communication port - local PC (USB2.0)

Connector type: Type B
Cable length: 5m (max.)
Rear Communication port - remote PC (RS485)
Connection: Multidrop (max. 32 relays)
Cable type: Twisted pair
Cable length: 1200m (max.)
Connector: Screw terminals
Isolation: 1kVac for 1 min.
Transmission rate: 19.2 kbps for Modbus RTU
Rear Communication port - remote PC (Ethernet)
100BASE-TX RJ-45 connector
100BASE-FX SC connector
Rear Time synchronizationport (IRIG-B port)
IRIG Time Code IRIG-B122
Input impedance 4k-ohm
Input voltage range 4Vp-p to 10Vp-p
Connector type Screw terminal
Cable type 50 ohm coaxial cable
Binary Inputs
Number 6 (x00 model) / 12 (x01 model) / 18 (x02 model)
Operating Voltage For alarm indication
Typical 154Vdc (min. 110Vdc) for 220Vdc rating
Typical 77Vdc (min. 70Vdc) for 110Vdc rating
Typical 33.6Vdc (min. 24Vdc) for 48Vdc rating
 291 
6 F 2 T 0 1 7 9
Typical 16.8Vdc(min. 12Vdc) for 24Vdc rating

For trip circuit supervision
≥88V for 220/250Vdc rating
≥38.4Vdc for 110Vdc rating
≥19.2V for 48Vdc rating
≥9.6V for 24Vdc rating
Binary Outputs
Number 4 (x00 model) / 10 (x01 model) / 16 (x02 model)
Ratings Make and carry: 5A continuously
for BO1 and BO2 CB control: Contact : 0.4A 250Vdc, 8A 380Vac, 3040VA, 150W
and for BO5 and BO6 (model x01) Make and carry: 30A, 250Vdc for 0.5s (L/R≥40ms)
and for BO11 and BO12 (model x02) Break: 0.1A, 250Vdc (L/R=40ms)
for other BOs Make and carry: 4A continuously
Contact: 0.2A 110Vdc, 8A 250Vac, 2000VA, 240W
Durability: Loaded contact: ≥1,000 operations
Unloaded contact: ≥10,000 operations
Pickup time: Less than 15ms
Reset time: Less than 10ms
Mechanical design
Weight 3.4kg (minimum configuration), 4.0kg (maximum configuration)
Case color Munsell No. 10YR8/0.5
Installation Flush mounting with attachment kits
CT requirement
The GRE160 does not require the use of dedicated CTs nor the use of CTs with an identical ratio.
The GRE160 can share the CTs with other protections and the different ratios are adjusted by
setting.
The general CT requirements are set for the through-fault stability which comes up when any CTs
saturate under very large through-fault currents. To ensure correct operation of the GRE160 for
such through-fault currents, the factor Ks of each CT is required to satisfy the following conditions:
Ks ≧ 1 when Tc ≦ 150ms
or
Ks ≧ 5 when Tc ≦ 200ms
where,
Ks = ratio of CT knee point voltage to CT secondary probable voltage under the maximum
through-fault current
= Vk / {(RCT + RL + RB + RO )(IFmax / CT ratio)}
Tc = d.c. time constant of primary circuit
Vk = knee point voltage of CT
RCT = resistance of CT secondary winding
RL = loop resistance of cable between CT and relay
RB = ohmic load of GRE160 (i.e. 0.1 ohm for 1A rating and 0.012 ohm for 5A rating)
 292 
6 F 2 T 0 1 7 9
RO = ohmic load of other series-connected relays (if any)

IFmax = maximum through-fault current
For example, if the following parameters are given:
Vk = 800 V, CT ratio = 1,200/1, RCT = 5.0 ohm, RL = 3.0 ohm, RB = 0.1 ohm,
RO = 0 ohm (i.e. no series-connected relays) and IFmax = 40kA
then the factor Ks is calculated as:
Ks = 800/{(5.0 + 3.0 + 0.1)×(40,000/1,200) }
= 800/270
= 3.0
This shows that the GRE160 operates correctly for all the faults under the condition that the d.c.
time constant of the primary circuit is less than 200ms.
 293 
6 F 2 T 0 1 7 9
ENVIRONMENTAL PERFORMANCE CLAIMS
Test Standards Details
Atmospheric Environment
Temperature IEC 60068-2-1/2 Operating range: -20°C to +60°C.
IEC 60068-2-30 Storage / Transit: -25°C to +70°C.
Humidity IEC 60068-2-78 56 days at 40°C and 93% relative humidity.
Enclosure Protection IEC 60529 IP52 (front), IP20 (rear), IP40 (top)
Mechanical Environment
Vibration IEC 60255-21-1 Response - Class 1
Endurance - Class 1
Shock and Bump IEC 60255-21-2 Shock Response Class 1
Shock Withstand Class 1
Bump Class 1
Seismic IEC 60255-21-3 Class 1
Electrical Environment
Dielectric Withstand IEC 60255-5 2kVrms for 1 minute between all terminals and earth.
IEEE C37.90.0 2kVrms for 1 minute between independent circuits.
1kVrms for 1 minute across normally open contacts.
High Voltage Impulse IEC 60255-5 Three positive and three negative impulses of
5kV(peak) for CT, Power Supply Unit (PSU), BI and BO
circuits; between terminals and earth, and between
independent circuits
3kV (peak) for RS485 circuit; between terminals and earth
3kV (peak) for BO circuit; across normally open contacts
1.2/50µs, 0.5J between all terminals and between all terminals
and earth.
Electromagnetic Environment
High Frequency IEC 60255-22-1 Class 3, 1MHz 2.5kV to 3kV (peak) applied to all ports in common mode.
Disturbance / Damped IEC 61000-4-12 1MHz 1.0kV applied to all ports in differential mode.
Oscillatory Wave IEEE C37.90.1
Electrostatic IEC 60255-22-2 Class 3, 6kV contact discharge, 8kV air discharge.
Discharge IEC 61000-4-2
Radiated RF IEC 60255-22-3 Class 3, Field strength 10V/m for frequency sweeps of 80MHz to 1GHz
Electromagnetic IEC 61000-4-3 and 1.7GHz to 2.2GHz. Additional spot tests at 80, 160, 450,
Disturbance 900 and 1890MHz.
Fast Transient IEC 60255-22-4 Class A, 4kV, 2.5kHz, 5/50ns applied to all inputs.
Disturbance IEC 61000-4-4,
IEEE C37.90.1
Surge Immunity IEC 60255-22-5, 1.2/50µs surge in common/differential modes:
IEC 61000-4-5 HV, PSU and I/O ports: 2kV/1kV (peak)
RS485 port: 1kV (peak)
Conducted RF IEC 60255-22-6 Class 3, 10Vrms applied over frequency range 150kHz to 100MHz.
Electromagnetic IEC 61000-4-6 Additional spot tests at 27 and 68MHz.
Disturbance
Power Frequency IEC 60255-22-7 Class A, 300V 50Hz for 10s applied to ports in common mode.
Disturbance IEC 61000-4-16 150V 50Hz for 10s applied to ports in differential mode.
 294 
6 F 2 T 0 1 7 9
Test Standards Details

Not applicable to AC inputs.
Conducted and IEC 60255-25, Conducted emissions:
Radiated Emissions EN 55022 Class A, 0.15 to 0.50MHz: <79dB (peak) or <66dB (mean)
IEC 61000-6-4 0.50 to 30MHz: <73dB (peak) or <60dB (mean)
Radiated emissions (at 10m):
30 to 230MHz: <40dB
230 to 1000MHz: <47dB
European Commission Directives
89/336/EEC Compliance with the European Commission Electromagnetic
Compatibility Directive is demonstrated according to generic
EMC standards EN 61000-6-2 and EN 61000-6-4.
73/23/EEC Compliance with the European Commission Low Voltage
Directive is demonstrated according to product safety standard
EN 60255-27.
 295 
6 F 2 T 0 1 7 9
Appendix L
Setting of REF Element
 296 
6 F 2 T 0 1 7 9
Type of transformer Scheme switch setting

[1REF] = 1I0
2ct-1
1ct-1 HV LV [2REF] = 1I0
1nC 2nC
1REF T T 2REF
In1 In2
1ct-1 HV LV 1REF = 1I0
1nCT
In1
1REF
 297 
6 F 2 T 0 1 7 9
Appendix M
Symbols Used in Scheme Logic
 298 
6 F 2 T 0 1 7 9
Symbols used in the scheme logic and their meanings are as follows:
Signal names
Marked with : Measuring element output signal
Marked with : Binary signal input from or output to the external equipment
Marked with [ ] : Scheme switch
Marked with " " : Scheme switch position
Unmarked : Internal scheme logic signal
AND gates
A A B C Output
B & Output 1 1 1 1
Other cases 0
C
A
A B C Output
B & Output 1 1 0 1
C Other cases 0
A
B A B C Output
& Output
1 0 0 1
C Other cases 0
OR gates
A A B C Output
B ≥1 Output 0 0 0 0
C Other cases 1
A
A B C Output
B ≥1 Output 0 0 1 0
C Other cases 1
A
A B C Output
B ≥1 Output 0 1 1 0
C Other cases 1
 299 
6 F 2 T 0 1 7 9
Signal inversion
A Output
A 1 Output 0 1
1 0
Timer
t 0 Delaye pick-up timer with fixed setting

XXX: Set time
XXX
0 t
Delayed drop-off timer with fixed setting
XXX: Set time
XXX
t 0 Delaye pick-up timer with variable setting

XXX - YYY: Setting range
XXX - YYY
0 t Delayed drop-off timer with variable setting

XXX - YYY
One-shot timer
A
A Output
Output
XXX - YYY
Flip-flop
S R Output
S 0 0 No change
F/F Output 1 0 1
R 0 1 0
1 1 0
Scheme switch
A Switch Output
A Output
1 ON 1
ON
Other cases 0
Switch Output
+ Output
ON 1
ON OFF 0
 300 
6 F 2 T 0 1 7 9
Appendix N
Implementation of Thermal Model to
IEC60255-149
 301 
6 F 2 T 0 1 7 9
Implementation of Thermal Model to IEC60255-149

Heating by overload current and cooling by dissipation of an electrical system follow exponential time
constants. The thermal characteristics of the electrical system can be shown by equation (1).
I2  −t 
θ = 2
1 − e τ  × 100% (1)
I AOL  
where:
θ = thermal state of the system as a percentage of allowable thermal capacity,
I = applied load current,
IAOL = kIB = allowable overload current of the system,
τ = thermal time constant of the system.
The thermal stateθis expressed as a percentage of the thermal capacity of the protected system, where 0%
represents the cold state and 100% represents the thermal limit, that is the point at which no further
temperature rise can be safely tolerated and the system should be disconnected. The thermal limit for any
given electrical plant is fixed by the thermal setting IAOL. The relay gives a trip output when θ = 100%.
If current I is applied to a cold system, then θ will rise exponentially from 0% to (I2/IAOL2 × 100%), with time
constant τ, as in Figure N-1. If θ = 100%, then the allowable thermal capacity of the system has been reached.
θ (%)
100%
I2 2 × 100%
I AOL
2 − tτ 
θ = I I 2 1 − e 

× 100%
AOL
t (s)
Figure N-1
A thermal overload protection relay can be designed to model this function, giving tripping times according
to the IEC60255-149 ‘Hot’ and ‘Cold’ curves.
 I2 
t =τ·Ln  2 2  (1) ∙∙∙∙∙ Cold curve
 I − I AOL 
 I2 − I 2 
t =τ·Ln  2 2P  (2) ∙∙∙∙∙ Hot curve
 I − I AOL 
 302 
6 F 2 T 0 1 7 9
where:
IP = prior load current.
In fact, the cold curve is simply a special case of the hot curve where prior load current IP = 0, catering for
the situation where a cold system is switched on to an immediate overload.
Figure N-2 shows a typical thermal profile for a system which initially carries normal load current, and is
then subjected to an overload condition until a trip results, before finally cooling to ambient temperature.
θ (%) Overload Current

Condition Trip at 100%
100%
Normal Load
Current Condition Cooling Curve
t (s)
Figure N-2 (1) Thermal Curve without Prior Load Current
θ (%) Overload Current

Condition Trip at 100%
100%
Cooling Curve
80%
Normal Load
Current Condition
t (s)
Figure N-2 (2) Thermal curve with Prior Load Current (θ=80%)
 303 
6 F 2 T 0 1 7 9
Appendix Q
Inverse Time Characteristics
 304 
6 F 2 T 0 1 7 9
IEC/UK Inverse Curves (NI) IEC/UK Inverse Curves (VI)

(Time Multiplier TMS = 0.1 - 1.5) (Time Multiplier TMS = 0.1 - 1.5)
100 100
10
10
Operating Time (s)

Operating Time (s)
TMS TMS
1.5 1 1.5
1.0
1.
0.5
0.5
1
0.2
0.1
0.2 0.1
0.1
0.1 0.01
1 10 100 1 10 100
Current (Multiple of Setting) Current (Multiple of Setting)
Normal Inverse Very Inverse
 305 
6 F 2 T 0 1 7 9
IEC/UK Inverse Curves (EI)

(Time Multiplier TMS = 0.1 - 1.5)
1000
100
UK Inverse Curves (LTI)

(Time Multiplier TMS = 0.1 - 1.5)
1000
10
Operating Time (s)
100
Operating Time (s)
1
TMS
TMS
10 1.5
1.5 1.0
1.0
0.5
0.1 0.5
0.2
1
0.1
0.2
0.1
0.01 0.1
1 10 100 1 10 100
Current (Multiple of Setting) Current (Multiple of Setting)
Extremely Inverse Long Time Inverse
 306 
6 F 2 T 0 1 7 9
Appendix S
Ordering
 307 
6 F 2 T 0 1 7 9
Ordering
Transformer Protection Relay
GRE160 0 A
Type:
Transformer Protection GRE160
Model (analog input):
2x three-phase CT 1
2x three-phase CT + 2 x zero-phase CT 2
2x three-phase CT + 1 x single-phase VT 3
2x three-phase CT + 2 x zero-phase CT 4
+ 1 x single-phase VT
2 x three-phase CT + 2 x zero-phase CT 5
+ 4 x single-phase VT
Model (binary input and output):
6 x BIs, 4 x BOs, 1 x Relay fail 0
Rating:
CT: 1/5A, f: 50/60Hz, 110-250Vdc / 100-220Vac 1
CT: 1/5A, f: 50/60Hz, 48-110Vdc 2
CT: 1/5A, f: 50/60Hz, 24-48Vdc A
Standard and language:
IEC (English) 0
Communication:
RS485 1port (Modbus/IEC 60870-5-103) 10
RS485 1port (Modbus/DNP3) 11
100BASE-TX 1port (Modbus/IEC 61850) A0
+RS485 1port (Modbus/IEC 60870-5-103)
100BASE-TX 1port (Modbus/IEC 61850/DNP3) A1
+RS485 1port (Modbus/DNP3)
100BASE-FX 1port (Modbus/IEC 61850) C0
+RS485 1port (Modbus/IEC 60870-5-103)
100BASE-FX 1port (Modbus/IEC 61850/DNP3) C1
+RS485 1port (Modbus/DNP3)
 308 
6 F 2 T 0 1 7 9
Version-up Records
Version Date Revised Section Contents

No.
0.0 Apr. 16, 2014 -- First issue
 309 

GRE160 Manual 6F2T0179-r0.0

Diunggah oleh

Informasi Dokumen

Judul Asli

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

GRE160 Manual 6F2T0179-r0.0

Diunggah oleh

Hak Cipta:

Format Tersedia

6 F 2 T 0 1 7 9

TRANSFORMER PROTECTION RELAY

© TOSHIBA Corporation 2014

Explanation of symbols used

• Fiber optic (option)

• Printed circuit board

3.2.3 Binary Output Signals 69

6.2 Cautions 168

The GRE160 provides the following metering and recording functions.

Table 1.1.1 Series Members and Functions

Model Number GRE160 -

Note: The model of “ _ “ is 0, 1or 2 for number of BO and BI.

2.1 Protection Scheme

Small Differential current Large

1OC/1OCI 1NOC/1NOCI CBF1 1OCV THM

2CT Calculate 3I0

2OC/2OCI 2NOC/2NOCI CBF2 2OCV

Figure 2.1.1 Measuring Elements

2.2 Current Differential Protection

Figure 2.2.1.2 Scheme Logic of Current Differential Protection

Display mode following differential tripping

5F-C 412 2REF2

Figure 2.2.1.3 Operating Phase and Faulted Phase Selection Logic

2.2.2 Stability for CT Saturation during Through-fault Conditions

Figure 2.2.2.1 Differential Element with CT Saturation Countermeasure

The algorithm of this element is given by the following equation:

2.2.3 Matching of CT Secondary Currents

Matching of CT ratio Matching of CT ratio

Figure 2.2.3.1 Matching Method

2.2.3.1 α-method phase matching

Ip1 Is1 Isb

Ipc Ipb Isc

2 Ipa − Ipb − Ipc Isa − Isc

Isa, Isb, Isc : Secondary side terminal current of transformer

2.2.3.2 Zero-sequence current elimination

Figure 2.2.3.2 External Earth Fault at the Star-connected side of a Transformer

2.2.3.3 Matching of CT Ratio

2.2.4 Connection between CT Secondary Circuit and the GRE160

(a) CT1POL setting “Object”(=0) and CT2POL setting “Object”(=0)

(b) CT1POL setting “Object”(=0) and CT2POL setting “Outside”(=1)

(c) CT1P0OL setting “Outside”(=1) and CT2POL setting “Object”(=0)

(d) CT1POL setting “Outside”(=1) and CT2POL setting “Outside”(=1)

Element Range Step Default Remarks

p1 10 − 100% 1% 100% % slope of small current region

Vn1 0.4-500.00kV 0.1kV 132kV Rated voltage at primary winding side

Setting of p1, p2 and kp

tap of the tap changer as a reference.

Setting for CT ratio matching

Figure 2.2.5.1 CT Ratio Matching

Example: Setting for star/delta transformer.

yd_p: Because the primary winding is star-connected, set 1.

Table 2.2.5.1 Phase Angle Matching Calculation

Table 2.2.5.2 Setting for Phase Angle Matching

Transformer connections Settings for phase angle correction Remarks

<How to set phase angle matching for GRE160>

Auto-transformer (with internal delta-winding)

2.3 Restricted Earth Fault Protection

Low-impedance Restricted earth fault protection

Figure 2.3.1 Restricted Earth Fault Protection

Figure 2.3.2 Block Diagram of REF

High-impedance Restricted earth fault protection

Figure 2.3.3 High Impedance REF

Figure 2.3.4 Scheme Logic of Restricted Earth Fault Protection