Aula

Introdução a Sistemas Digitais

VHDL

Parte 1: comandos concorrentes

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006
 Aula
Estrutura do VHDL 6

library library_name; 6 process(sinais)

use library_name.tipo; begin
7
entity name is 1 2 end process;
port(pino1 : in tipo;
pino2 : in tipo; process(clk)
pino3 : out tipo); begin
8
name end;

end process;
architecture name_tipo of name is
<declaração de componentes> 5
<outros comandos> 4
<declaração de sinais> 3 <instanciação de componentes;
begin
end;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 2 / 37
 Aula

7e8
Comandos Sequencias

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006
 Aula
Comandos Sequenciais 6

• Execução de acordo com a

ordem com que os comandos
sequenciais aparecem.
• Permitido apenas dentro da
estrutura process
• Usado para representar
algoritmos.

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 4 / 37
 Aula
Process 6
• Contem comandos sequenciais
• Existe apenas dentro da arquitetura
entity AND_OR_XOR is
• Todos os process rodam ao mesmo port (A,B : in bit;
tempo de maneira concorrente. Z_OR, Z_AND, Z_XOR : out bit);
• A execução dos process são end AND_OR_XOR;
controladas por: architecture RTL of AND_OR_XOR is
– Lista de sensibilidade (sinais begin

de trigger para a execução A_O_X: process (A, B)

do process), ou begin
Z_OR <= A or B;
– Comandos de wait Z_AND <= A and B;
Z_XOR <= A xor B;
• O label do process é opcional end process A_O_X ;

end RTL;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 5 / 37
 Aula
Comando: IF… then … else …. 6

if CONDITION then
-- sequential statements
end if;

A condição é uma
if CONDITION then
-- sequential statements
expressão booleana
else Opcional:
-- sequential statements -elsif
end if;
-else

if CONDITION then
-- sequential statements
elsif CONDITION then
-- sequential statements
···
else
-- sequential statements
end if;
Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 6 / 37
 Aula
IF Statement: Examplo 6

entity IF_STATEMENT is
port (A, B, C, X : in bit_vector (3 downto 0);
Z : out bit_vector (3 downto 0);
end IF_STATEMENT;

architecture EXAMPLE1 of IF_STATEMENT is architecture EXAMPLE2 of IF_STATEMENT is

begin begin
process (A, B, C, X) process (A, B, C, X)
begin begin
Z <= A;
if (X = "1111") then if (X = "1111") then
Z <= B; Z <= B;
elsif (X > "1000") then elsif (X > "1000") then
Z <= C; Z <= C;
end if; else
end process; Z <= a;
end EXAMPLE1; end if;
end process;
end EXAMPLE2;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 7 / 37
 Aula
Comando: CASE … is… WHEN …. 6

case EXPRESSION is
• Opções não podem ser
when VALUE_1 => coincidentes.
-- sequential statements
• Todas as opções devem
when VALUE_2 | VALUE_3 => ser cobertas:
-- sequential statements • valores simples
• intervalo de valores
when VALUE_4 to VALUE_N => • seleção de valores por
-- sequential statements ("|" que significa "or")
• uso obrigatorio de
when others =>
-- sequential statements
"when others" para
cobrir a(s) ultima(s)
end case ; opções.

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 8 / 37
 Aula
entity CASE_STATEMENT is
port (A, B, C, X : in integer range 0 to 15; 6
Z : out integer range 0 to 15;
end CASE_STATEMENT;

architecture EXAMPLE of CASE_STATEMENT is

begin
process (A, B, C, X)
begin
case X is
when 0 =>
Z <= A;
when 7 | 9 =>
Z <= B;
when 1 to 5 =>
Z <= C;
when others =>
Z <= 0;
end case;
end process;
end EXAMPLE;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 9 / 37
entity RANGE_2 is Aula
port (A, B, C, X : in bit_vector(3 downto 0); 6
Z : out bit_vector(3 downto 0);
end RANGE_2;

architecture EXAMPLE of RANGE_2 is

begin
process (A, B, C, X)
begin
case X is
when "0000" =>
Z <= A;
when "0111" | "1001" =>
Z <= B;
when "0001" to "0101" => -- wrong
Z <= C;
when others =>
Z <= 0;
A sequencia de valores é
end case;
indefinida para arrays.
end process;
end EXAMPLE;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 10 / 37
entity CONDITIONAL_ASSIGNMENT is Aula
port (A, B, C, X : in bit_vector (3 downto 0);
6
Z_CONC : out bit_vector (3 downto 0);
Z_SEQ : out bit_vector (3 downto 0));
end CONDITIONAL_ASSIGNMENT;

architecture EXAMPLE of CONDITIONAL_ASSIGNMENT is

begin
-- Concurrent version of conditional signal assignment
Z_CONC <= B when X = "1111" else
C when X > "1000" else
A;

-- Equivalent sequential statements

process (A, B, C, X)
begin
if (X = "1111") then
Z_SEQ <= B
elsif (X > "1000") then
Z_SEQ <= C;
else
Z_SEQ <= A;
end if;
end process;
end EXAMPLE;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 11 / 37
 Aula
Comando: FOR Loops 6

entity FOR_LOOP is
port (A : in integer range 0 to 3;
Z : out bit_vector (3 downto 0));
end FOR_LOOP;

architecture EXAMPLE of FOR_LOOP is

begin Se o LOOP é para ser
process (A) sintetizado, o intervalo do
begin loop não pode depender
Z <= "0000"; do valor de um sinal ou
for I in 0 to 3 loop variavel, ou seja, deve ser
if (A = I) then totalmente estático o
Z(I) <= `1`; intervalo.
end if;
end loop;
end process;
end EXAMPLE;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 12 / 37
 Aula
Loop Sintaxe 6

[LOOP_LABEL :]
for IDENTIFIER in DISCRETE_RANGE loop
-- sequential statements
end loop [LOOP_LABEL] ;

[LOOP_LABEL :]
while CONDITION loop
-- sequential statements
end loop [LOOP_LABEL] ;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 13 / 37
 entity CONV_INT is Aula
port (VECTOR: in bit_vector(7 downto 0); 6
RESULT: out integer);
end CONV_INT;

architecture A of CONV_INT is architecture B of CONV_INT is architecture C of CONV_INT is

begin begin begin
process(VECTOR) process(VECTOR) process(VECTOR)
variable TMP: integer; variable TMP: integer; variable TMP: integer;
variable I : integer;
begin begin begin
TMP := 0; TMP := 0; TMP := 0;
I := VECTOR'high;
for I in 7 downto 0 loop for I in VECTOR'range loop while (I >= VECTOR'low) loop
if (VECTOR(I)='1') then if (VECTOR(I)='1') then if (VECTOR(I)='1') then
TMP := TMP + 2**I; TMP := TMP + 2**I; TMP := TMP + 2**I;
end if; end if; end if;
end loop; end loop; I := I - 1;
end loop;
RESULT <= TMP; RESULT <= TMP; RESULT <= TMP;
end process; end process; end process;
end A; end B; end C;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 14 / 37
 Aula
Comando: WAIT 6

O comando wait' para a execução do process

– O process é continuado quando a instrução é completada.

– wait para um especifico tempo

– wait por um evento do sinal

– wait por uma condição verdadeira (necessita de um evento

do sinal)

– indefinido (process não é mais ativado)

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 15 / 37
 Aula
WAIT Statement: Examplos 6

entity FF is
port (D, CLK : in bit;
Q : out bit);
end FF;

architecture BEH_1 of FF is architecture BEH_2 of FF is

begin begin
process process
begin begin
wait on CLK; wait until CLK=`1`;
if (CLK = '1') then
Q <= D; Q <= D;
end if;
end process; end process;
end BEH_1; end BEH_2;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 16 / 37
 Aula
WAIT Statement: Examplos 6

STIMULUS: process
begin
SEL <= `0`;
BUS_B <= "0000";
BUS_A <= "1111";
wait for 10 ns;

SEL <= `1`;

wait for 10 ns;

SEL <= `0`;

wait for 10 ns;

wait;
end process STIMULUS;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 17 / 37
 Aula
6

READ_CPU : process
begin
wait until CPU_DATA_VALID = `1`;
CPU_DATA_READ <= `1`;
wait for 20 ns;
LOCAL_BUFFER <= CPU_DATA;
wait for 10 ns;
CPU_DATA_READ <= `0`;
end process READ_CPU;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 18 / 37
 Aula
Clocked Process:
6
Detecção da borda do Clock

if
clock_signal_ name'EVENT and clock_signal_ name='1'
clock_signal_ name='1' and clock_signal_ name'EVENT
not clock_signal_ name'STABLE and clock_signal_ name='1'
clock_signal_ name='1' and not clock_signal_ name'STABLE
RISING_EDGE ( clock_signal_ name)

IEEE 1076.6 is not fully supported by all tools

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 19 / 37
Clocked Process: Clock Edge Aula

Detection 6

wait until
•clock_signal_ name'EVENT andclock_signal_ name='1'
•clock_signal_ name='1' and clock_signal_ name'EVENT
•not clock_signal_ name'STABLE and clock_signal_ name='1'
•clock_signal_ name='1' and not clock_signal_ name'STABLE
•RISING_EDGE ( clock_signal_ name)
•clock_signal_ name='1'

IEEE 1076.6 is not fully supported by all tools

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 20 / 37
Detection of a Rising Edge by Use of Aula
Functions 6

• Defined in std_logic_1164 package

process
begin
wait until RISING_EDGE (CLK);
Q <= D;
end process;

function RISING_EDGE (signal CLK : std_ulogic)

return boolean is
begin
if (CLK`event and CLK = `1` and CLK`last_value = `0`) then
return true;
else
return false;
end if;
end RISING_EDGE;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 21 / 37
 Aula
Inferindo um Registrador 6
library IEEE;
use IEEE.std_logic_1164.all;
Elementos de memoria são inferidos, ou
entity COUNTER is seja, gerados sempre que os sinais
port (CLK: in std_logic; receberem assinalamentos dentro de
Q : out integer range 0 to 15 ); uma process controlado por relógio
end COUNTER; (clock)
COUNT: 4 flip flops
architecture RTL of COUNTER is
signal COUNT : integer range 0 to 15 ; Q: not used in clocked process
begin
process (CLK)
begin
if CLK`event and CLK = `1` then
if (COUNT >= 9) then
COUNT <= 0;
else
COUNT <= COUNT +1;
end if;
end if;
end process;

Q <= COUNT ;
Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 22 / 37
 Aula
Asynchronous Set/Reset 6
library IEEE;
use IEEE.std_logic_1164.all;

entity ASYNC_FF is
port (D, CLK, SET, RST : in std_logic;
Q : out std_logic);
end ASYNC_FF;

architecture RTL of ASYNC_FF is

begin
process (CLK, RST, SET)
begin
if (RST = `1`) then
Q <= `0`;
elsif SET ='1' then
Q <= '1';
elsif (CLK`event and CLK = `1`) then
Q <= D;
end if;
end process;
end RTL;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 23 / 37
 Aula
Clocked Process: Rules 6

process
begin
wait until CLK'event and CLK='1';
if RESET = '1' then Wait-form:
-- synchronous register reset no sensitivity list
else Synchronous reset
-- combinatorics
end if;
end process;

process(CLK, RST)
begin
if (RST = `1`) then If-form:
-- asynchronous register reset only clock and asynchronous
elsif (CLK`event and CLK=`1`) then signals (reset) in sensitivity list
-- combinatorics Synchronous and asynchronous
end if; reset
end process;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 24 / 37
 Aula

6
Bibliotecas IEEE para VHDL

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006
 Aula
Library IEEE 6

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.math_complex.all;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 26 / 37
 Aula
library IEEE;
6
use IEEE.std_logic_1164.all;

• The package std_logic_1164 provides enhanced signal types

• Types defined include:
• std_ulogic
• std_ulogic_vector
• std_logic
• std_logic_vector

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 27 / 37
 Aula
library IEEE;
6
use IEEE.std_logic_textio.all;

• The package textio provides user input/output.

• Types defined include:

• line
• text
• side
• width
• Functions defined include: readline, read, writeline, write, endline

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 28 / 37
 Aula
library IEEE;
6
use IEEE.std_logic_arith.all;

• std_logic_arith_syn.vhd defines types signed and unsigned and has

arithmetic functions that operate on signal types signed and
unsigned and std_logic_vector and std_ulogic_vector, but adding A
to B of std_logic_vector type, needs unsigned(A) + unsigned(B).

• std_logic_arith_ex.vhd has arithmetic functions that operate on

signal types std_logic_vector and std_ulogic_vector

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 29 / 37
 library IEEE; Aula

use IEEE.numeric_bit.all; 6

use IEEE.numeric_std.all

• The package numeric_bit provides numerical computation Types

defined include: unsigned signed arrays of type bit for signals

• The package numeric_std provides numerical computation Types

defined include: unsigned signed arrays of type std_logic for signals

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 30 / 37
 library IEEE; Aula
6
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all
• The package std_logic_signed provides signed numerical
computation on type std_logic_vector

• The package std_logic_unsigned provides unsigned numerical

computation on type std_logic_vector

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 31 / 37
 library IEEE; Aula

use IEEE.math_real.all; 6

use IEEE.math_complex.all;

• The package math_real provides numerical computation on type

real

• The package math_complex provides numerical computation Types

defined include: complex, complex_vector, complex_polar

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 32 / 37
 Aula

Uso de Variaveis em VHDL

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006
 Aula
Variaveis 6

• Variaveis são usadas apenas architecture RTL of XYZ is

signal A, B, C : integer range 0 to 7;
em processes
signal Y, Z : integer range 0 to 15;
– São declaradas antes do begin
begin do process process (A, B, C)
– Conhecidas apenas variable M, N : integer range 0 to 7;
localmente no process onde begin
M := A;
foram declaradas
N := B;
• VHDL 93: variaveis globais Z <= M + N;
– Não sintetizavel M := C;
Y <= M + N;
• Assinalamento global
end process;
– signal to variable end RTL;
– variable to signal
– types have to match

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 34 / 37
 Aula
Variaveis vs. Sinais 6

• Valores de sinais são assinalados depois da execução do process.

• Apenas o ultimo assinalamento é levado em consideração
• M <= A;
é sobre escrito por M <= C;
• A segunda entrada do somador é conectado a C.

signal A, B, C, Y, Z : integer; signal A, B, C, Y, Z : integer;

signal M, N : integer;
begin begin
process (A, B, C) process (A, B, C, M, N)
variable M, N : integer;
begin begin
M := A; M <= A;
N := B; N <= B;
Z <= M + N; Z <= M + N;
M := C; M <= C;
Y <= M + N; Y <= M + N;
end process; end process;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 35 / 37
 Aula
Uso de Variaveis 6

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 36 / 37
 Aula
entity PARITY is
port (DATA: in bit_vector (3 downto 0); 6
ODD : out bit);
end PARITY;

architecture RTL of PARITY is

begin
process (DATA)
variable TMP : bit;
begin
TMP := `0`;

for I in DATA`low to DATA`high loop

TMP := TMP xor DATA(I);
end loop;

ODD <= TMP;

end process;
end RTL;

Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt – 2006 37 / 37