Digital

Complex digital systems design
CHAPTER 2: INTRODUCTION TO
THE FPGAs
Departamento de Ingeniería Electrónica y Automática

Universidad de Jaén
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
Index
1. A brief review about digital logic gates
2. What is an FPGA?
3. Applications with FPGAs
4. FPGAs Vs. Processors
5. Pitfalls of FPGAs
6. Main manufactures on the market
7. How can we program an FPGA? VHDL Vs. Verilog
8. Extra material on Internet
1. A brief review about logic gates
 The most basic and elemental digital logic gate is the inverter which is built
from two MOSFET transistors: NMOS and PMOS.
 The layout defines all the masks necessary for creating the device.
 The inputs and outputs of digital circuits can only be 0 (low level) or 1 (high
level).
 Digital logic gates are defined by their table of truth

Asynchronous circuit
How fast is the response of an inverter?

The propagation delay is the length of The propagation delay will depend on the

time from the input change till the number and size of the capacitors to charge.
output consecutively also change
Propagation delay achieves values around ps or ns
CMOS technology allows to obtain complex logic gates only using MOSFET
transistors (resistors, capacitors or whatever else is not required).

What kind of logic
gate do we have ?
A B OUT?
0 0
0 1
1 0
1 1
CMOS technology offers to digital designers a paramount feature: scalability
Basic elements Only connections Adding inputs is easy

are needed
Every logic
function can be
implemented by
NANDs gates
All the processes
can be developed
automatically from
the basic elements
The simplicity of the CMOS technology and its low power consumption are
the clues of its rise.

NAND GATE (CMOS Technology) NAND GATE (TTL Technology)
Homework: take a look to your notes about logic gates

OR NOR
NAND
XOR XNOR
Last challenge...

What kind of digital logic gate do we have ?
A B OUT?
0 0
0 1
1 0
1 1
2. What is a FPGA?
The acronym of FPGA comes from Field Programmable Gate Array
INPUTS OUTPUTS
Any connection is implemented inside the chip these ones have to be program by the user
Proximity land Land motor

sensor Function 1 controller
The proximity sensor FPGA The land motor is

provides a 2 bits digital controlled by the FPGA:
output:

Proximity land Land motor

sensor Function 1 controller
FPGA
Water sensor
Function 2 Water motor
controller
Adding new functionalities
to the system is easy
Proximity
water sensor
Land motor
Proximity land controller
sensor Function 1
Function 2
Driving System
Water sensor FPGA
Function 3
Water motor
Proximity controller
water sensor
The FPGA can be separately
programmed and the overall
system will still exhibit a real
time response
4. FPGA Vs. Processor
Land motor
sensor Function 1
Function 2
Driving System
Water sensor FPGA
Function 3
Water motor
water sensor The FPGA's response
depend on the
propagation time and the
fanout.
For CMOS technology
fanout is ~34.000
Land motor
sensor Stack
Stack
Inst.1
pointer
Inst.2 Driving System
Water sensor Inst.3
Inst.4 Water motor
water sensor Memory The processor is limited by the
internal clock.
If the processor needs too
much time for an instruction or
Processor cluster of them, the system
stops being a realtime system
 XQVR4000XL FPGA by Xilink was used for the landing

XQVR1000 FPGA by Xilink was used for controlling
wheels motors, arms, cameras and instrumentation.
The Curiosity was lunched in 2011 and landed on Mars in The FPGA has the advantage that
2012 . Although, it was governed by a processor, some can be reprogrammed from afar.
specifics tasks were controlled by FPGAs
5. Pitfalls of FPGAs
 Expensive (academic: $300. Commercial $600)

 High power consumption
 Volatile, the configuration has to be saved
 High pin-in and pin-out
 Complicated (take a look to the data sheet)
 Complex CAD tools (Quartus II 1.5 GB !!)
 Difficult for programming: VHDL and Verilog are
not intuitive
6. Main manufactures on the market
Xilinx
 On the market from 1984 Altera. No longer on the market!!
Widely used for automotive, defence and

 On the market from 1984. Bought by Intel 2015
aerospace applications Widely used for industrial and academic
Popular series devices: Artix, Kintex, Virtex and purposes
Spartan  Popular series devices: Stratix and Ciclone.
FPGAs can be easily program thanks to HDL

(hardware description languages). This ones
allow to simulate and synthesise FPGA and ASICs
VHDL Evolution
Hardware program language created by U.S.
Defence Department for ASICs designs in 1981
 Intermetrix, IBM and TI create a baseline language
IEEE leaded the project and publish the first
standard in 1987
 The standard is revised each 5 year (or sooner)
VHDL is used mostly
in Europe, Korea and
Japan
Verilog is used in
North and South,
South-East Asia and
India
VHDL Verilog
 Strongly-typed  Weak-typed
 More verbose  More concise
 Very deterministic  only deterministic if you follow some rules carefully
 Non-C-like syntax  More C-like syntax
 Everything is exportable to Verilog  No everything is exportable to VHDL
8. Extra material on Internet
Videos to introduce you to the basics of FPGAs

 https://www.youtube.com/watch?v=gUsHwi4M4xE
 https://www.youtube.com/watch?v=CfmlsDW3Z4c
Complex digital systems design
CHAPTER 2:
ARCHITECTURE OF
PROGRAMMABLE LOGIC DEVICES
Departamento de Ingeniería Electrónica y Automática

Universidad de Jaén
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: 110AB. Email: jmunoz@ujaen.es
Index
1. Introduction
2. Origin and classification of the PLDs and CPLDs
3. Architecture of the FPGAs
3.1 Types of FPGAs´ architectures
3.2 Main blocks in FPGAs
3.2.1 Logic blocks (LBs)
3.2.2 Input/output blocks (I/O blocks)
3.2.3 Specific functional blocks in FPGAs
3.3 Interconnection in FPGAs
3.3.1 Interconnection lines
3.3.2 Programmable connections

Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. Introduction
The are two ways when a digital implementation has to be done:
1. A method based on a software solution
2. A method based on a hardware solution

1. Introduction
Software solution
 It is used electronic devises like processors or microcontrolers

(general purpose) which can be programmed by means of a list of
instructions. For a specific task there are devises with a shorter
number of instructions like DSPs
 This electronic devices present a limited number of functions
which are linked to the instructions available
 The programmer has to elaborate a program based on a
sequential list of instructions
 The internal hardware in terms of digital blocks will not change
by the programming

1. Introduction
Software solution

 Every processor has a similar structure in

terms of functional blocks. Some of them are:
*) Control unit (instructions executing, bus
access, etc.)
*) ALU (arithmetic logic unit)
*) Memory program
1. Introduction
Software solution
 The power of processor to handle and solve difficult tasks
is limited by
*) The sequential feature of its execution
*) The number of instructions is limited

1. Introduction
Hardware solution
 The resolution of the problem involves the reaching of

a final logic function which will be synthesised by logic
gates (NOR or NAND for example)
 The designer has to define all the gates and the
interconnections between them (pitfall)
 The circuit has an only one purpose but theoretically it
is faster than the solution implemented by software.

1. Introduction
Hardware solution
The hardware solution of a digital problem can be

coped by three different methodologies:
 By using a discrete number of standard logic gates

and establishing the connections between them:
Ladder logic
 By means of an applicationspecific integrated circuit
(ASIC)
Semifull custom
Full custom
 By a programmable logic device (PLD), complex
programmable logic device (CPLD) or field
programmable field array (FPGA)
1. Introduction
Ladder logic Hardware solution

 Large number of pins and interconnections

 Large PCBs
 Obsolete. Only use for industrial application
(automatisms) and didactic purpose
1. Introduction
ASIC Hardware solution

 Very specific, very powerful with a low power consumption

 Difficult to implement because it is almost a handmade process
 Very expensive only for specific tasks
1. Introduction
Hardware solution
PLD and FPGA

 The group of PLDs can be chronologically  The FPGAs are an evolution of the PLDs
divided into the following categories : and could be included inside the group of
complex programmable logic devices
PROMs PALs PLAs GALs (CPLDs)
PROMs PALs PLAs GALs

Encoder
0 0 0  The programmable read only memories
(PROMs) appeared in 1956.
000 1
001 0  The PROMs is a logical device with n
010 0
address inputs and m data output.
011 0
100 0
101 0
 The PROMs consists of a decoder + one-
110 0 only programmable array + encoder.
111 0
 Although the PROMs were design to work
as a memory (specially for bootstrapping)
Decoder their features allow any logical function to
0 1 0 1 be synthesised
Burnt or blown fuse
F1 F2 F3 F4

HOW DOES WORK?
 The anti-fuses are the elements which
establish the connections according to the
wished logical function to implement
Problem: PROMs are not erasable


EPROMs EEPROMs
 The erasable programmable read-only  The electrical erasable programmable read-
memories (EPROMs) was invented 1971 only memories (EEPROMs)
and presented the advantage that could be
erased applying UV light .
Floating gate
The burning is made by an electrical field applied

The UV light ionise the device removing the stored
charge
Interesting reading: transient radiation effect on electronics

 Are we really used all the minterms at the input? The PALs tries to solve this problem
Fixed array
000 Programmable array

001
010
011
100
101
110
111
PROM
Fixed array
Programmable array
 The programmable array

logic (PAL) appeared on the
market in 1978 and were
extensively used
 The PAL16L8 was a very popular
device which came in a 20 DIP
package
PAL16L8
How does
work?
 The PAL devices manufactures provided some software tool in

order to program their chips:
 PALASM (PAL- Assembler) was written in FORTRAN IV for
an IBM 370/168
 CUPL (Compiler for Universal Programmable Logic)
 ABEL ( Advanced Boolean Expression Language )
All of them represent the origin of VHDL

 The programmable logic arrays (PALs) allow the “AND plane” and the “OR
plane” be programmed by the designer
Programmable Programmable
array array
 More functionality for the

designer

 The Generic Array Logic (also known as GAL) devices were an innovation of
the PAL and was invented by Lattice Semiconductor.
 One of the advantages of the GALs from their predecessors was that GALs
were electrical erasable.
 GALs displayed
GAL 22V10 design
improvements to
handle the input and
output
Macro-Cells

Clock
 Each Macro-Cell could be configured by the user to be combinational or

registered, active high or active low
 The GAL 22V10 displays the possibility to build for example a shift register due to they
allow signal clock and cascade configurations to be implemented.
 Registered mode
S0= 0 S0= 1
S1= 0 S1= 0
 Combinatorial mode
S0= 0 S0= 1
S1= 1 S1= 1
3. Types of FPGAs´ architectures
Types of FPGAs´ architectures
Logic blocks in FPGAs

- Configurable logic blocks
- Input/output blocks
- ASIC
Interconnection in FPGAs
- Interconnection lines
- Programmable connections
3.1 Architecture of the FPGAs
The FPGAs can be classified from a point of view of their internal

architecture and layout as follows:
According to the placing of the According to the placing of the connections lines
connections lines and logic blocks
 Channelled  Terrace architecture
 Manhattan architecture
 Channel-less
 Sea of Gates
architecture
Terrace architecture
 Advantages: less delay,

less area and more simple.
 Disadvantages: less
functionality, less flexible
when the LB have to work
together
Manhattan architecture
 Advantages: More flexible,

more powerful when are
necessary a big number of
LB
 Disadvantages: More
delay.
Sea of gates architecture
 Advantages: low delay

and low area of silicon
 Disadvantages:
technological
manufacturing
3.2.1 Logic blocks in FPGAs
Configurable logic blocks

 Design to execute logic tasks
 Simple or complex
ASIC (application specific

integrate circuit)
According to the number and complexity of

the logic blocks we will speak about:
 Fine granularity: high number of simple logic
blocks LBs able to execute easy tasks
 Coarse granularity: Low number of complex
logic blocks able to execute difficult tasks
WARNING: each brand uses its own nomenclature which can even depend
on the FPGA series.
ALTERA
 Simple logic blocks : Logic Elements (LEs)
 Complex logic blocks: Logic Array Blocks
(LABs -Cyclon III-), Adaptive Logic Module
(ALM -Cyclon V-)
XILINX
 Simple logic blocks : Logic blocks (LB)
 Complex logic blocks (Virtex II): Slice
(composed by 4 LB), Configurable Logic
Block (CLB, composed by 4 slices) .
 In other families (Spartan): SLICEL,
SLICEM, , SLICEX
Configurable logic blocks
Simple logic blocks Complex logic blocks

 Based on discrete number of  Based on non universal
CMOS transistors combinational logic gates
(e.g. Multiplexers)
 Based on logic gates
 Based on universal
combinational logic circuits
(Look up table)
Simple logic blocks. Based on discrete number of CMOS transistors
The FPGAs from the family CK20K (currently obsolete) by Croospoint has
this configuration based on 2 lines of transistors (PMOS and NMOS) call
Transistor Pair Tile


Transistor Pair Tile (CK20K by Crosspoint)
GATE 1? ? GATE 2?


Transistor Pair Tile (CK20K by Crosspoint)
Good example of
terrace
architecture
Simple logic blocks. Based on logic gates
These type of logic blocks are based on a combinational functions

implemented by logic gates. The logic blocks can be configured depending on
the stated of the control signals.
Simple logic blocks. Based on logic gates
The family XC8100 by Xilinx has the possibility to define 4 different kinds of
combinational functions depending on two control signals
How many
data inputs?
Obtaining more complex

functions is made by using
cascade configurations
Simple logic blocks. Based on universal combinational logic circuits
Most of the FPGAs available on the market implement an enhanced version

of the Logic Block which can be shown in the Figure below. They are mainly
based on Look-Up tables (LUTs)
LUT: Look-up table

FA: Full adder
DFF: D flip-flop

Look-Up Table, in general terms is basically a table that determines what the
output is for any given input(s). In the context of combinational logic functions,
it corresponds to truth table. This truth table effectively defines how your
combinatorial logic behaves
A LUT is a logic element with
a unique output.
Building a LUT with X inputs
X1 implies to use:
f
X2 
2X memory cells
X3 
X levels of multiplexers
Level 1 → 2X/2

Level 2 → 2X/4

2X-1 multiplexers are
needed
Erasable memory element (SRAM)
What kind of logic gate is

implemented with this 2 input LUT?
X1
Draw the internal design of a 3 input
f
X2 LUT configured for implementing a
X3 NAND gate
Simple logic blocks. ALTERA / QUARTUS EXAMPLE

This is a combinational function implemented in practical sessions:
How is this function

implemented in the
FPGA ?
RTL Viewer gives you a

schematic implemented by
logic gates
Post-Mapping provided an
specific implementation for
the FGPA serie
Post-Fitting provided an
specific implementation for
the model of the FGPA inside
the serie.

Post-Mapping result
Quartus provides tools in order to

identify how many logic elements are
in use and their location in the FPGA
Just a Logic Element (LE) is necessary

to implement the function:
It is possible to track
down the physical
implementation till
arrive inside the Logic
Elements
Quartus II provides tools

to know what is the level
of resources utilised
after compiling.
A full adder is a logical circuit that performs an addition operation on three

one-bit binary numbers. The full adder produces a sum of the two inputs and
carry value
Bypass
The full adder is a useful resource which allows arithmetic operations (sums,
products, counters and so on) to be done by the logic block
Complex logic blocks. Based on non universal combinational logic circuits

The Eclipse family by QuickLogic implemented a
logic block named Logic SuperCell based on
logic gates, multiplexers and filp-flops.
Features:
 The 17 simultaneous inputs.
 6 outputs;
Logic
SuperCell  4 combinatorial functions
from Eclipse
family by  2 Flip-flops
QuickLogic
 Fine granularity
No longer
on the The single level of logic delay provides a faster
market from response compare to other architectures which
2010 require two or more levels of delay
Logic blocks from ALTERA
Altera calls their logic blocks Logic Elements which are implemented using a
standard architecture based on lookup tables + adder + flip-flop
Logic
Element
from
Cyclone II
family by
Altera
For FPGAs by Altera the LUT

includes the full adder
For Cyclone family the LEs are gathered in blocks of 16 LEs named Logic Array Blocks (LABs)

 LAB Carry Chain: Enables fast
Logic
adders by providing fast
Element
from Cyclone interconnect between adjacent
II family by LABs
Altera
 Register Chain: Enables fast shift
registers by providing fast
registered connection between
parallel Les
 Register Packing: Combines
register with combo Logic
 Register Feedback: Feedback
from Flip-Flop output back to 4 LUT
Operating modes:
 Normal: combinational/sequential
 Arithmetic: Adders, counters, so on
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE11
LE12
LE13
LE14
LE15
LE16
Typical Manhattan architecture of the Cyclone II family by Altera

Logic blocks from Xilinx
Logic Cell Xilinx calls their logic blocks as logic cells.

For Spartan II family the slices are
implemented using logic cells composed by
lookup tables, adder and flip-flop.
Logic Cells (LC)

(LUT+FA+FF)
Slice from
Spartan II
family by
Xilinx Slice
(composed by 2 LC for Spartan II)
Configurable logic Block (CLB)

Slice (composed by 2 slices for Spartan II)
Logic blocks from Xilinx
Logic Cell in  LUTs support both logic and

detail from memory (including both RAM16
Spartan III and SRL16 shift registers)
family by Xilinx
 Simple fast and complete
Logic Cells (LC)
arithmetic logic
(LUT+FA+FF) Divided tasks inside the CLB:
 2 slices are dedicated for memory
Slice and logic functions (SLICEM)
(composed by
2 LC)  2 slices are dedicated for logic
functions only (SLICEL)
CLB
composed by
4 slices
3.2.2 Input/Output blocks in FPGAs
Main functionality features

 Input/output (I/O, hereafter) blocks
provide an interface among the internal
FPGA's circuits and the external
environment
 I/O terminals can be configured as an
input, output or bidirectional port
 D flip-flops are usually included inside
the I/O blocks to provided registered
inputs and/or inputs.
Nomenclature
 Altera: input-output element (IOE)
 Xilinx: input-output cell (I/O cells)
 Lattice: Programmable I/O Cell (PIC)
Main elements of an I/O block
The tristate control will define the operation of the The output buffer will adapt the output to
output buffer the output standard used (TTL, LVTTL
LVCMOS, PCI, etc.) or to set the line in
high impedance. The output also
incorporates flip-flops.
Connection to the external

environment (~2-4 pF)
The input buffer will enhanced the input signal and will join the
external input into the connection resources of the FPGA
passing through optional delays or flip-flops
FPGAs packaging types
Field-programmable gate arrays are available in a variety of IC package types and with
different numbers of pins and flip-flops. Usual IC package types for field-programmable
gate arrays are listed below:
 Ball grid array (BGA) Very popular nowadays
 Quad flat package (QFP)
Advantages
1) High density (hundreds of pins)
2) Low thermal resistance (better cooling)
3) Low-inductance leads and parasitic capacitances
Disadvantages
1) Inflexible (problems related to thermal stress)
2) Difficulty of inspection (X-ray or boundary scan)
3) Without reliable sockets for development
4) Equipment cost
Main elements of an I/O block (General overview)
The figure describes the main blocks of I/O cell from XC4000 family by Xilinx
3 Output stage:
1) Programmable buffer
2) Direct/registered output through FF
1
3) Slew Rate Control
2
A
Input stage:
A) Input buffer
C B B) Programmable delay
C) Direct/registered output through FF
Main elements of an I/O block (Programmable output buffer)
The FPGA is able to adapt the output buffer depending on the

technology of the device connected afterwards. Different I/O standards
The existed I/O standards are identified by the power supply and 4 remarkable voltages
and their margin noise values:
Different I/O standards are identified by the power supply and 4 remarkable voltages:
TTL inverter
CMOS inverter
For Cyclone II a huge range of I/O standards could be used but, what is the reason of
this evolution regarding the fall of the voltage supply and also the margines noise?
P∝f2
P = I x V = I x ( VDD -VSS )
Main elements of an I/O block (Slew-rate control)
What is the Slew Rate?
Slew rate is the maximum voltage change per unit time in a
node of a circuit (typically the output), due to limited
current sink or source
What is the Slew Rate?
Rise time (tr ): The time required for the output to go

from 10% (20%) of the Logic "1" level to 90% (80%) of
the Logic "0" level
Fall time (tf ):The time required for the output voltage
to go from 90% (80%) of the Logic "1" level to 10%
(20%) of the Logic "0" level
Propagation delay (tpd ): Propagation delay of a gate,

net or bus is the time it takes for a signal at the input
pin to affect the output signal at output pin. The tpd is
usually measured as the time it takes between 50 % of
input rising to 50 % of output rising
Example 1
A digital circuit -which implements a double CMOS inverter- is exited with a 400 ps width
square wave at the input. The wave form is registered at the output, obtaining the
following measurements:
 Represent the output and the input signal
tr = 80 ps tpd= 35 ps
 Find the slew-rate of the output line
tf = 80 ps
Example 2
Find if an FPGA which implements a LVCMOS-3.3V standard output and displays a SR= 20
V/ns can be used for a application where a time rise of 30 ps is needed
The slew rate can be controlled for the Cyclone family by Altera
High slew-rate → Shape wave forms → High number of harmonics → EMI increasing
Medium slew-rate → Soft wave forms → Control of the harmonics → EMI controlling
Low slew-rate → no-shape wave forms → is it a 0 or 1? → Metastability
I/O blocks in commercial FPGAs (Cyclone II family by Altera)
The most remarkable features according to

the manufacturer’s data sheets are listed
below:
More information and details on:

https://www.altera.com/support/support-resources/operation-and-testing/io/io-features.html
Tri-state control line stage
(Cyclone II family by Altera)
1
2
3
2
4
2
5 5
1,3
4 6
6
output stage
1 Different I/O standards (LVTTL, LVCMOS, etc), slew-rate and current strength
2 Weak pull-up resistor to set the output to 1 by default
5
3 Tri-state buffer to isolate the output stage
4 Bus-hold circuitry very useful to keep the last state of the bus
5 Programmable delays to avoid to minimise set-up times
6 Open-drain output enables the device to provide system-level control signals
Input stage 7 Clamp diode for protection and adjustment of the logic levels
Clamp diodes
Clamp diodes are used for adding protection against harmful inputs although
they can be also used to adapt the voltage input levels.
Suitable for low bit rate

communications
Suitable for high bit rate

communications
Overshoot demising
because of clamp diodes
Programmable I/O delays
A delay setting in an I/O path affects the timing requirement on that pin. Use
programmable delay to improve the read or write timing in an interface.
Quartus II development software automatically programs these delays if you constrain the input or
output port. Use the set_input_delay or set_output_delay command with the TimeQuest timing analyzer
I2C Protocol. An example of open drain output
The undriven pins have to be avoided at all cost s due to line noise could
produce an unexpected 0 or 1. The I2C protocol bus set by default the
line to a high logic level by means a pull-up resistor.
The elements involve in the communication can only set the data or
clock line to zero by means a open drain output.
Arduino, Raspberry Pi,

PIC 16F88, and so on
implement this protocol
Let go to see a
transmission example
I2C Protocol. An example of open drain output
A B
1 1,0,1,0,1,0
0 0,1,0,1,0,1
1 0 Wake up!!
0 1 0 0
0 0 0 0
Disengage port (IDLE) The master takes the control
0 0 (start bit)
0 0
C You talkin' to me? You talkin' to me?
D
1,0,1,0,1,0 1,0,1,0,1,0
0,1,0,1,0,1 0,0,0,0,0,0,0,1 0,1,0,1,0,1 0

0
1,1,1,1,1,1,1,0 0,0,0,0,0,0,0,1 0,0,0,0,0,0,0,1 0
0 0 1 0
The master identifies the The slave responds (ACK)
0 0 0 0
slave to write (0) or reed (1)
Finally, it is me Dream on...
(Cyclone II family by Altera)
The I/O pins on Cyclone II devices are grouped

together into I/O banks and each bank has a
separate power bus.
Each device I/O pin is associated with one I/O

bank. In the case of the Cyclone II EP2C35
there are eight I/O banks as is shown in the
figure
Each I/O bank has its own VCCIO pins. A

single device can support 1.5-V, 1.8-V, 2.5-V,
and 3.3-V interfaces; each individual bank
can support a different standard with different
I/O voltages. Each bank also has dual-
purpose VREF pins to support any one of the
voltage-referenced
Cyclone II family by Altera. Quartus II tools for I/O pins assignment
The I/O pins assignment in Cyclone II can be modified and checked by the tool Pin Planner
Pin planner (Quartus II)
The Pin Planner provided a

graphical way to reassigning the
pins
Each pin is denoted by its

coordinates (row and column).
The symbol used will indicate the
purpose of the pin.
Pins are gathered in Banks.

Cyclone II included in
development board DE2 has
8 I/O banks
The I/O standard can be
configured for each bank:
Tri-state control line stage
(Spartan II family by Xilinx)
1 Different I/O standards are supported (LVTTL, LVCMOS, etc)

and slew-rate
2 7
1,3
output stage 4
5 6
2 Pull-up and pull-down resistor network
3 Tri-state buffer to isolate the output stage
4 Keeper latch circuitry to hold the last state of the bus
5 Programmable delays to avoid to minimise setup times
6 Vref pins to define a user-supplied threshold voltage for 1 logic input
Input stage 7 Protection against damage from electrostatic discharge (ESD) and over-voltage
(Spartan II family by Xilinx)
The I/O pins on Spartan II by Xilinx are

grouped together into 8 I/O banks which output
standard can be configured by the user:
Each I/O bank has its own VCCIO pins. Each

bank also has dual-purpose VREF pins to
support any one of the voltage-referenced
Most of the commercial FPGAs have and unspecific number of functional blocks which
carry out particular tasks. Some of this blocks could be implemented using standard
logical blocks however, the use and inclusion of these functional blocks made the
process more efficient.
Some of the most common specific functional blocks included in the commercial FPGAs
available on the market are listed below:
RAM memory Multipliers DSPs PLLs
RAM memory
The RAM (random access memory) memory is included by the manufactures to provide
an easy way to have a element to store information which will be used during the
processes carried out by the FPGA.
The RAM memory can be implemented by logic blocks using the SRAM included in the
LUT. But, it is technically a waste of resources because the size of the built RAM is small
2m x n
Size (bits) of data stored by the memory
Size (bits) of the address
CLK Number of addressable storage units
Random access memory
Whatever address can be directly selected

Example
Considering the schematic of the following SRAM find: 2m x n
1) Size of the word stored
2) Size of the address bus ?
3) Size of the data bus
?
4) Number of addressable words
?
RAM memory
RAM memories can be divided into single port or dual port memories depending on
the possibility of accessing to a memory address at the same time by two different paths.
✓ Memory Density (8 kb, 64 kb, 128 kb, 512 kb...)

✓ Maximum Access Time (from 3.3 ns to 65 ns)
✓ Working frequency
Single ✓ Power supply needed
Port
CLK
Port 1
SRAM cell memory
Port 2
Dual port memories need more MOSFETs per memory cell thus, the area needed is higher. However, they allows a double access memory
RAM memory
Depending on the need to refresh the memory or not, RAM memories can be divided into
DRAM (dynamic RAM) or SRAM (Static RAM).
SRAM: if the power supply turns off the information will be lost although it is not needed
to refresh the memory to hold the information
DRAM: if the power supply turns off the information will be lost but, in addition it is
necessary to refresh the memory to hold the information
DRAM cell memory
Depending on the synchronism established according to the system clock for reeding or writing on the
memory, RAM memories can be divided into SDR SRAM and DDR SRAM.
SDR SDRAM: The data will be read or write according to the positive-going transition (raising edge) of the
clock
DDR SDRAM: The data will be read or write according to the positive-going and negative-going transition
(rising and falling edge) of the clock. Double Data Rate compare to SDR RAM
RAM memory blocks on the market for expansion sockets
RAM memory in commercial FPGAs (Cyclone II family by Altera)
The Cyclone II embedded memory consists of

columns of M4K memory blocks. The most
remarkable features of theses SRAM units
according to the manufacture data sheets are
listed below:
Complete the following table for the different ram memory configurations for
Cyclone II
Address BUS Addressable words Length word
Common applications using the RAM available

in FPGAs:

Memory for embedded processors (NIOS II)

Rd/Wr data for arithmetic computations (FIR filters)

Direct Digital Synthesis (DDS)

Long or width shift registers

Programmable delays

Circular Buffers (FIFO buffer)
RAM memory in commercial FPGAs (Spartan II family by Xilinx)
The FPGAs from Xilinx have RAM memory

blocks of 4096-bit which are organised in
columns. All Spartan-II devices contain two
such columns, one along each vertical edge.
SRAM Memory
Memory blocks can be configured as single or

dual port
RAM memory in commercial FPGAs (Spartan II family by Xilinx)
The memory blocks present at the Spartan II FPGA family can be configured to
obtain different ranges of width (bits for word) and depth (number of words) as it
happens for FPGAs by Altera
2m x n
Size (bits) of data stored by the memory
Size (bits) of the address
Number of addressable storage words
MULTIPLIERS
The digital signal processing (DSP) are based on two digital blocks: multipliers and
adders. Both digital functions can be implemented by logic blocks however, the
implementation of these devices by logic block implies a high cost of resources.
The new FPGAs available on the market include multipliers or more complex logic
blocks able to process signals (adding and multiplying) such as DSPs
Xilinx included this specific Altera included this specific

logic blocks: logic blocks:
- From Virtex IV - From Stratix II
- From Spartan III - From Cyclone II
- For all the 7-series by Xilinx
MULTIPLIERS
The multipliers are usually placed close to the memory blocks for minimising the
input/output delay. For the family Cyclone II by Altera the multipliers operate with two
factors (A and B) of 18 bits expressed in two's-complement representation. The product
result (P) is a 36 bits data expressed in two's-complement representation as well.
Digital Multiplier from Cyclone II family by Altera
(1) Soft Multipliers: Implemented by the SRAM memory available

MULTIPLIERS
Digital multipliers are widely used for radio transmission For AM modulation, the carrier
signal can be implemented by digital direct synthesis (DDS) while the modulating signal
is digitalised by an analog to digital converter (ADC). The signal to transmit (before the
RF power amplifier) is converted by a digital to analog converter (DAC).
MULTIPLIERS
1101 00000000
As the adders present in the logic blocks, the
multiplexers can be built using several ways. The shown
method uses shift left registers, adders and
multiplexers.
1
1101
X 1011 11010 1101
1101
11010 1
100111 100111
110100
0000
100111 0
1101000
1101000 100111
10001111
1
Another ways to implement a multiplier: http://www.andraka.com/multipli.php 10001111

DSPs
The digital signal processing blocks (DSPs) are logic block whose
architecture is optimised for the operational needs of digital signal processing.
Xilinx included DSPs in theirs high capacity an ALTERA included DSPs from Cyclone III
performance FPGAs (included from 2010 in and in Stratix family
Virtex IV)
DSPs
DSPs can be consider as a microprocessor with a short list of instructions
focused on a specific arithmetical operations and with a low consumption
compare to a common processor.
Arithmetic-Logic Unit DSP from

Virtex 4/5
Multiplier family by Xilinx
A Virtex 5 FPGA could have Accumulator

till 1056 DSPs which can
work in parallel at 550MHz.
Manufactures offer specific

software to program the DSP
from Matlab-Simulink files.
DSPs applications
Machine vision (MV) refers to both industrial and non-industrial applications where
operational guidance is provided to equipment for the execution of functions based on
the capture and analytical processing of images (Embedded Machine Vision, Printers,
Scanners, Currency, Smart Cameras and Large scale inspection)
Avionics and defence including single and multicore ARM, DSP, and ARM+DSP, are
well-suited to defence and avionics applications including radar, electronic warfare,
avionics, and software defined radios (SDR).
Video encoding and decoding. Providing power and cost-efficient, high-density

programmable video coding solutions
Biometrics. DSPs are widely used for biometric applications such as iris or fingerprint
biometric
PLLs
FPGAs have dedicated hardware to generate the clock signals. The most
common used device for this purpose is the Phase-Lock Loop (PLL).
General overview of the

The PLLs are part of more complex layout from Cyclone II
clock structures, for example: family by Altera
XILINX: Digital clock managers (DCM)
ALTERA: Clock Control Block
The number of DCMs or Clock Control

Blocks will depend on how large the
FPGA is. The larger Cyclone II devices
have 16 clock control blocks. The
smaller Cyclone II devices have four
clock control blocks.
PLLs (Altera: clock control blocks)
The number of Clock Control Blocks will depend on how large the FPGA is. The larger Cyclone II
devices have 8 clock control blocks (4 for each side). The smaller Cyclone II devices have 4 clock
control blocks (2 for each side).
Cyclone II model Cyclone II models

EP2C15 EP2C35 & EP2C8
PLLs
The PLL is a device utilised to regenerate the clock signal and avoid the
possible delays that could appear as a result of the rutting
Skew: it is a phenomenon in which the same

sourced clock signal arrives at different
components (generally latches or flip-flops) at
different times.
The clock signals of the

FPGA are regenerated General
according to the overview clock
CLKSWITCH control block
from Cyclone II
family by Altera
PLLs
PLL is a closed-loop frequency-control system based on the phase difference

between the input clock signal and the feedback clock signal of a controlled
oscillator.
PFD: phase frequency detector N: pre-scaler counter

VCO: voltage controlled oscillator C: post-scaler counters
M: feedback counter
Block diagram of a
PLL circuit
PLLs (XILINX: Digital clock managers DCM)
The Digital Clock Manager (DCM) are the blocks used by Xilinx to regenerate and
establish the clock signal of the system. Their main features are listed below
1) Suppress the clock skew 3) Suppress the clock skew, rebuild the signal and
adapt the input clock signal to a different standard
2) Multiply or divide the clock signal (LVTTL, LVDS and so on)
3
General overview
of a DCM by Xilinx
PLLs (XILINX: Digital clock managers DCM)
The clock signal uses dedicated interconnections lines where their placement in the
overall layout of the FPGA is very specific in order to avoid delays.
Buffer
Clock Buffers are used to establish a
distribution suitable clock level. Buffers and
from Spartan DCMs have dedicated lines to be
family by Xilinx connected to each other and avoid
the transitions delays
Buffer Buffer
Buffer
PLLs and Clock signals in VHDL
The are several rules of thumb which must be followed to avoid problems related
to the clock signal: glitch
Glitch: it is an undesired transition that occurs before the signal settles to its intended value
Imagine that situation where the designer decided to hold the flip-flop output asynchronously:
CLK
Enable BAD DESIGNED
The glitch is a problem that appears when there is some delay charge on the clock signal and
and as a result there is an unexpected output.
PLLs and Clock signals in VHDL
The are several rules of thumb which must be followed to avoid problems related
to the clock signal: glitch
As a rule of thumb the clock signal must not be charged with any extra delay. In other words, the
clock lines have to go from the clock block managers to the logic blocks without passing through
any combinational function.
Enable
Process (clk)
WELL DESIGNED Begin
If (reset= '1') then
.....................
elseif ( rising_edge (clk) ) then
X<= '0';
CLK Take
Y<=X;
care
F<=Y;
.........
Wrong elseif ( rising_edge (clk) ) then
3.3 Interconnection resources in FPGAs
Main functionality features

 The interconnection resources allow to
connect the logic blocks between them
and with the input output blocks.
 The higher the number of
interconnection lines are, the better is
the flexibility of the FPGA although the
propagation delay will be also higher
There are two elements which conform

the interconnection resources:
 Interconnection lines
 Configurable connections
3.3 Interconnection resources in FPGAs
Interconnection lines
Configurable
connections
The interconnection lines are made of metal segments and provided a

physical way for the electrons across the FPGA.
Local lines Global lines

Local lines are those ones used to These lines span the entire length or
interconnect adjacent logic blocks width of the interconnection area, being
(eg. carry) direct lines to avoid the delay (eg clock)
The table below lists the number and characteristics of the available
interconnections for a complex logic block (CLB) for the Virtex 2 family by Xilinx
3.3.2 Configurable connections
The configurable connections allow the

global and/or local lines to be
connected.
Depending on the kind of lines to attach
the physical junction will be done by
multiplexers or pass-transistors
 Connections between global lines

and local lines are implemented by
multiplexers in Cyclone II family by
Altera.
The control terminal line of the
multiplexer is accessible by the
synthesiser which executes the
routing
3.3.2 Configurable connections
The pass-transistors are the element used to implement the connections between
global vertical and horizontal lines

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Complex digital systems design

Departamento de Ingeniería Electrónica y Automática

The propagation delay is the length of The propagation delay will depend on the

Basic elements Only connections Adding inputs is easy

Proximity land Land motor

The proximity sensor FPGA The land motor is

Proximity land Land motor

 XQVR4000XL FPGA by Xilink was used for the landing

 Expensive (academic: $300. Commercial $600)

Widely used for automotive, defence and

FPGAs can be easily program thanks to HDL

Videos to introduce you to the basics of FPGAs

Departamento de Ingeniería Electrónica y Automática

1. A method based on a software solution

2. A method based on a hardware solution

 It is used electronic devises like processors or microcontrolers

 Every processor has a similar structure in

 The resolution of the problem involves the reaching of

The hardware solution of a digital problem can be

 By using a discrete number of standard logic gates

 Large number of pins and interconnections

 Very specific, very powerful with a low power consumption

PROMs PALs PLAs GALs

PROMs PALs PLAs GALs

Problem: PROMs are not erasable

PROMs PALs PLAs GALs

The burning is made by an electrical field applied

PROMs PALs PLAs GALs

000 Programmable array

PROMs PALs PLAs GALs

 The programmable array

PROMs PALs PLAs GALs

 The PAL devices manufactures provided some software tool in

PROMs PALs PLAs GALs

 More functionality for the

PROMs PALs PLAs GALs

PROMs PALs PLAs GALs

 Each Macro-Cell could be configured by the user to be combinational or

Types of FPGAs´ architectures

Logic blocks in FPGAs

The FPGAs can be classified from a point of view of their internal

 Channelled  Terrace architecture

 Advantages: less delay,

 Advantages: More flexible,

Sea of gates architecture

 Advantages: low delay

Configurable logic blocks

ASIC (application specific

According to the number and complexity of

Configurable logic blocks

Simple logic blocks Complex logic blocks

Simple logic blocks. Based on discrete number of CMOS transistors

Simple logic blocks. Based on discrete number of CMOS transistors

Simple logic blocks. Based on discrete number of CMOS transistors

Simple logic blocks. Based on logic gates

These type of logic blocks are based on a combinational functions

Simple logic blocks. Based on logic gates

Obtaining more complex

Simple logic blocks. Based on universal combinational logic circuits

Most of the FPGAs available on the market implement an enhanced version

LUT: Look-up table

Simple logic blocks. Based on universal combinational logic circuits

Simple logic blocks. Based on universal combinational logic circuits

What kind of logic gate is