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This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2717541, IEEE
Transactions on Power Electronics

Modular Multilevel Converter Control Strategy


Based on Arm Current Control under Unbalanced
Grid Condition
Zhujian Ou, Guangzhu Wang, Member, IEEE

Abstract — The existing control strategies of modular capacity, lower switching frequency, lower output harmonics,
multilevel converter (MMC) balance the capacitor voltage modular design and so on. Thus it is suitable for medium/high
on the premise that the active power of ac-side is balanced voltage applications, such as high-power motor drives [2], [3],
with that of dc-bus. Thus, the symmetrical ac-side current unified power flow controller (UPFC) [4], grid connected
references and the unevenly distributed dc current inverter [5], high voltage direct current transmission (HVDC)
references in three legs are obtained by coordinate [6]-[23]. However, it has demerits as capacitor voltage
transformation, precise calculation and numerous filters balancing and circulating current.
under unbalanced grid condition. However, by controlling Multiple modulation strategies are applied as the bottom-
capacitor voltages, the active powers between ac-side and level modulation strategies to balance the capacitor voltage,
dc-bus can self-regulate to balance, and this could simplify such as phase disposition pulse width modulation (PD-PWM)
the obtainment of ac-side current references and dc bus [6], [7], nearest level modulation (NLM) [8]-[10] and phase-
current references. Based on this idea, this paper proposed shifted carriers pulse width modulation (PSC-PWM) [17]-[20].
a control strategy which combines the multi-hierarchy Based on these modulation strategies, conventional ac-side
control with the arm current control for MMC under current feedback control method applied in two-level converter
unbalanced grid condition. Within the multi-hierarchy is adopted in MMC [3]-[17]. However, since the ac-side
control, the symmetrical ac-side current references and the current is only the summation of the upper and the lower arm
unevenly distributed dc current references in three legs currents, simply controlling ac-side current will leave the
could be obtained easily by three voltage controllers in abc current component with opposite polarity in the upper and the
coordinate, avoiding coordinate transformation, precise lower arms uncontrolled, e.g., circulating current. Thus, the
calculation and numerous filters in the existing methods. circulating current suppressing controllers are designed.
Besides, the employment of the arm current control Under unbalanced grid condition, the control of MMC is
removes the need of the three-sequence ac-side current more complex. Symmetrical ac-side currents and zero power
controllers and the three-sequence circulating current ripples in dc-bus can be achieved simultaneously because the
suppressing controllers. The proportional regulator with a capacitors in MMC could absorb all the active power ripples in
feedforward steady state duty cycle is designed for arm ac-side. To control MMC properly, the following controllers
current regulator, which can perfectly track its reference are indispensable. Firstly, the dual vector current control
and is easy to design, avoiding the complicated design of scheme (DVCC) is needed to eliminate the negative-sequence
PR controllers. Both system-level simulation results and current in ac-side [6], [11], [12]. Secondly, the zero-sequence
low-level experiment results verify the feasibility and current canceller is need for ac-side in event of asymmetrical
effectiveness of proposed strategy. faults on the converter side of the transformer or in a
Index Terms—Arm current control, Circulating current, transformer-less scheme [12], [13]. Thirdly, circulating current
Modular multilevel converter (MMC), Multi-hierarchy suppressing controllers should be designed to eliminate the
control, Unbalanced grid condition.1 three-sequence circulating currents [13]-[16]. Under
unbalanced grid condition, the dc current is no longer
I. INTRODUCTION averagely distributed among three legs, and this increases the
The MMC was introduced by A. Lesnicar and R. Marquardt difficulty to extract the circulating current from the arm current
in 2003 [1]. This converter possesses merits as upgraded [16], [21]-[23]. What’s more, dc-bus voltage ripple suppressing
controller is needed [11], [13]. However, since ac-side power
ripples are manifested as the zero-sequence circulating currents,
Author Contact Information: the dc-bus voltage ripple suppressing controller can be
1) Dr. Zhujian OU removed if circulating currents are well suppressed [16],
Mailing address: School of Electrical Engineering, [21]-[23]. The comprehensive control is rather complicated
Shandong University, 17923 Jingshi Road, Jinan, China, when conventional ac-side current feedback control is applied
250061.E-mail: zj_ou89@163.com Tel:86-18660136202 under unbalanced grid condition [21], [22].
2) Dr. Guangzhu WANG (Corresponding author) However, the arm current contains all the current messages
Mailing address: School of Electrical Engineering, in MMC, including three-sequence ac-side currents, dc bus
Shandong University, 17923 Jingshi Road, Jinan, China, current and three-sequence circulating currents. Controlling the
250061.E-mail: sdwgz@sdu.edu.cn Tel: 86-13964065132 arm current will realize the control of the above currents [19].
Conference Presentation: Partly presented at the 5th International The comprehensive control strategy based on arm current
Conference on Electric Utility Deregulation and Restructuring and control was first given in reference [20]. However, the strategy
Power Technologies (DRPT), Changsha, China, November 26-29,
in [20] is not suitable for unbalanced grid condition because
2015.

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Transactions on Power Electronics

none of the control targets in [22] is satisfied. Reference [21]


proposed the MMC control strategy based on arm current
control under unbalanced grid condition. This paper focused
on eliminating the active power ripples of ac-grid and adopted
the PIR controllers as the arm current controller. However, the
ac-side currents in this paper are seriously asymmetrical,
which will cause the protective devices malfunction [13].
Reference [22] proposed a PI plus VPI controller, which has a
better performance and stability margin than the PIR controller.
In [23], authors in this paper presented two control strategies
based on arm current control for MMC under unbalanced grid
condition. This paper is inadequate in analysis and short of
experiment results. To the authors’ best knowledge, all the
control strategies proposed for unbalanced grid condition until
now were verified only by simulations, and short of
experiment verification.
The capacitor is a key component in MMC. The existing
control strategies including ac-side current feedback control
and arm current control both balance the capacitor voltages on
the premise that the active power of ac-side is balanced with
that of dc-bus. In this situation, the ac-side current references Fig. 1. Basic structure of MMC.
are precisely calculated by the active power and reactive power
references in dq SRF with coordinate transformation [12], [13], lower arm of a phase form a leg. Each arm is constituted by N
[16], [21], [22], and the dc current references in three legs of submodules (SMs) connected with an inductor L. upx and unx
MMC are calculated by the measured ac-side voltages and (x=a, b, c) are respectively output voltages of the upper and the
currents with three low-pass filters [21], [22]. However, by lower arms. ipx and inx are respectively the upper and the lower
controlling the capacitor voltages, the active powers between arm currents. usx and isx are respectively the ac-side voltage and
ac-grid and dc-bus can self-regulate to balance, and this could current. Ud and Id are respectively dc bus voltage and current.
simplify the obtainment of the symmetrical ac-side currents The capacitor of SM is the only energy-storage element
and the unevenly distributed dc currents in three legs. Based on except arm inductor in MMC. When an arm absorbs active
this idea, this paper analyzed the active power in MMC, and power, the voltages of arm capacitors will rise. When an arm
proposed a comprehensive control strategy combined the arm outputs active power, the voltages of arm capacitors will fall.
current control with the multi-hierarchy control for MMC Thus the voltages of arm capacitors can be controlled if active
under unbalanced grid condition. In this strategy, the ac-side power absorbed by an arm is controlled. In order to elicit the
currents are controlled to be symmetrical by adjusting active control strategy and choose appropriate control variables for dc
power distribution among three legs. The symmetrical ac-side bus and capacitor voltages, power analysis is done firstly.
current references and the unevenly distributed dc current In steady state, ignoring the influences of arm inductances,
references in three legs are obtained by average voltage the relationship of voltages can be obtained as follows.
controllers of three legs in abc frame, avoiding the coordinate u px  U d 2  usx
transformation, precise calculation and numerous filters in the  (1)
u nx  U d 2  usx
existing methods. Besides, the employment of the arm current
control removes the need of the three-sequence ac-side current The upper and the lower arm currents ipx and inx satisfy
controllers and the three-sequence circulating current ipx  ispx  idiffx  ispx  I dx  icir _ x
suppressing controllers. The proportional regulator with a  (2)
inx  isnx  idiffx  isnx  I dx  icir _ x
feedforward steady state duty cycle is applied for arm current
regulator, which perfectly tracks its reference. Both simulation where ispx and isnx are parts of ac-side current; idiffx is the inner
and experiment results verify the feasibility and effectiveness unbalanced current, containing dc current component Idx and
of the proposed strategy. the circulating current icir_x. Relationship between ac-side
The rest of this paper is organized as follows. In Section II, current and arm currents satisfies
power analysis of MMC is done to elicit the control strategy isx  ipx  inx  ispx  isnx (3)
and to choose appropriate control variables for dc bus voltage Dc bus current Id satisfies the following equation.
and capacitor voltage. Detailed control strategies are shown in 1
Section III, including arm current control, multi-hierarchy I d   ipa  ina    ipb  inb    ipc  inc    I da  I db  I dc (4)
2
control and the comprehensive control strategy. Simulations
Currents ispx, isnx, Idx and icir_x satisfy
and experiments are respectively presented in Section IV and V.
 T U i dt  0
 0 d spx
Section VI concludes this paper.
II. POWER ANALYSIS OF MMC  T
 0 U d isnx dt  0
Basic structure of MMC is shown in Fig. 1. Each phase  T
contains an upper arm and a lower arm. The upper arm and the  0 U d icir _ x dt  0 (5)
 T
 usx icir _ x dt  0
 0
 T
 0 usx I dx dt  0

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Transactions on Power Electronics

where T is the period of ac-gird. Thus, (6) can be derived from


the law of energy conservation according to (5).
Psx  Pdx  Ppx  Pnx (6)
where Psx is the active power absorbed from ac-grid; Pdx is the
active power flowing into dc-bus; Ppx and Pnx are respectively
the active power absorbed by the upper and the lower arms of
MMC. Each power can be expressed as
 1 T
 Psx  T 0 usx isx dt
 (7)
 P  1 T U I dt
 dx T 0 d dx
 1 T 1 T Ud 1 T
 Ppx   T 0 upx ipx dt   T 0 2 I dx dt + T 0 usx ispx dt Fig. 2. Single phase equivalent circuit of MMC.
 (8)
 P  1 T u i dt   1 T U d I dt + 1 T u i dt
 nx T 0 nx nx T 0 2
dx
T 0
sx snx

A. Two Control Strategies


If device loss of MMC is ignored, i.e.,
Ppx  Pnx  0 (9)
then the active power absorbed from ac-grid and output to dc
bus by MMC should be equivalent. For convenience, (10) is
shown in the form of phase a, b, c.
 1 T 1 T
 Psa  Pda  T 0 usa isa dt  T 0 U d I da dt Fig. 3. Arm current control scheme.

 1 T 1 T
 Psb  Pdb  0 usb isb dt  0 U d I db dt (10)
 T T
 1 T 1 T
 Psc  Pdc  T 0 usc isc dt  T 0 U d I dc dt

Under unbalanced grid condition, ac-grid voltage will be
asymmetrical. On this basis, two control strategies of MMC
could be deduced from (10).
1) Strategy one: Ensure Ida=Idb=Idc=Id/3, whereas isa, isb, isc
are asymmetrical. Fig. 4. Arm current controller design method.
Since Ida=Idb=Idc, according to (10), relationships among
active powers should satisfy suitable for both balanced and unbalanced grid conditions.
Pda  Pdb  Pdc  Psa  Psb  Psc  B. Control Variables for Dc-Bus Voltage and Capacitor
1 T 1 T 1 T (11) voltage
 usa isa dt   usb isb dt   usc isc dt
T 0 T 0 T 0 From (7), active power issued from ac-grid can be regulated
According to (11), since usa, usb, usc are asymmetrical, by adjusting ac-side active currents; if dc bus voltage keeps
ac-side currents isa, isb, isc will be asymmetrical too. Protective constant, active power transmitted to dc bus can be regulated
devices may malfunction if relatively serious negative-, or by adjusting dc current.
zero-sequence currents are detected [13]. Thus, this strategy is From (8), average active powers of the upper and the lower
not suitable for unbalanced grid condition. However, it works arms are constituted by two parts. The first part is relevant to
well under balanced grid condition. Idx; the second part is relevant to ispx and isnx. By controlling
2) Strategy two: Ensure isa, isb, isc are symmetrical, whereas either Idx or ispx and isnx can realize the control of Ppx and Pnx,
I da  I db  I dc . thus controls capacitor voltages.
In general case, ispx and isnx are set equal, that is
If isa, isb, isc are controlled to be symmetrical, then active
ispx  isnx  isx 2 (13)
power absorbed by three legs of MMC from ac-grid will be
unequal since usa, usb, usc are asymmetrical, then exists However, when taking asymmetrical device loss of the
Psa  Psb  Psc  Pda  Pdb  Pdc  upper and the lower arms into consideration, there should be a
fine-tuning of ac-side current distribution in the upper and the
1 T 1 T 1 T lower arms, thus ∆isxP in (14) is introduced. The frequency and
 U d I da dt   U d I db dt   U d I dc dt  (12)
T 0 T 0 T 0 phase angle of ∆isxP are the same as usx and satisfy
I da  I db  I dc 1 T 1 T
Ppx  Pnx   usx  ispx  isnx  dt   usx isxP dt (14)
On the basis of not affecting Id, adjusting dc current T 0 T 0
distribution among three legs of MMC can realize the In fact, device loss differences exist among all submodules
adjustment of active power distribution among three legs, thus of an arm, so fine-tuning of active power of each submodule
the ac-side currents can be controlled to be symmetrical. should be designed or the NLM should be adopted to realize
Thereby, power relationship in (12) is realized. This strategy is the balance of capacitor voltages within an arm.

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Transactions on Power Electronics

Fig. 5. Dc bus voltage control. Fig. 7. Voltage control between the upper and the lower arms.

Fig. 6. Average voltage control of a leg.


Fig. 8. zero-sequence current canceller.
III. CONTROL METHOD
A. Arm Current Control Method
Fig. 2 shows the single phase equivalent circuit of MMC. In
Fig. 2, the upper and the lower arms are similar and are almost
independent of each other, thus the upper and the lower arm
currents ipx and inx can be controlled directly by corresponding
PWM duty cycles. From (3) and (4), ac-side currents and dc
bus current can be controlled only if arm currents are
controlled. At the same time, it does not require a circulating
current suppressing controller.
Arm current control scheme of MMC is shown in Fig. 3. In
Fig. 3, Uc is the rated voltage of capacitor; ipxref and inxref are
respectively the upper and the lower arm current references of Fig. 9. Proposed control strategy for MMC.
phase x; uN0 is the zero-sequence voltage, and it could be
uN0  0.5  max  usa , usb , usc   min  usa , usb , usc   (15) eipx  j1   iprefx  j1  43 (20)

Dpx and Dnx in Fig.3 are steady state PWM duty cycles of the As for sin wave with frequency of 100Hz, ω2=200π (e.g.,
circulating current),
upper and the lower arms used as feedforward variables; d pxctrl
eipx  j2   iprefx  j2  22 (21)
and d nxctrl are duty cycles output by the upper and the lower
The steady state errors are small enough in practice.
arm current controllers; dpx and dnx are PWM duty cycles of the
upper and the lower arms. Duty cycles satisfy B. Control of Dc Bus Voltage and Capacitor Voltage
d px  Dpx  d pctrl
x
Strategy two in II-A-2) is adopted here to control the MMC
 (16) under unbalanced grid condition.
ctrl
d nx  Dnx  d nx 1) Dc Bus Voltage Control: From (10), active power flowing
where into dc bus and absorbed from ac-grid of each phase are
 0.5U d  (usx  uN0 ) u  uN0 equivalent. Thus, controlling ac-side current isx could indirectly
 Dpx   0.5  sx control dc bus voltage. If so, the magnitudes of ac-side currents
 NU c NU c
 (17) references can be set identical directly. Combined with the
 D  0.5U d  (usx  uN0 )  0.5  usx  uN0 control in the following III-B-2), the ac-side currents could be
 nx NU c NU c controlled to be symmetrical automatically under unbalanced
Arm voltages are controlled by applying modulation method grid condition. So ac-side current isx is chosen to control dc bus
(e.g. PSC-PWM, NLM, etc.) with the duty cycles in (16). as shown in Fig. 5. In Fig. 5, Pdctrl is the output active power of
The detailed design procedure of arm current regulator controller, UsN is the RMS value of ac-side phase voltage, Isctrl
xP
refers to [19]. Different from [19], calibrating the closed-loop
control diagram in Fig. 4(a) as the one in Fig. 4(b), the current is the RMS value of ac-side active current reference.
controller could be a proportional controller as in (18). Taking active power balance between ac-side and dc bus
L into consideration, Pdctrl could be used as a feedforward signal
WIR  s   K i  (18) of dc component of arm current to improve the dynamic
3Td NU c
property, i.e.,
where Td is the time delay of control system. From Fig. 4(b),
I FFW  Pdctrl  3U d  (22)
steady state error is expressed in (19).
1 2) Capacitor Voltage Control: Multi-hierarchy control is
eipx  j   iprefx  j  (19) adopted to balance capacitor voltage.
KI The first hierarchy is average voltage control of a leg, which
1+
j  jTd  1 keeps capacitors’ average voltage of a leg balanced with its
In experiments of this paper, Td=25us, KI=1/(3Td). For sine rated value. Since isx is chosen to control dc bus voltage, Idx is
wave with frequency of 50Hz,ω1=100π. Put it into (19), then chosen to control capacitor voltage here. In this situation, dc
the steady state error is obtained as current (namely power) distribution among three legs of MMC

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Transactions on Power Electronics

will be automatically adjusted according to the active power


absorbed from ac-grid by each leg. Taking the feedforward
signal in (22) into consideration, average voltage control of a
leg is shown in Fig. 6. In Fig. 6, U cx is the average voltage of
leg x; U cref is the corresponding reference value; Pxctrl
P is the
Fig. 10. Grid fault scheme in the simulation.
output of controller; I dxctrl is the dc current reference of phase x.
By adjusting the distribution of dc currents among three legs,
the symmetrical ac-side current references and the unevenly
distributed dc current references of three legs are obtained.
The second hierarchy is voltage control between the upper
and the lower arms, which keeps the average voltage of the
upper arm balanced with that of the lower arm. This hierarchy
can perfectly resolve the asymmetry problem of the upper arm
and the lower arm, especially in experiment with a small
amount of SMs or when taken asymmetry inductance of each
arm into consideration. However, when the MMC operates in
high-voltage situation with hundreds of SMs and ignores the Fig. 11. Arm current tracking result.
asymmetry inductance of each arm, this hierarchy can be
removed. This hierarchy is realized by controlling ∆isxP, as Table I. Circuit parameters in simulations
shown in Fig. 7. In Fig. 7, U cpx and U cnx are respectively the
average voltages of the upper and the lower arm of phase x; Items Values
ΔPsctrl
xP is the output of controller.
Rated Power PN 600MW
The third hierarchy is the balance control of the capacitor Rated RMS Line-to-line Voltage of 230kV
voltages within an arm. It could be achieved by NLM, or the Ac-side Us
fine-tuning control combined with PSC [19], [20], [23].
3) Active Current References of the Upper and the Lower Rated Voltage of dc Bus Ud 600kV
Arms: From the above analysis, the active current references of SM Capacitor Voltage Uc 2.4kV
the upper and the lower arms can be obtained as:
Arm Inductance L 60mH
 I spctrlxP  0.5  I sctrl
xP  I sxP 
ctrl

 ctrl (23) SM Capacitance C 15mF
 I snxP  0.5  I sxP  I sxP 
ctrl ctrl

Resistance of dc Bus RL 600ohm


where I spctrlxP and I snctrlxP are RMS values of ac active current Number of SMs per Arm N 250
components of the upper and the lower arm current references.
Carrier Frequency f 80Hz
The RMS values can be transformed to be instantaneous values
Arm Current Controller Ki 1.333
as
ispctrlxP  I spctrlxP  sin x Dc Bus Controller Kbus 1.667
 ctrl (24) Dc Bus Controller Tbus 0.00025s
ctrl
isnxP  I snxP  sin x
where sinx is the phase message of usx, which can be obtained Capacitor voltage Controller Kc 1.543
by a PLL. Capacitor voltage Controller Tc 0.07s
4) Zero-sequence Current Canceller: As shown in (23),
asymmetrical device loss of each arm will cause
I saP  I sbP  I scP (25) iprefx  isprefxP  0.5isrefxQ  I drefx  icir
ref
_x
According to (23), (24) and (25), asymmetrical device loss  ref ref ref ref ref
(26)
will generate zero-sequence fundamental-frequency current inx  isnxP  0.5isxQ  I dx  icir _ x
which will flow into dc-bus. To prevent the zero-sequence where isrefxQ is reactive reference current of ac-side; icir ref
_ x is the
fundamental-frequency current flowing into the dc-bus, a reference circulating current. In a general case, reference
zero-sequence current canceller is designed as in Fig. 8. Since circulating current should be set to zero, i.e., icir ref
_ x  0 , which
this current canceller exists accompanied with the voltage
control between the upper and the lower arms, if the voltage also means omissible. However, when MMC works under
control between the upper and the lower arms is omitted as no-load condition, circulating current could be set to an
discussed in III-B)-2), then this current canceller can be appropriate value to provide arm current for realizing the
removed too. voltage balance of submodules. The complete control strategy
is shown in Fig. 9.
C. Comprehensive Control Strategy
IV. SIMULATION RESULTS
Based on the above dc bus voltage control and capacitor
voltage control, the upper and the lower arm reference currents In order to verify the proposed control strategy in
of phase x can be obtained according to (2). system-level performance, simulations are carried out by
PSCAD/EMTDC. The grid fault scheme is designed as shown
in Fig. 10. The single-phase to ground fault happens in phase a
at t=1.0s. In these simulations, NLM is adopted as the third

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Transactions on Power Electronics

Fig. 12. Simulation results when control strategy in [20] is Fig. 13. Simulation results when the proposed control strategy
adopted. (a) Line-to-line voltages of ac-grid; (b) Ac-side is adopted. (a) Line-to-line voltages of ac-grid; (b) Ac-side
currents; (c) Dc-bus voltage; (d) Inner unbalanced currents of currents; (c) Dc-bus voltage; (d) Inner unbalanced current of
three phases; (e) The voltages of the first capacitor of three phases; (e) The voltages of the first capacitor of
respectively the upper and the lower arms in phase a. respectively the upper and the lower arms in phase a.

hierarchy to balance the capacitor voltages within an arm. evenly distributed state soon. It is also clear that there is small
Parameters in the simulations are shown in table I. circulating current after the fault happens, which is caused by
Fig. 11 shows the arm current tracking results of phase a the tracking error of the arm current regulator. However, the
respectively before and after the fault happens. It is clear from circulating current is so small that it can be ignored. The
Fig. 11 that the arm current perfectly tracks its reference with voltages of the first capacitor of respectively the upper and the
almost zero tracking error whether before or after the faults. lower arms in phase a are shown in Fig. 12(e). From Fig. 12(e),
This shows the effectiveness of the arm current regulator, the capacitor voltage recovers to its reference value after a
which is composed by the proportional regulator with a divarication. It is also clearly that the voltage fluctuations of
feedforward steady state duty cycle. the capacitors become larger after the fault happen, and this is
Fig. 12 shows the simulation results when control strategy in caused by the larger arm current after the fault happens.
[20] is adopted. The idea of this control strategy is the same Fig. 13 shows the simulation results when the proposed
with the one in II-A-1), which ensures that the dc current is control strategy is adopted. This control strategy ensures that
evenly distributed among three legs. As a result, the ac-side the ac-side currents are symmetrical, whereas the dc current
current will be asymmetrical under unbalanced grid condition. does not distribute averagely among three legs. Fig. 13(a)
Fig. 12(a) shows the line-to-line voltage of ac-side before and shows the line-to-line voltage of ac-side before and after the
after the single-line to ground fault happens. In Fig. 12(b), the fault happens. In Fig. 13(b), the ac-side currents keep
ac-side currents become asymmetrical when fault happens and symmetrical when fault happens and all of the currents
the current of phase a increases apparently larger than those of increase in a relatively small amplitude when compared to the
phase b and c. The ac-side current relationship is in accordance currents in Fig. 12(b). The dc-bus voltage is shown in Fig.
with the analysis in II-A-1). The dc-bus voltage is shown in 13(c). There is also a small fluctuation with double-frequency
Fig. 12(c). There is a small fluctuation with double-frequency in dc-bus voltage after the fault happen, and the fluctuation is
in dc-bus voltage after the fault happen, which is caused by the less than 0.33% of the dc-bus voltage too, which can be
small tracking error of the arm current regulator at the double ignored approximately. The inner unbalanced currents of three
frequency. However, the fluctuation is less than 0.33% of the legs which contain dc current and the circulating current are
dc-bus voltage, which can be ignored approximately. Fig. 12(c) shown in Fig. 13(d). It is clear from Fig. 13(d) that the dc
shows a good control effect of the dc-bus voltage control and current does not distribute evenly in three legs when fault
the arm current regulator. The inner unbalanced currents of happens. From Fig. 12(b), the ac-side current of phase a is
three phases which contain dc current and the circulating larger than those of phase b and c. According to (12), in order
current are shown in Fig. 12(d). It is clear from Fig. 12(d) that to realize the symmetry of ac-side currents, the dc current
the dc current distributes evenly in three legs before fault (active power) distribution among three legs should be
happens. When fault happens, there is a small divarication of adjusted. The dc currents of phase b and c should be increased
dc current distribution in transient process, and recover to whereas that of phase a should be decreased, and this agrees

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Fig. 14. Three-phase back-to-back MMC prototype.

Table II. Circuit parameters in experiments


Items Values
Rated Power PN 10kW
Rated RMS Voltage of Ac-side Usx 220V
Fig. 16. Waveforms in case one. (a) Dc-bus voltage Ud and
Rated Voltage of dc Bus Ud 800V ac-side currents isa, isb, isc; (b) Capacitor voltages ucpa1, ucna1 and
Rated Current of dc Bus Id 12.5A arm currents ipa, ina of phase a; (c) upper arm currents ipa, ipb, ipc
of three phases and upper arm output voltage upc of phase c.
SM Capacitor Voltage Uc 200V
Arm Inductance L 10mH
SM Capacitance C 2400uF
Resistance of dc Bus RL 64ohm
Number of SMs per Arm N 4
Carrier Frequency f 5kHz
Arm Current Controller Ki 0.167
Dc Bus Controller Kbus 20.833
Dc Bus Controller Tbus 0.00025s
Capacitor voltage Controller Kc 20.57
Capacitor voltage Controller Tc 0.07s

Fig. 17. Waveforms in case two. (a) Dc-bus voltage Ud and


ac-side currents isa, isb, isc; (b) Capacitor voltages ucpa1, ucna1 and
arm currents ipa, ina of phase a; (c) upper arm currents ipa, ipb, ipc
of three phases and upper arm output voltage upc of phase c.
Fig. 15. Grid fault scheme in the experiment.
side, the rectifier side with the Y/Y transformer is employed in
with Fig. 13(d) and the analysis in II-A-2). It is also clear from our experiments. Parameters in the experiment are shown in
Fig. 13(d), the circulating current is so small that it can be table II. The grid fault scheme in the experiment is designed as
ignored. The voltages of the first capacitor of respectively the shown in Fig. 15. Under balanced grid condition, ac grid of
upper and the lower arms in phase a are shown in Fig. 13(e). phase a is not grounded at the point Gs, and the transformer is
The capacitor voltage fluctuations in Fig. 13(e) are smaller and connected to ac-grid through the dotted line. Under unbalanced
recover to their reference value in a shorter time when grid condition, the dotted line is broken, and the primary side
compared to the capacitor voltages in Fig. 12(e). It is because of transformer of phase a is directly grounded at the point Gs. It
the arm current in the proposed strategy is much smaller than should be noted here that under unbalanced grid condition,
that in the control strategy in [20]. resistance of dc bus RL is twice of the rated value for avoiding
overcurrent of arm switch devices. In experiments, the
V. EXPERIMENT RESULTS
fine-tuning control combined with PSC is adopted as the third
Fig. 14 shows the experimental prototype of a back-to-back hierarchy to balance the capacitor voltages within an arm.
MMC. Both rectifier side and inverter side are isolated from
A. Case One: Under Balanced Grid Condition.
the ac-grid by three-phase transformers: one is in Y/Y structure,
the other is in Y/∆ structure. In order to verify the feasibility Under balanced grid condition, MMC operates at rated
and effectiveness of the proposed control strategy in rectifier power. Experiment results are shown in Fig. 16. Dc-bus

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Fig. 18. Waveforms in case two.

Fig. 20. Waveforms when control strategy in [20] is adopted. (a)


Fig. 19. Unbalanced line-to-line voltages in the secondary side Dc-bus voltage Ud and ac-side currents isa, isb, isc; (b) Capacitor
of transformer. voltages ucpa1, ucna1 and arm currents ipa, ina of phase a; (c)
Capacitor voltages ucpb1, ucnb1 and arm currents ipb, inb of phase
voltage and the symmetrical ac-side currents are shown in Fig. b; (d) upper arm currents ipa, ipb, ipc of three phases and upper
16(a). In Fig. 16(b), the voltages of the first capacitor arm output voltage upc of phase c.
respectively of the upper arm and the lower arm in phase a are
well balanced. The currents of respectively the upper arm and
the lower arm in phase a present as sinewave without
double-frequency circulating component, and this shows a
good performance of arm current control to suppress the
circulating current. Fig. 16(c) shows the upper arm output
voltage of phase c and the upper arm currents of three phases.
The arm output voltage appears as a five-level wave, and the
upper arm currents of three phases are symmetrical. Fig. 16
shows the good static characteristics of the proposed control
strategy under balanced grid condition.
B. Case Two: A Switchover from Inductive Reactive Current
to Capacitive Reactive Current.
At the beginning, MMC operates at rated inductive reactive
current. Then change this current into rated capacitive reactive
current. In Fig. 17(a), at the switching moment, a small
fluctuation happens in the dc-bus voltage, and it disappears
quickly. A phase reversal happens in the ac-side current since
the current changes from inductive into capacitive. In Fig.
17(b), the capacitor voltage waveform changes when the arm Fig. 21. Waveforms when proposed strategy is adopted. (a)
current changes from inductive into capacitive. Both the Dc-bus voltage Ud and ac-side currents isa, isb, isc; (b) Capacitor
capacitor voltages and arm currents recover to balance quickly voltages ucpa1, ucna1 and arm currents ipa, ina of phase a; (c)
after the switching. In Fig.17(c), the arm output voltage Capacitor voltages ucpb1, ucnb1 and arm currents ipb, inb of phase
changes accompanied with the variation of the capacitor b; (d) upper arm currents ipa, ipb, ipc of three phases and upper
voltage. Arm currents of three phases recover to symmetrical arm output voltage upc of phase c.
quickly after the switching moment. Fig. 17 shows a rapid
response speed to the switchover of reactive current and a good frequency exists in ipa-ina. This small ripple is caused by the
control performance of dc bus voltage and capacitor voltages. device loss difference of the upper arm and the lower arm as
C. Case Three: A Switchover from Capacitive Reactive mentioned in (14). When change the reactive current reference
Current Reference to Circulating Current Reference. into circulating current reference, ipa-ina changes into double-
frequency circulating current instantaneously. The ac-side
At the beginning, there is only capacitive reactive reference
current isa changes into almost zero, and the arm current ipa and
current in ac-side. Then change this reference current into
ina change from fundamental-frequency into double-frequency
circulating current reference. Experiment results are shown in
with opposite phase instantaneously. Fig. 18 shows a good
Fig. 18. In Fig. 18, ipa-ina is the difference value of the upper
control performance of the proposed strategy on circulating
and the lower arm currents of leg a, and it is twice the value of
current and ac-side current.
idiffa. When there is only reactive reference current, ipa-ina is
almost zero since there is no dc current and the circulating D. Case Four: Under Unbalanced Grid Condition.
current is suppressed. However, a small ripple of fundamental- Grid fault scheme is shown as in Fig. 15. The unbalanced

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line-to-line voltages in secondary side of Y/Y transformer are feedforward steady state duty cycle is designed for arm current
shown in Fig. 19. Control strategy in [20] and the one regulator, which can perfectly track its reference. Both the
proposed in this paper are adopted for comparison. The system-level simulations and the low-level experiments are
experiment results of the control in [20] are shown in Fig. 20, performed to verify the good effect of the arm current regulator,
and the results of the proposed control are shown in Fig. 21. and the feasibility and effectiveness of the proposed strategy.
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2717541, IEEE
Transactions on Power Electronics

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