Introduction to the
System-on-Package (SOP)
Technology
Prof. Rao R. Tummala and Tapobrata Bandyopadhyay
Georgia Institute of Technology
T
he primary drivers of the information age are microsystems technologies and
market economics. Gigascale integration of microelectronics, gigabit wireless
devices, terabit optoelectronics, micro- to nano-sized motors, actuators, sensors,
and medical implants and integration of all these by the system-on-package concept
leading to ultraminiaturized, multi-to-mega function are expected to be the basis of the
new information age.
This book is about system-on-package (SOP) technology in contrast to system-on-
chip (SOC) technology at the integrated circuit (IC) level and stacked ICs and packages
(SIP) at the module level. In this book, SIP is defined as the stacking of ICs and
packages. Thus SOP is considered as an inclusive system technology of which SOC,
SIP, thermal structures and batteries are considered as subset technologies. System-
on-package is a new, emerging system concept in which the device, package, and
system board are miniaturized into a single-system package with all the needed
3
4 Chapter One
system functions. The SOP technology can be thought of as the second law of electronics
for system integration in contrast to Moore’s law for ICs.
This chapter introduces the basic concept of SOP. It reviews the characteristic features
of a system-on-package and compares it with traditional and other major system
technologies. It provides insight into the status of global research and development efforts
in this area. Finally, it outlines the different technologies involved in making SOP-based
products. The chapter concludes with an overview of all these basic SOP technologies,
which form the chapter titles of this book.
1.1 Introduction
The concept of SOP originated in the mid-1990s in the Packaging Research Center at the
Georgia Institute of Technology. The SOP is a new and emerging system technology
concept in which the device, package, and system board are miniaturized into a single-
system package with all the needed system functions. The SOP is described in this book
as the basis for the second law of electronics for system integration in contrast to Moore’s
law for IC integration. The focus of SOP is to miniaturize the entire system, such as
shown in Figure 1.1, which includes
PCB fan
mounting point
Heat sink
IC
IC package
Connectors
(I/O ports)
Discrete passives
System board
FIGURE 1.1 A typical example of a system with all its system components—DFI LanParty UT RD600.
(Courtesy: dailytech.com)
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 5
100
% System miniaturization
SOP
System
SIP integration
30 Stacked chip
or package
SOC
integration
15 IC integration
FIGURE 1.2 The miniaturization trend in ICs since the 1960s to systems around 2020.
The initial focus of SOP is on miniaturization and convergence of the package and
system board into a system package, hence the name system-on-package. Such a single-
system package with multiple ICs provides all the system functions by codesign and
fabrication of digital, radiofrequency (RF), optical, micro-electro-mechanical systems
(MEMS), and microsensor functions in either the IC or the system package. The SOP
thus harnesses the advantages of the best on-chip and off-chip integration technologies
to develop ultraminiaturized, high-performance, multifunctional products. Figure 1.2
depicts the miniaturization trend that started at the IC level in the 1960s at the microscale
level and continued on to reach the expected level below 40 nanometers (nm). This is
referred to as “SOC.” The single-chip package miniaturization took place in a similar
manner but at a slower rate until chip-scale packages (CSP) and two-dimensional (2D)
multichip modules (MCMs) in the 1990s and three-dimensional (3D) SIPs a decade later
were introduced. This is referred to as module-level miniaturization. The system-level
miniaturization began subsequently.
IDE • Nanoscale
BR (22 nm)
IC • 10% System
G
GIN
package
PACKA
Connectors • 90% System
• Milli-scale
Board
Discrete
FIGURE 1.3 Packaging is the bridge and the barrier between ICs and systems.
criteria—size of the system and functionality of the system as shown in Figure 1.2.
Computers in the 1970s were bulky, providing computing power measured in millions of
instructions per second (MIPS). The subsequent IC and package integration technologies
in the 1980s paved the way for systems with billions of instructions per second (BIPS),
which further led the way for smaller and personal systems called PCs. The technical
focus of these small computing systems by IC integration to single-chip processors, and
package integration to multilayer thin-film organic buildup technologies, together with
other miniaturization technologies such as flip-chip interconnection technology led to a
new paradigm in personal and portable systems—cell phones. This trend, as shown in
Figure 1.4, is expected to continue and to lead to highly miniaturized, multifunction-to-
megafunction portable systems with computing, communication, biomedical, and
Workstation
10000
Volume (cm3)
Laptop
Single function
Mobile Bio-sensor
1000
Multi function
SMART
100 watch
Mega function
FIGURE 1.4 Electronic system trend toward highly miniaturized digital convergence.
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 7
consumer functions. Figure 1.4 shows some examples of electronic systems in the past
and others projected in the future. This trend is expected to continue to megafunction
systems that are about a cubic centimeter in size with not only computing and
communication capabilities but also with sensors to sense, digitize, monitor, control,
and transmit through the Internet to anyone anywhere.
Heat removal Bulky heat sinks and heat Advanced nano thermal interface
elements spreaders. Bulky fans for materials, nano heat sinks and heat
convection cooling spreaders, thin-film thermoelectric
coolers, microfluidic channel based
heat exchangers
System board PCB-based motherboard Package and PCB are merged into
the SOP substrate
Connectors/ USB port, serial port, Ultrahigh density I/O interfaces
sockets parallel port, slots [for
dual in-line memory
modules (DIMM) and
expansion cards]
Sensors Discrete sensors on PCB Integrated nanosensors in IC and
SOP substrate
IC-to-package Flip chip, wire bond Ultraminiaturized nanoscale
interconnections interconnections
TABLE 1.1 Building Blocks of a Traditional Electronic System versus an SOP-based System
8 Chapter One
SIP SOC
WA FE R IC integration
IC
SOP PKG.
Package
enabled
integration
Connectors
Board
SYSTEM
PKG.
Discretes System
integration
FIGURE 1.5 Three main integration approaches to address the system barriers.
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 9
(a) Industry’s first MCM (IBM), 1982 (b) 61 Layer LTCC/Cu-MCM (IBM), 1992
• Stacked ICs with silicon-through vias (with flip chip or copper-to-copper bonding)
• Silicon ICs on silicon wafer board
• Wafer-to-wafer stacking
The ultraminiaturized systems such as “Dick Tracy’s watch” in Figure 1.3 with dozens
of functions requires yet another major paradigm in system technology. This paradigm
is based on the concept of system-on-package, which originated in the mid-1990s at the
NSF-funded Packaging Research Center at the Georgia Institute of Technology [3].
10 Chapter One
Interconnects: µm → nm
Interconnects: µm → nm
Interconnects: mm → µm
100x−1000x
IC IC
miniaturization
Pa
cka
ge IC IC
Package Package
ard
bo System package
m
ste
Sy
System board
Interconnects: µm → nm
Interconnects: mm
SOB-based System SOP-based System
FIGURE 1.7 A comparison between three-tier SOB-based and two-tier SOP-based systems.
The SOP technology concept has two characteristics. First, it combines the IC, package,
and system board into a system package (as shown in Figure 1.7), hence its name system-
on-package. The second key attribute of SOP is its integration and miniaturization at the
system level just like IC integration at the device level. Unlike SIP, which enables IC stacking
without real package integration, SOP integrates all the system components either in ICs or
packages as ultrathin films or structures that include the following [4]:
• Passive components
• Interconnections
SIP, 3D
SOB WSI MCM SOC Si on Si SOP
FIGURE 1.8 Historical evolution of the five system technologies over the past 50 years.
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 11
• Connectors
• Thermal structures such as heat sinks and thermal interface materials
• Power sources
• System board
Such a single-system package provides all the system functions such as computing,
wireless and network communications, and consumer and biomedical functions in
one single module. Figure 1.8 depicts the historical evolution of the five system
technologies during the last 50 years as well as the expected projection during the next
15 years.
IC Integration
ASICS
DRAM
RF-IC
Storage
capacitance
OE-IC
Flash
DSP High voltage
System tunnel oxides
integration SRAM
U processor Imaging Dense features
Light sensitive devices
Package-Enabled Integration
RFIC Digital IC Optical IC
Substrate
MCM: Interconnected components
IC
Package
Flash
RAM
IC
µP
SOP-Based Integration
RF IC Opto IC Digital IC
IC and RF Opto Electrical
Codesign
system and
Package with opto, RF, digital functions optimization
Best of:
• IC integration
• Package-enabled integration
• System integration
FIGURE 1.9 (a) IC and package-enabled integration interconnecting two or more ICs. (b) SOP:
True package and IC integration.
that this kind of progress can go on forever, leading to a “system-on-a-chip” for all
applications to form complete end-product systems.
The SOC schematic shown in Figure 1.9a, for example, seeks to integrate numerous
system functions on one silicon device horizontally, namely the chip. If this chip can be
designed and fabricated cost effectively with computing, communication, and consumer
functions (such as processor, memory, wireless, and graphics) by integrating the required
components (such as antennas, filters, switches, transmitting waveguides, and other
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 13
components required to form a complete end-product system), then all that is necessary
to package such a system is to provide protection, external connections, power, and
cooling. If this can be realized, SOC offers the promise for the highest performance
and the most compact, lightweight system that can be mass-produced. This has been
and continues to be the road map [8] of IC companies.
So the key question is whether SOC can lead to cost-effective, complete end-product
systems such as tomorrow’s leading-edge cell phones with digital, wireless, and sensing
capabilities or biomedical implants. Researchers around the world, while making great
progress, are realizing that SOC, in the long run, presents fundamental limits for computing
and integration limits for wireless communications and additional nonincremental costs to
both. Among SOC challenges are the long design times due to integration complexities,
high wafer fabrication costs and test costs, and mixed-signal processing complexities
requiring dozens of mask steps and intellectual property issues. The high costs are due to
the need to integrate active but disparate devices such as bipolar, CMOS, silicon germanium
(SiGe), and optoelectronic ICs—all in one chip with multiple voltage levels and dozens of
mask steps to provide digital, RF, optical, and MEMS-based components.
It is becoming clear that SOC presents major technical, financial, business, and legal
challenges that are forcing industry and academic researchers to consider other options
for semiconductors and systems. For the first time, industry may not invest in extending
Moore’s law beyond 2015. This is leading the industry to explore alternative ways to
achieve systems integration wherein semiconductor integration is pursued, not only
horizontally by SOC, but also vertically by SIP via 3D stacking of bare or packaged ICs
and by SOP. More than 50 companies are pursuing SIP as indicated in Chapter 4.
Hence, a new paradigm that overcomes the shortcomings of both SOC and
traditional systems packaging is necessary. The SOP technology described in this book
makes a compelling case for the synergy between the IC and the package integration by
means of the SOP concept, which can also be applied to SOCs and SIPs, as well as to
silicon wafer, ceramic, or organic carrier platforms or boards.
latency, if the size of the chips and their thicknesses used in stacking are small. SIP is also
defined often as the entire system-in-a-package. If all the system components (for example,
passive components, interconnections, connectors, and thermal structures such as heat
sinks and thermal interface materials), power sources, and system board are miniaturized
and integrated into a complete system as described in this book as SOP, then there is no
difference between SIP and SOP. The intellectual property issues as well as yield losses
associated with dozens of sequential mask steps and large-area IC fabrication are also
minimal. Clearly, this is the semiconductor companies’ dream in the short term.
But there is one major issue with this approach. The SIP, defined above as stacking of
ICs, includes only the IC integration and hence addresses only about 10 to 20 percent of
the system by extending Moore’s law in the third dimension. If all the ICs in the stack are
limited to CMOS IC processing, the end-product system is limited by what it can achieve
only with CMOS processing at or below nanoscale. The above fundamental and integration
barriers of SOC, therefore, remain. There are clear major benefits, however, to SIP: simpler
design and design verification, a process with minimal mask steps, minimal time-to-
market, and minimal Intellectual Property (IP) issues. Because of the above-mentioned
SIP benefits, however limited, about 50 IC and packaging companies alike have geared
up in a big way to produce SIP-based modules (Figure 1.10).
SIP Categories
The SIP technology can be broadly classified, as shown in Figures 1.10 and 1.11, into two
categories: (1) stacking of bare or packaged ICs [9–12] by traditional wire-bond, TAB, or
flip-chip technologies, and (2) stacking by through-silicon vias (TSVs), without using
wire bond or flip chip. SIP and 3D packaging are often meant to be the same and are
loosely referred to as the vertical stacking of either bare or packaged dies. In this book,
however, 3D package integration refers to stacking of ICs by means of TSV technology.
SIP by Wire Bonding Three-dimensional integration of bare dies can be done using wire
bonding as shown in Figure 1.12. In this approach, the different stacked dies are
interconnected using a common interposer (or package). The individual dies are
connected to this interposer by wire bonds. Wire bonding is economical for interconnect
densities of up to 300 I/Os. However, it suffers from the high parasitic inductance of the
wire bonds. There is a lot of inductive coupling between the densely placed wire bonds
which results in poor signal integrity.
SIP by Flip Chip and Wire Bonding In this 3D integration technique, as shown in Figure 1.13,
the bottom die of the stack is connected to the package by flip-chip bonds. All other dies
on the top of it are connected to the package using wire bonds. This eliminates the wire
bonds required for the bottom die, but still suffers from the high parasitics of the wire
bonds for the upper dies.
SIP by Flip Chip–on–Chip The bare dies are flip-chip bonded with each other in this
approach of 3D integration as shown in Figure 1.14a and b. The dies are arranged face-
to-face with the Back End of Line (BEOL) areas of the dies facing each other. The bottom
die is usually bigger than the top die. The bottom die is connected to the package by
wire bonds.
stacking
1971-A.D. Scarbrough
2003-IME 2005-Hitachi
Si chip carrier
and Renesas
1981-GE 1994-Bosch
TSV
1986-RPI, GE 1999-Tru-Si 2006-IBM 2006-Intel
and IBM
Chip stacking
2007-IBM
1973-IBM 2001-ASET 2006-Samsung
1967
Bell labs 2001-Intel, Tessera
1983-GM
1993-Thomson-
CSF
1994-White
Package stacking
1972-IBM 2001-Sharp
Microelectronics
2001-IMEC,
1992-Irvine 1997-Tohoku
Fujitsu
Chip stacking
1993-nChip
Year
15
SIP
FIGURE 1.13 Three-dimensional integration using a combination of flip-chip and wire bonding.
Solder ball
Organic substrate Substrate Bump Sub-chip Solder ball
Bump
(a) Perspective view (b) Cross-sectional view
FIGURE 1.14 Three-dimensional integration by the flip chip-on-chip approach. (a) Perspective view.
(b) Cross-sectional view. [13]
16
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 17
Si Substrate or Carrier
The concept of the silicon chip carrier was developed in 1972 [14] at IBM where a Si
substrate was used as a chip carrier instead of insulating organic or ceramic substrates.
Initially, the chips were connected to the chip carrier by perimeter connections such as
wire bonding. Later, the connections were replaced by flip-chip connections. Lately,
TSVs have been used in the chip and the carrier. The TSVs help to develop a high-density
50 µm × 4
Interposer (Si) 1 mm
FIGURE 1.16 Package-in-package (PiP) structure. Left: PiP package stack of two packages (four
chips). Right: PiP with a package and a die stack (four dies). [16]
interconnection from the chip to the carrier and from the carrier to the board. Presently,
silicon chip carrier technology involves through-silicon vias (TSVs), high-density wiring,
fine pitch chip-to-carrier interconnection, and integrated actives and passives. The TSVs
can also be used to stack the Si chip carriers on top of one another [15].
FIGURE 1.17 Package-on-package (PoP) structure with two packages (four chips). [16]
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 19
Moore’s law
108 106
Transistors/cm3
10% System
107 105
s
o
IC
Nan
for 90% System
106 s law 104
o re’ SIP
Mo D, System
,3 integration law
SOP
105 M CM 2010 103
2005
o
Micr
PRC-2003
104 102
MILLI nsity 50
de
Component
103 SMT MCM 10
PTH
1971 1980 1990 2000 2004 2020
FIGURE 1.18 Second law of electronics achieves true package integration combined with the
best of IC integration.
Evolution of IC Packages
SoP
SIP
Family QFP BGA FC-BGA DCA Non-TSV TSV SoP
IC Wire bond Wire bond Solder ball ---- WB, FC TSV Flip chip
Package Leadframe Substrate Substrate Thin-film Substrate Substrate Substrate
Si efficiency 30 50 75 100 >100 >100 >100
System integration
Power sources
IC integration
Thermal
structures SRAM CMOS
Boards and
packages Processors
Memory
Flash
Cables and
memory
connectors Graphics
Passives Baseband
R, L, C, filters, antennas,
waveguides, MEMS
Thin
actives
FIGURE 1.20 Fundamental basis of SOP with two parts: the digital CMOS IC regime and system regime.
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 21
Si
wafer
(300 mm)
Cost $
Cost $
Si
Package
wafer
Package
(600 mm)
FIGURE 1.21 Cost advantages of package integration over digital CMOS integration, for the same
components.
Optoelectronics, which today finds use primarily in the back plane and is used for
high-speed board interconnects, is expected to move onto the SOP package as chip-to-
chip high-speed interconnections replacing copper, thereby, addressing both the
resistance and crosstalk issues of electronic ICs. Optoelectronics, as it moves into silicon
as silicon photonics by Intel, is viewed, not as CMOS technology, but as an SOP-like
heterogeneous technology.
The SOP is about system integration enabled by thin-film integration of all system
components at microscale in the short term and nanoscale in the long term. As such, the
system package integration that SOP enables can be applied to CMOS ICs as overlays;
applied as thin films on top of silicon wafers (TFOS), silicon carriers, ceramic, and glass
substrates; or embedded into multilayer ceramics, packages, or board laminates.
• Higher performance
• Lower cost
• Higher reliability
• Higher functionality
• Smaller size
100
SOP
% System miniaturization
80
SIPs by
TSV
3D System
SIPs
20
3D IC packages
MCMs • Embedded ICs
and substrates
3D IC • Embedded
QFP passives
packages
2D IC • Nano TIMs &
SOCs packages heat transfer
10
CSP • Nano
components
ICs
• Nano batteries
FIGURE 1.22 Historical evolution of miniaturization technologies during the last four decades.
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 23
leading to nanometer nodes currently from micrometer nodes in the 1970s. This
miniaturization is expected to continue through at least 32 nm and perhaps beyond. The
miniaturization in IC packages, however, was not so dramatic. As can be seen from
Figure 1.18, the dual in-line packages with only I/Os in centimeter size in the 1970s
migrated to Quad-Flat Pack (QFP) with I/Os on all four sides of the package in the
1980s. Both are lead frame based, making them bulky. The next wave in miniaturization
led to solder ball attach and surface mount assembly to the board and was typically
achieved with ball grid arrays. The IC assembly miniaturization followed a similar path
starting with coarse-pitch peripheral wire bond, then finer pitch, and then to area array
wire bond by some companies. Further miniaturization at the IC level was brought about
by a major breakthrough by IBM, commonly referred to as “flip chip.” The flip-chip
miniaturization that started in the 1970s at the millimeter pitch, is paving the way to 10-
to 20-micron pitch by 2015. The so-called chip scale package that was no more than 20
percent larger in size than the packaged ICs was the next miniaturization technology
currently implemented at the wafer level. Further miniaturization has been accomplished
with bare chips by so-called chip-on-board or flip-chip MCM technologies.
The next wave in miniaturization has been achieved by 2D MCMs for ultrahigh
computing performance, as shown previously in Figure 1.5. Two factors contributed to
this miniaturization: (1) the highly integrated substrate and its multilayer fine line and
via wiring dimensions, and (2) 2D dimensions with as many as 144 bare chips
interconnected in 100- to 144-mm size substrate. The market need for cell phones
changed this 2D approach to 3D, achieved by stacking as many as 9 thinned chips to
date with the potential to stack 20 or more by 2015. Two major factors contributed to
this miniaturization: (1) thinned chips to 70 microns in thickness and (2) shorter and
finer-pitch flip-chip assemblies. The next paradigm in miniaturization is being achieved
by so-called through-silicon-via technology, as described above, and pad-to-pad
bonding, replacing the flip-chip assembly.
The fraction of the system miniaturized by the above IC-based and Moore’s law driven
technologies, as shown in Figure 1.22, is typically about 10 to 20 percent of the system,
leaving the remaining 80 percent in a bulky state. This 80 percent consists of such system
components as passives, power supplies, thermal structures, sealants, intersystem
interconnections, and sockets. This is what SOP is all about, miniaturizing these components
from their milliscale to microscale in the short term and nanoscale in the long term.
System Drivers
Higher
Higher system performance
reliability
Higher volumetric
thermal Lower power
dissipation consumption
Higher Smaller
flexibility size
Higher
Higher system
performance MCM
reliability
(multichip
module)
Higher Smaller
flexibility size
FIGURE 1.23 (a) System drivers: miniaturization, electrical performance, power usage, thermal
performance, reliability, development and manufacturing cost, time-to-market, and flexibility.
(b) System technologies compared against system driver parameters showing the strengths and
weaknesses of each.
Antennas are another example that cannot be integrated on silicon due to size
restrictions [20, 22–25]. Another example involves RF circuits that function in the microvolt
range. Integration of dissimilar signals requires large isolation between them. On standard
silicon, a major concern is substrate coupling caused by the finite resistivity of the silicon
substrate. Though solutions have been proposed using high-resistivity silicon or N-well
trenches, the isolation levels achieved are insufficient. For multiple voltage levels,
distributing power to the digital and RF circuits while simultaneously maintaining
isolation and low electromagnetic interference (EMI) can be a major challenge [26].
These issues can be addressed quite easily with SOP using embedded filtering and
decoupling technologies [27–31]. The SOP has already been demonstrated with Q
values in the range of 100 to 400 using low-loss dielectrics and copper metallization
structures that enable low-power solutions. With advances in digital processing speeds,
embedded optical waveguides in the package have the potential of bringing photonics
directly into the processor. This integration in the package can eliminate the serialization
and deserialization of data and therefore provide a compact platform for integration
with higher data bandwidth. In synchronous systems that support large ICs, a major
problem is the clock skew between various logic circuits on silicon. A potential solution
for such problems is the use of embedded optical clock distribution in the package,
which is immune to most noise sources [32–41].
The SOC, MCM, and SIP described above have one major shortcoming. They extend
Moore’s law in two or three dimensions. They address only 10 to 20 percent of system
needs and depend on CMOS only for system functions and on packaging for
interconnection only. This leads to bulky systems, not because of ICs but because of the
lack of system miniaturization. This single-chip CMOS focus at the system level, over
the long run, presents fundamental limits to digital systems and integration limits to RF
and wireless systems. Thus, while CMOS is good for transistors and bits and certain
other components, such as Power Amplifier (PA) and Low Noise Amplifier (LNA), it is
not an optimal technology platform for certain other components such as antennas,
MEMS, inductors, capacitors, filters, and waveguides.
The SOB, on the other hand, shows its strengths in those areas where SOC is weak
but suffers in those areas such as electrical performance and power usage where SOC
shines. The SIP is a good tradeoff between these two technologies, and at the same
time it is at the heart of semiconductor companies and their need to manufacture
as much silicon as possible to justify their wafer fabrication investments. In addition,
the SIP addresses the wireless cell phone “sweet spot” application. Therefore, it is
not surprising that almost all major IC companies are manufacturing these modules.
The major weakness of SIP is that it addresses the system drivers at the module level
only and not at a system level. The 80 to 90 percent of the system problems remains
unanswered.
The SOP is an even better and more optimized system solution than SIP, as can be
seen from Figure 1.24. It addresses at the IC level without compromise by means of both
on-chip SOC integration and package-enabled SIP and 3D integration and at the system
level by system miniaturization technologies such as power supplies, thermal structures,
and passive components, as indicated previously in Figures 1.5 and 1.9b for digital, RF,
optical, and sensor components. Unlike SOC, however, no performance compromises
have to be made in order to integrate these disparate technologies since each technology
is separately fabricated either in the IC or the package and subsequently integrated into
the SOP system package. System design times are expected to be much shorter in the
SOP concept, as it allows for greater flexibility with which to take advantage of emerging
26 Chapter One
System System
Device Package End system
technology board
Highly
System miniaturized
SOP SOC SIP
integration nano-micro
system
Mixed
signal PD/TIA SOC MEMS Ga-As
test
IBM
Embedded opto
Bromont
Back Plane-NTT, Siemens,
Agilent
Infineon
Waveguides-Toray,
Reliability Kyocera, DuPont, Shipley,
Motorola DOW, GE
Intel MSM Detectors-Fraunhoffer,
IBM Kyocera
SONY BATTERY
TI
Signal and power integrity Embedded RF SOP
EMI-NEC Corp., Toshiba Embedded passives-IBM, EKC-DuPont, Sanmina, 3M,
Power distribution-Sun, Cadence, Intel, and AMD Boeing, Shipley, Motorola, Nokia, Intel, Amkar, Lucent, IMEC,
Signal integrity-IBM and Ansoft Kyocera
Embedded decoupling-Sanmina, EIT, DuPont Antennaes-Asahi, DoD, NASA
Design tools-Cadence, Sun, Motorola, HRL, Rambus Design tools-Cadence
Recently, IBM researchers have built an optical transceiver (Figure 1.27) in current
CMOS technology and coupled it with other optical components, made with materials
such as indium phosphide (InP) and GaAs, into a single integrated package only 3.25
by 5.25 mm in size. This compact design provides both a high number of communications
channels as well as very high speeds per channel. This transceiver chipset is designed
to enable low-cost optics by attaching to an optical board employing densely spaced
polymer waveguide channels using mass assembly processes. According to IBM, this
prototype optical transceiver chipset is capable of reaching speeds at least eight times
faster than traditional discrete optical components available today.
1.8.2 RF SOP
At the Interuniversity Microelectronics Center (IMEC), in Leuven, Belgium, Robert
Mertens and colleagues are studying the best type of RF antenna to build in an SOP for
a range of wireless communications products yet to be introduced. IBM has developed
a small, low-cost chipset that could allow wireless electronic devices to transmit and
receive 10 times faster than today’s advanced WiFi networks. The embedding of the
antennas directly within the package helps reduce the system cost since fewer
components are needed. A prototype chipset module, including the receiver, transmitter,
and two antennas, would occupy the area of a dime. By integrating the chipset and
antennas in commercial IC packages, companies can use existing skills and infrastructure
to build this technology into their commercial products.
Laser
coiler
VCO
FPGA
MUX
....
D.S
Power combiner
Climer Amp
Embedded
Multiple
detector
Class I-mixer
optical
diffrential RF out
channel
VCO
DMUX
FPGA
....
S.D TIA
Embedded
Power optical
doubler detector
(a)
Ultra-compact Ku-band
VCO Stacked microvias
cross-section view Embedded chip to
CPW inductor, 1 mm × 1 mm
High density wiring chip optoelectronics Embedded optical
Wire bond VCO die 25–50 µm lines/spaces Poly waveguides
waveguide
All other RF components 50–100 µm vias Polymer cross-section view
embedded in substrate waveguide
Digital ICs (µP) Buffer layer
RF IC (VCO)
Signal Signal
Inductors 30 µm 10 µm
Signal Ground
Embedded C:10 nF/cm2,
Filter Antenna 10 µm film
Power
Ground VCO ground
(b)
FIGURE 1.29 (a) A conceptual broadband system called the intelligent network communicator (INC),
developed at Georgia Tech. (b) A cross-sectional view of the INC.
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 31
technology from design to fabrication to integration, test, cost, and reliability. The
testbed explored optical bit stream switching up to 100 GHz; digital signals up to 5 to
20 GHz; decoupling capacitor integration concepts to reduce simultaneous switching
noise of power beyond 100 W/chip; design, modeling, and fabrication of embedded
components for RF, microwave, and millimeter wave applications up to 60 GHz.
So far, at least 50 companies have taken parts of the SOP technology developed at
the Georgia Institute of Technology’s Packaging Research Center (PRC) and applied
them to their automotive, computer, consumer, military, and wireless applications. A
number of test vehicles have also been built over the years for different companies
focused on integrating different combinations of analog, digital, RF, optical, and sensor
components in a single package.
Japanese companies, such as Ibiden, Shinko, Matsushita, Casio, and NEC, have been
active in R&D in EMAP technology for more than 5 years. Casio and Matsushita have
already demonstrated embedded passives and IC components in laminate layers. They
started this research around 1998–2000. One example of Matsushita’s SIMPACT
technology developed in 2001 is shown in Figure 1.30 where discrete passives and actives
are embedded in dielectric layers. Matsushita indicated that its embedding program
uses discretes but will migrate to thin films as the company perfects manufacturing.
In the United States, Intel has been active in EMAP for its RF modules and digital
applications and is expected to appear with EMAP products in the market in 2 to
3 years. Companies like 3M and Oak-Mitsui have thin-film capacitor technologies ready
for production. GE has been a big player in embedded actives technology for a long
time and is now focusing on embedded passives to go with existing embedded active
technology. TI is beginning to be a big contender in this research and business. Even
in the automotive industry, companies like Delphi are interested in EMAP technology.
There is a big interest in Europe too, such as by Nokia.
Motorola uses parts of SOP technology in two models of its GSM/General Packet Radio
Service quad-band cell phones to gain about a 40 percent reduction in board area. The
module contains all the critical cell phone functions: RF processing, base-band signal
processing, power management, and audio and memory sections. Not only does the module
free up space for new features, it is also the base around which new cell phones with different
shapes and features (camera or Bluetooth, for instance) can be rapidly designed. Motorola
calls it a system-on-module (SOM), for which it developed its own custom embedded-
capacitor technology. It reports it has shipped more than 20 million SOM-based phones.
Via Bare IC
FIGURE 1.30 Matsushita SIMPACT with embedded discrete passives and actives developed in 2001.
32 Chapter One
1999
Embedded inductors 1999
(up to 22 nH) Gen 1 embedded resistors
(20% tolerance)
1999
Gen 1 embedded capacitors
(0.8 pF/mm2)
2003
Gen 2 trimmed resistors
(1–3% tolerance)
2002
Gen 2 embedded capacitors 2006
(16.8 pF/mm2) Gen 3 embedded capacitors
(3000 pF/mm2; in scale-up)
Motorola has been a global leader in both the R&D and manufacturing
implementation of RF passives (Figure 1.31). Its first generation of RF capacitor passives
was used in its cell phones in the 1999 time frame. The second generation of passives
was improved for not only capacitance density but also for process tolerances around
2002. Ferroelectric thin film capacitors are under development in Motorola.
Intel has also reported a 43 percent reduction in the form factor along with increased
functionality in its wireless local area network (WLAN) solution (Figure 1.32)
2004: Intel@ pro wireless 2915 ABG 2006: Intel@ pro wireless 3945 ABG
network connection WLAN card network connection WLAN card
• 43% area redux
• Double-sided to single-
sided assembly
• Increased functionality
50 × 30 mm
9 × 9 mm leadframe (1500 sq mm)
(QFN1) transceiver Pkg
• Single row
• Increased
60 × 44 mm (2640 sq mm) functionality
FIGURE 1.32 SOP implementation in Intel’s WLAN and wireless WiFi link cards. [43]
I n t r o d u c t i o n t o t h e S y s t e m - o n - P a c k a g e ( S O P ) Te c h n o l o g y 33
FIGURE 1.33 SOP includes all system building blocks: SOCs, SIPs, MEMS, embedded components
in ICs and substrates, thermal structures, batteries, and system interconnections.
34 Chapter One
1.11 Summary
SOP is about system miniaturization enabled by IC and system integration by ultrathin-
film components at microscale in the short term and nanoscale in the long term for all
system components. Some of these thin-film system technologies that SOP enables can
be used in CMOS ICs as overlays, as thin films on top of silicon wafers (TFOS) and
silicon carriers, or on ceramic and glass substrates or embedded into multilayer ceramic
or organic laminate packages and boards.
SIP is defined in this book as the stacking of ICs and packages. But since SIP is also
often referred to as a total system technology that miniaturizes and integrates all system
components such as passives, actives, thermal structures, power sources, and I/Os, if this
happens, then SOP and SIP are identical. But so far, this has not been demonstrated.
Acknowledgments
The authors gratefully thank the Georgia Tech PRC team of faculty, engineers, students,
and industry advisors for their contributions in the development of the SOP technology.
The authors also thank both the Georgia Research Alliance and the National Science
Foundation Engineering Research Centers for their funding of SOP technology for more
than a decade.
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