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A Project Report

on
Design and Simulation of Negative Capacitance MOSFET

Submitted in the Partial Fulfillment of the Requirements


for the award of

Bachelor of Technology
in
Electronics & Communication Engineering
By
Puneet Kumar (20145046)
Yedla Jagadeesh (20145111)
Pankaj Rawat (20125086)

Under the guidance of


Dr. Vadithya Narendar
Assistant Professor, ECED
MNNIT Allahabad

Department of Electronics & Communication Engineering


Motilal Nehru National Institute of Technology Allahabad
Allahabad – 211004
INDIA
UNDERTAKING

We declare that the work presented in this project titled “Design and Simulation of
Negative Capacitance MOSFET”, submitted to the DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING, MOTILAL NEHRU
NATIONAL INSTITUTE OF TECHNOLOGY ALLAHABAD, ALLAHABAD for the
award of the Bachelor of Technology degree in Electronics and Communication
Engineering is our original work. We have not plagiarized or submitted the same work for
the award of any other degree. In case this undertaking is found incorrect, we accept that
our degree may be unconditionally withdrawn.

Date: 4st December, 2017

Allahabad, India

Puneet Kumar

Yedla Jagadeesh

Pankaj Rawat

ii
CERTIFICATE

This is to certify that the work contained in the project titled “Design and Simulation of
Negative Capacitance MOSFET”, submitted by Puneet Kumar, Yedla Jagadeesh and
Pankaj Rawat in the partial fulfillment of the requirement for the award of Bachelor of
Technology in Electronics & Communication Engineering to the Electronics &
Communication Engineering Department, Motilal Nehru National Institute of Technology,
Allahabad, is a bonafide work of the students carried out under my supervision.

Date: 4st December, 2017


Place: Allahabad
Dr. Vadithya Narendar
Assistant Professor
ECE Department
MNNIT, Allahabad

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ACKNOWLEDGEMENT

We express our deep sense of gratitude and immeasurable appreciation to our thesis
supervisor Assistant Professor Vadithya Narendar, for his support and encouragement
throughout this work which helped in completion of this project work in its present form.
We express our sincere thanks to PhD scholar Mr. Varun Mishra from Department of
Electronics and Communication for his sincere advice and encouragement. We express our
heartfelt esteem to the MNNIT Allahabad. We express our special thanks to all our friends.
We would like to thank our colleagues who helped us a lot during this project. We bow in
the deepest reverence to our beloved families.

Date: 4st December, 2017


Place: Allahabad

Puneet Kumar
Yedla Jagadeesh
Pankaj Rawat

iv
ABSTRACT
Owing to the fundamental physics of the Boltzmann distribution, the continuously
increasing power dissipation in nanoscale transistors threatens an end to the almost-four-
decade-old cadence of continued performance improvement in complementary metal-
oxide-semiconductor (CMOS) technology. It is now agreed that the introduction of new
physics into the operation of field-effect transistors–in other words, “reinventing the
transistor”– is required to avert such a bottleneck. In this report, we present a novel physical
phenomenon, called the negative capacitance effect in ferroelectric oxides, which could
dramatically reduce power dissipation in nanoscale transistors. It was theoretically
proposed in 2008 that by introducing a ferroelectric negative capacitance material into the
gate oxide of a metal-oxide-semiconductor field-effect transistor (MOSFET), the
subthreshold slope could be reduced below the fundamental Boltzmann limit of 60
mV/decade, which, in turn, could arbitrarily lower the power supply voltage and the power
dissipation.

In this work, a 2-D analytical model for Double-Gate Negative Capacitance MOSFET with
PZT Gate-Stack of 2nm on Ultra-thin oxide has been developed. Drift-Diffusion model,
Shockley-Reed-Hall recombination, quantum mechanical model and non-local path band-
to-band model are utilized from ATLAS library along with the ferro model for considering
the ferroelectric effect in gate oxide. Simulation results have been obtained combining the
Silvaco TCAD commercial simulator with Landau’s theory of ferroelectrics. We report a
clear and significant double improvement in average subthreshold swing using NC effect.
NCFET can operate at low power using the NC effect, with an average subthreshold swing
of 40 mV/decade at room temperature instead of 68.1 mV/decade. The double-gate
structure is proposed to overcome the large mismatch between the ferroelectric and MOS
capacitor to enhance the NC effect and reduce the ferroelectric’s optimized thickness.

v
Table of Contents

Undertaking…………………………………………………………………………….…ii
Certificate……………………………………………………………………...................iii

Acknowledgement………………………………………………………………………..iv

Abstract………………………………………………………………………....................v

Table of Contents……………………………………………………………....................vi

List of Figures………………………………………………………………...................viii

List of Tables…………………………………………………………………...................ix

List of Abbreviations……………………………………………………………………....x

Chapter 1 Introduction

1.1 Development in the field of semiconductors……………………………......1

1.2 Dennard’ Scaling Law…………………………………………....................2

1.3 Scaling trend of MOSFET and Power crisis in Nanoelectronics……………2

1.4 Motivation…………………………………………………………………...6

Chapter 2 Literature Overview

2.1 Negative Capacitance to rescue ……………………………………………..8

2.2 Capacitance: Positive and Negative……………………………….………..11

2.3 How to realize Negative Capacitance: the case of Ferroelectric oxides…….12

2.4 An Introduction to ferroelectric oxides……………………………………..13

vi
2.5 Landau Theory of Ferroelectric and Negative capacitance…………………16

2.6 Why has Ferroelectric Negative Capacitance never been observed until
now ………………………………………………………………………18

Chapter 3 Device Structure and Tools


3.1 Device Structure……………………………………………………..…….21
3.2 SILVACO ATLAS……………………………………………………..….22
3.3 Model Development in ATLAS………………………………………...….23
3.3.1 Meshing……………………………………………………………...23
3.3.2 Regions …………………………………………………………....24
3.3.3 Device Electrode…………………………………………………….25
3.3.4 Doping……………………………………………………………….26
3.3.5 Material……………………………………………………...………27
3.3.6 Models……………………………………………………………….27
3.3.7 Numerical Method Selection………………………………………...29
3.4 Simulation Parameters…………………………………………………….29
Chapter 4 Simulation Results and Discussion
4.1 Results……………………………………………………………………...30
Chapter 5 Conclusion and Future Scope
5.1 Conclusion……………………………………………………………….....35
5.2 Limitation…………………………………………………………………..35
5.3 Future Scope of work…………………………………………………….....35
References……………………………………………………………………………….36

vii
List of Figures
1.1 First transistor made in Bell’s LAB in 1948……………….……………………......1
1.2 Transistor scaling over the years has followed the well-known Moore’s law
resulting in 2X increase in transistor count every two years. With each generation of scaled
technology the transistor performance has been improved. Beyond the 22 nm node Tri-
gate/Multi-gate devices, Ge and III-V MOSFETs/QW-FETs, TFETs and a host of other
novel devices are being explored……………………………………….………………….3
1.3 To maintain constant power density, both the supply and the threshold voltages of a
CMOS integrated circuit should be reduced along with the lithographic dimension of
CMOS transistors. But due to MOSFET subthreshold leakage, both VDD and VT scaling
have slowed down in recent technology
generations……………………………………………………...……………………...….4
1.4 (a)Rising transistor count in INTEL microprocessor chip(b) The total power
dissipation in modern CPU is limited to around 100
Watt…………………………...……………………………………………….……….….5
2.1 (a)Schematic diagram of a metal-oxide-semiconductor field-effect-transistor
(MOSFET). (b) The output characteristics of a MOSFET. We are in search of a low-power
device with less than 60 mV/decade of subthreshold swing…………………………….….7
2.2 Potential profile in a nanoscale transistor. The capacitor network shows how the
applied gate voltage is divided between the oxide insulator and the
semiconductor……………………………………………………………………………..9
2.3 Charge-voltage characteristics and energy landscapes of a positive capacitance (a) and
a negative capacitor(b)……………………….......………………………………….11
2.4 Energy landscape of a ferroelectric materials. The region under the dashed box
corresponds to the negative capacitance state……………....……………….......………..12
2.5 Relationship between the piezoelectric class and its subgroups within the 32 symmetric
point groups……………………………………………………………………………....14
2.6 (a) Unit of cell of a classical ferroelectric PbTiO3. The opposite off-centering of the
central ion corresponding to the two different polarization states are shown. (b) The
switching of the polarization of a ferroelectric capacitor upon the application of a voltage
larger than the coercive voltage………………………………………………………….16

viii
2.7 Polarization-voltage hysteresis characteristics of a ferroelectric capacitor. The energy
landscapes at different points on the hysteresis curve are also shown…………………….17
2.8 Charge (or polarization)-voltage characteristics of a ferroelectric material according to
the Landau theory. The capacitance is negative in a certain region of charge and voltage
which is indicated by the dotted line…………………………………………….....……..18
2.9 Negative capacitance state is unstable and the polarization spontaneously rolls downhill
from a negative capacitance state to one of the minima making a direct measurement of the
phenomenon experimentally difficult…………………………………………………....19
2.10 An LCR meter cannot directly measure a ferroelectric negative capacitance……….19
3.1 ATLAS inputs and outputs……………..…………………………………………....22
3.2 Meshing of SOI standard FET…………………..…………………………………...24
3.3 Different regions of SOI standard MOSFET……………..………………………….25
3.4 Cross section of SOI standard MOSFET showing doping in different regions and
electrodes……………………………………………………………………………...…26
4.1 Drain current (ID) v/s Gate Voltage (VG) characteristics of simulated Standard
MOSFET for bias voltage VDS =0.5V…………………………………………………….30
4.2 Logarithmic Drain current [log (ID)] v/s Gate Voltage (VG) characteristics of simulated
standard MOSFET for bias voltage VDS=0.5V………………………………………...…31
4.3 Structure of Negative Capacitance MOSFET with PZT gate stack on oxide
Layer…………………………………………………………………………………..…32
4.4 Transfer characterstics of NC-MOSFET versus STANDARD MOSFET…………...34

List of Tables
3.1 ATLAS Command Groups with primary statements in each group…………………18
3.2 Description of different models used in this project…………………………………23
4.3 Drain Current versus Gate Voltage for MOSFET and NCFET……...........................28

ix
LIST OF ABBREVIATIONS

2D Two Dimensional
CTotal Total Capacitance
CFe Ferroelectric Capacitance
CMOS Metal Oxide Semiconductor Capacitance
DG Double Gate
FEFET Ferroelectric Field Effect Transistor
MOSFET Metal Oxide Semiconductor Field Effect Transistor
NCFET Negative Capacitance Field Effect Transistor
PZT Lead Zirconate Titanate Pb [ZrxTi1-x] O3 (0≤x≤1)
TCAD Technology Computer Aided Design
TFET Tunnel Field Effect Transistor

x
Chapter 1
Introduction

This chapter delineates the evolution of MOSFET as a part of integrated circuit over the
last 50 years. It also draws attention towards one of the most daunting problem viz. power
crisis of today’s nanoelectronics and shows how this unnerving issue can be circumvented
by alternative device architectures. Among these alternative architectures, NCFET stands
out to be the most propitious candidate for future low power applications. Brief overviews
of NCFET, objectives and methodology of this project have also been presented in this
chapter.
1.1 Development in the field of Semiconductors

Figure 1.1: First transistor made in Bells LAB in 1948

The first Bipolar Junction transistor shown in Fig. 1.1.1 was built in 1948 at Bell
labs. Later, in 1958, Texas Instruments demonstrated their first integrated circuits. Gordon
E. Moore, one of the founders at Intel, had observed the ongoing trend of the integrated
Circuit development and noted that the number of transistors in a fixed die area will double
in every 18-24 months. Several scaling laws were emerged after Moore’s prophecy.
Dennard’s scaling is one of those stated scaling laws.

1
In today's semiconductor devices, more importance is given to the speed and battery life of
the device. On a fixed die, higher the number of transistors fabricated, higher are the
functions to build on it.

1.2 Dennard’s Scaling Law


Following the Moore’s prophecy, Dennard’s Scaling law states that the transistors
become faster, consume less power, and are cheaper to manufacture as they shrink. Thus,
the Operational characteristics of a MOS transistor can be preserved and the performance
is improved if the critical parameters are scaled down. Critical Parameters are:
 Device dimensions
 Device voltages
 Device densities
It is also known as the constant field scaling as both power supply and device dimensions
scale down. Power dissipation is becoming a major concern with the current market
scenarios. With the current scaling trend, power dissipation for every transistor reduces by
a factor of two keeping the frequency constant. In order to support the power scaling, the
power supply should be reduced. However, with the Vdd scaling, threshold voltage (Vth)
should also scale simultaneously to maintain the drive current. But Vth does not follow the
scaling trend as expected. Power dissipation has increased drastically until the early 2000’s
due to frequency increase with considerable pipelining.

1.3 Scaling Trend of MOSFET and Power Crisis in Nanoelectronics


In logic circuits, MOSFETs operate as switch and in this regime speed and power
consumptions are major concerns. To achieve higher speed and lower power consumption,
the dimensions of MOSFETs have been shrunk continuously because the capacitance of
logic nodes decreases as the dimensions of MOSFETs decreases. A smaller capacitance
results in a shorter switching time, t and a smaller switching power, P of a logic circuit.
The relationship between capacitance, switching time and switching power are:
t = CVD /ID (1.1)
P = CF V2D/ 2 (1.2)
Where, VD is the supply voltage and f is the clock frequency. In fact the feature size of
MOSFETs or minimum line width used for a MOSFET has kept shrinking at an average

2
rate of 0.7 times about every two to three years over the past four decades, which has
resulted in a line width reduction of a factor of 1/500 and a MOSFET area reduction of
1/250000 since 1970s. Because of the downsizing of MOSFETs the number of MOSFETs
in an integrated circuit was doubled every two or three years. This is well known as
Moore’s Law [3] which was proposed by Gordon Moore in 1966.

Figure 1.2: Transistor scaling over the years has followed the well-known Moore’s
law resulting in 2X increase in transistor count every two years. With each generation
of scaled technology the transistor performance has been improved. Beyond the 22
nm node Tri-gate/Multi-gate devices, Ge and III-V MOSFETs/QW-FETs, TFETs and
a host of other novel devices are being explored [4].

The downsizing of MOSFETs contributes to the performance enhancement in two


ways: shorter switching time of MOSFETs and parallel processing capability. It should
also be noted that with downsizing, the cost and power dissipation per MOSFET also
become smaller. Clearly, the downsizing of MOSFET is critically responsible for the
improvement of density, power and performance of integrated circuits.

3
The reduction in the feature size of MOSFET necessitates a corresponding diminution in
the supply voltage at which the transistor operates. As can be verified from eq (1.1) and
(1.2), the scaling of the supply voltage is required in order to reduce the dynamic power, P
and switching time, t of the transistor.
The downsizing of MOSFET attains performance enhancement through a combination of
reduced capacitances, increased drive current and scaled supply voltage. The ON current
per unit µm width for advanced CMOS transistor [5] is given by

IDS.SAT = βCox (VD – VT) α (1.3)

Figure 1.3: To maintain constant power density, both the supply and the threshold
voltages of a CMOS integrated circuit should be reduced along with the lithographic
dimension of CMOS transistors. But due to MOSFET sub-threshold leakage, both
VDD and VT scaling have slowed down in recent technology generations.

Where, β is the proportionality constant and α is the fitting parameter which takes a value
between 1 and 2 depending on the channel length and VT is the threshold voltage.

4
It is evident from equation (1.3) that in order to maintain or enhance ON current ID,
threshold voltage VT needs to be scaled at least as rapidly as VD. In traditional MOS
transistor the sub threshold swing, S (defined as dVG /d (log ID)) is dictated by the diffusion
of carriers from the source to the channel of the device. Therefore, the carriers at the
Boltzmann tail of Fermi-Dirac distribution (i.e. hot/high energy carriers) take part in this
OFF state transport phenomena, which inevitably puts a thermodynamic limit of
(kT/q)ln(10) = 60mV/decade on the sub threshold swing of the device. In any transistor
with sub threshold swing S, ID at zero VG is given by the following expression.
ID(VG = 0) = ID(VG = VT) exp (−VT /S) (1.4)

(a) (b)
Figure 1.4: (a) Rising transistor count in Intel microprocessor chips, (b) The total
power dissipation in modern CPU is limited to around 100 W [6].

This current is termed as the static or sub-threshold leakage current of the transistor since
it represents the amount of current flowing in the logic gates in the quiescent state. Apart
from that, the number of transistors per chip has doubled every two years and both these
factors have caused an exponential rise in the leakage power of the chip.
In modern multi-core CPU’s the total power dissipation is limited to around 100 W due to
thermal issues. But, more transistors are required with each generation of scaled technology
to meet the ever increasing demand for higher functionality.

5
1.4 Motivation
Because of the increasing demand of high performance electronic components, high
power dissipation takes place. This leads to
 High effort for cooling
 Increasing operating cost
 Reduced reliability & mobility
 Higher weight (Batteries) etc.

Because of previous mentioned problems we are forced to look for low power techniques
to solve these. . For 22 nm node and beyond a host of new devices and materials are being
investigated, trying to address this most critical bottleneck to transistor scaling i.e. the
power dissipation. In order to surmount this limit of 60mV/decade a number of super steep
subthreshold slope devices has recently been proposed to the literature such as Impact
Ionization MOS[7]-[10] Nanoelectromechanical FET[11]-[12], FeFET[13] and Tunnel
FET[14]-[15]. This work studies designing and simulation of a Negative capacitance
MOSFET. The proposed device is mainly based on ferroelectric gate oxide.

6
Chapter 2
Literature Overview
This chapter focuses on ferroelectric materials and their applications. It provides additional
details beyond what was described in Chapter 1. This chapter discusses the properties of
ferroelectric materials and negative capacitance

Figure 2.1: (a) Schematic diagram of a metal-oxide-semiconductor field-effect-


transistor (MOSFET). (b) The output characteristics of a MOSFET. We are in
search of a low-power device with less than 60 mV/decade of subthreshold swing.

The reason why the power supply voltage in microprocessors has not scaled at par
with the transistor dimensions originates from the fundamental physics of transistor
operation. The Boltzmann distribution dictates that, to increase the drain current ID by an
order magnitude at room temperature, the gate voltage VG needs to be increased by at least
KBTlog10=60 mV, KB and T being the Boltzmann constant and the temperature,
respectively. Hence the lower limit of the sub-threshold slope S, defined as 𝜕𝑉𝐺 ⁄𝜕𝑙𝑜𝑔10 𝐼𝐷
is 60 mV/decade. To maintain a good on-off ratio of the current, ∼1 V needs to be applied
at the gate. This limitation has been termed as the “Boltzmann Tyranny” and this is a
fundamental physical bottleneck.
However much engineering is put into a transistor design, the sub threshold slope cannot
be lowered below this limit. It is now generally agreed that, without introducing new

7
physics into the physics of transistor operation, this limitation cannot be overcome. As a
result, there has been an industry-wide call for “reinventing the transistor” [16]-[19].
To overcome this problem in the conventional transistors, a number of alternative
approaches are currently being investigated. Examples include band-to-band tunneling
field effect transistors (TFET) [20, 21], impact ionization metal oxide semiconductor
transistors (IMOS) [22] and also nano-electro mechanical (NEM) switches [23, 24]. In
these approaches the mechanism of transport, i.e., the way electrons flow in a transistor, is
altered such that the minimum limit of 2.3kBT/q can be avoided. In contrast, it was
theoretically shown that it may be possible to keep the mechanism of transport intact, but
change the electrostatic gating in such a way that it steps up the surface potential of the
transistor beyond what is possible conventionally. The basic principle of such “active”
gating relies on the ability to drive the ferroelectric material away from its local energy
𝑑𝑄
minimum to a non-equilibrium state where its capacitance ( 𝑑𝑉 ) is negative and stabilizing

it there by adding a series capacitance. In the next several sections, we shall discuss this
mechanism.
2.1 Negative Capacitance to recue
The idea for negative capacitance to reduce the sub threshold slope below 60
mV/decade was proposed in 2008. The proposal is to replace the gate oxide with a negative
capacitance material [13]. To understand how negative capacitance may help reducing the
supply voltage and hence energy dissipation in conventional transistors, we start by noting
that a field effect transistor could be thought of a series combination of two capacitors: the
gate oxide capacitor Cox and the semiconductor capacitor Cs as shown in figure (2.2). In a
conventional transistor, where Cox is a positive quantity, the equivalent capacitance of the
series network would be smaller than that of each of the constituent capacitors. On the
other hand, when Cox is negative, the equivalent capacitance would be larger than Cs
provided |Cox| > |Cs|. This is surprising considering that in a series network of two ordinary
capacitors the total capacitance must be smaller than either of the constituent capacitances.

8
Figure 2.2: Potential profile in a nanoscale transistor. The capacitor network shows
how the applied gate voltage is divided between the oxide insulator and the
semiconductor.

Now the reduction in supply voltage can be understood in the following way: since
the total capacitance is enhanced by having a negative Cox, it requires less voltage to
produce the same amount of charge Q across the capacitors, Cs and Cox, both of which have
the same Q due to being in series. The current in the channel is proportional to the charge
across Cs. This means that the same amount of current can now be produced with smaller
voltage. Perhaps a more intriguing aspect of the network in Fig. 2.2 is the fact that the
internal node voltage, ψs is larger than gate voltage VG due to the presence of a negative
Cox. This makes the channel ‘see’ a larger voltage than what was actually applied.
Recognizing that the Boltzmann factor is given by 𝑒𝑞𝜑𝑠 /𝐾𝐵 𝑇 , the minimum voltage
required to increase current by one order of magnitude is 2.3 KBT/rq.
Conventionally, r = ψs/VG < 1; but in this case, r > 1 since Cox < 0. As a result the
minimum voltage (to increase current by one order of magnitude) reduces below 60 mV at
room temperature.

9
Mathematically, subthreshold swing S is defined as:
𝜕𝑉𝐺 𝜕𝑉𝐺 𝜕𝜓𝑠
S= = (2.1)
𝜕𝑙𝑜𝑔10 𝐼𝐷 𝜕𝜓𝑠 𝜕𝑙𝑜𝑔10 𝐼𝐷

In figure 2.1(b), the region below where the current saturates is known as the subthreshold
region. S provides an estimate for how steeply the current is increasing with voltage. The
lower the value of S, the steeper the curve and vice versa. Going back to Equation 2.1, one
would see that the expression can be written as a product of two terms. To understand these
terms, let’s look at figure 2.2 which also shows a simplistic view of the relationship
between the capacitor network to the potential profile in a nanoscale transistor. Note that
here the channel-drain or channel-source coupling capacitors are not drawn explicitly.
These capacitances are rather lumped into the semiconductor capacitance itself. This
treatment does not change the physical scenario that explained here. The internal node
voltage, ψs, also called the surface potential, controls the current flow over the barrier. The
second term determines the inverse of how much current flows as a function of ψs. This
term is dictated by the Boltzmann factor 𝑒𝑞𝜑𝑠 /𝐾𝐵 𝑇 , and can only give an S of 2.3KBT/q
(=60 mV/decade) at room temperature. Clearly, as long as the transport mechanism of
electrons is not altered from a barrier modulated transport, the second term is a fundamental
one and provides only 60mV/decade of the subthreshold swing. This is the motivation
behind TFET [20, 21], IMOS [22] and NEMFET [23-24] as mentioned before, where the
mode of transport is changed. The negative capacitor approach effects the first term. This
term is simply the ratio of supply voltage, VG to the internal node voltage, ψs which can
be written as
𝜕𝑉𝐺 𝐶𝑠
m= =1+ (2.2)
𝜕𝜓𝑠 𝐶𝑜𝑥

This ratio, often called the ‘body-factor’ in the MOSFET literature, will always be larger
than 1 because of the voltage divider rule in conventional capacitors.
Thus ordinarily S cannot be less than 60 mV/decade. However, if the conditions Cox< 0

and |Cox| < |Cs|, can be satisfied, m could be made to be less than one leading to an overall
S which is less than 60 mV/decade. Obtaining an effective negative Cox is the main
objective of this report.

10
2.2 Capacitance: Positive and Negative

Figure 2.3: Charge-voltage characteristics and energy landscapes of a positive


capacitance (a) and a negative capacitor (b).

A capacitor is a device that stored charge. Capacitance of a device C is defined as the rate
𝑑𝑄
of increase of the charge Q with the voltage V (C =𝑑𝑉 ). Hence, by definition, for a negative

capacitor, Q decreases as V is increased (figure 2.3(a)). Alternatively, capacitance can also


be defined in terms of the free energy U. For a negative capacitor, the energy landscape is
an inverted parabola (figure 2.3(b)).
𝑄2
For a linear capacitor, U = . In terms of free energy, the capacitance can be defined as
2𝐶
follows.

𝜕2 𝑈
C= [ ]-1 (2.3)
𝜕𝑄2
The same relation holds also for a non-linear capacitor. In other words, the negative
curvature region in the energy landscape of an insulating material corresponds to a negative
capacitance.

11
2.3 How to realize Negative Capacitance: The case of Ferroelectric oxides
Which insulating materials have a negative curvature in their energy landscape? The
energy landscape of a ferroelectric material is shown in figure 2.4. It has two degenerate
energy minima. This means that the ferroelectric material could provide a non-zero
polarization even without an applied electric field. In general, the total charge density in a
given material can be written as QA = ϵE+P, where ϵ is the linear permittivity of the
ferroelectric, E is the external electric field and P is the polarization. In typical ferroelectric
materials, P >> E leading to QA ≈ P. For this reason we shall use P and QA interchangeably.

Figure 2.4: Energy landscape of a ferroelectric materials. The region under the
dashed box corresponds to the negative capacitance state.

Since charge density is what we are interested in, we shall also drop the subscript A and
simply use Q for charge density. If we compare the characteristic ferroelectric energy
landscape (figure 2.4) with that of an ordinary capacitor shown in figure 2.3(b), we would
see that the curvature around Q = 0 of a ferroelectric is just the opposite of that of an
ordinary capacitor.

12
𝑄2
Remembering that the energy of an ordinary capacitor is given by ( ), this opposite
2𝐶
curvature already hints at a negative capacitance for the ferroelectric material around Q =
0. Therefore, around this point, a ferroelectric material could provide a negative
capacitance.
2.4 An Introduction To Ferroelectric Oxides
A ferroelectric is an insulating material with two or more discrete stable or metastable
states of different nonzero electric polarization in zero applied lactic field, referred to as
“spontaneous” polarization. For a system to be considered ferroelectric, it must be possible
to switch between these states with an applied electric larger than the coercive field, which
changes the relative energy of the states through the coupling to the field to the polarization.
The polarization switch-ability criteria for a ferroelectric material and, in fact, the term
“Ferro-electricity” was established through the work of Joseph Valasek, who, in 1921,
demonstrated the hysteretic nature of the polarization of Rochelle salt: NaKC4H4O6.4H2O
and its dependence on temperature [25]. Research in inorganic ferroelectric ceramics
received an impetus during the WWII and the ferroelectric nature of the ceramic BaTiO3
was first demonstrated in 1945 by applying an external field, electrically aligning, or
“polling”, the domains within the grains [25]. Research and development in piezoelectric
transducers paved the way for research in other ferroelectric Perovskite compounds from
1950 to the 1970s, most notably lead Zirconate (PbZrO3): lead Titanate (PbTiO3) ceramic
systems for their high Curie temperatures [25]. Ferroelectric material class can further be
sub grouped into pyrochlores, perovskites, layer structures, tungsten bronze structure etc.
Non-Centro symmetry of the crystal structure plays an important role in Ferro electricity
and negative capacitance phenomenon in ferroelectrics is essentially structurally driven.
The Non-Centro symmetric nature is essential in producing electric dipoles, and thus
collectively the vector quantity: polarization. All crystals can be categorized into 32
different classes, or point groups, based on their symmetry elements as shown in figure 2.5
[26]. Among the 32 point groups, 11 classes are centrosymmetric and 21 are
noncentrosymmetric. Of the 21 noncentrosymmetric point groups, 20 are piezoelectric
classes, which consist of materials with the ability to electrically polarize when subjected
to stress and strain [26]. Among the piezoelectric class, 10 are Pyroelectric, consisting of

13
materials that can develop spontaneous polarization and form permanent dipoles in the
structure as a function of temperature

32
Symmetry Point Groups

21 11
Non-centrosymmetric Centrosymmetric
(Non -Piezoelectric)

20
Piezoelectric
(Polarized under stress)
)

10
Pyroelectric
(Polarized under stress)

Subgroup Ferroelectric
(Spontaneously polarized, reversibility
under applied electric field)

Tungsten Bronze Oxygen Pyrochlore Layer Structure


(PbNb2O6) Octahedral (Cd2Nb2O7) (Bi4Ti2O12)

Perovskite
(ABO3)

BaTiO3 PbTiO3 Pb (ZrxTi1-x) O3 PMN (NaK)NbO3


pbTP
Figure 2.5: Relationship between the piezoelectric class and its subgroups within the
32 symmetric point groups [26].

14
Ferroelectrics are a subgroup in pyro electrics which not only possess unique, stable polar
axes (piezoelectricity), and exhibit spontaneous polarization (pyro electricity), but are also
capable of reversing their polarization by an external electric field [26].
In this report, we will explore the negative capacitance effect only in tetragonal
Perovskite ferroelectrics. Perovskite ferroelectrics belong to a large class of materials
called the complex oxides. Typical chemical symbol of Perovskite complex oxide is ABO3,
where B is a transition metal element. Due to the partially filled/unfilled d or f orbitals in
the transition metal element, a wide range of interesting properties are observed in complex
oxide including high temperature superconductivity, Ferro electricity, antiferroelectricity,
multiferroicity. Let us consider the case of a classical Perovskite ferroelectric: PbTiO3
(PTO). Figure 2.6(a) shows the unit cell of PTO. In this case, the central 𝑇𝑖 4+ is not at the
center of the symmetry of the unit cell; rather it is off- centered and hence the crystal
structure is non-centrosymmetric. This off-centering of the central ion results in a
spontaneous dipole moment or electric polarization in the material. The unit cell of PTO is
tetragonal (crystal class P4mm), which means that the one of the side of the cell is longer
than the other two (i.e. c > a) and all the angles between the sides are 90° . The off-centering
of the central ion δ is of the order of picometers resulting in the “spontaneous polarization”
𝑞𝛿⁄
P= =∼0.5 𝐶⁄𝑚2 . The off-centering of the central atom in the two opposite
𝑐𝑎2
directions corresponds to the two different minima of the ferroelectric energy landscape
shown in figure 2.4. Figure 2.6(b) shows the switching of the polarization up on the
application of a voltage larger than the coercive voltage. Figure 2.7 shows the polarization-
voltage hysteresis characteristics of a ferroelectric capacitor and the energy landscape
corresponding to different points of the hysteresis loop. The properties of a ferroelectric
material are strongly dependent on temperature.

15
Above a critical temperature, called the Curie temperature, a ferroelectric material goes
through a phase transition transforming into a paraelectric. In the paraelectric phase, the
material does not have any spontaneous polarization and is akin to a regular dielectric.

Figure 2.6: (a) Unit of cell of a classical ferroelectric PbTiO3. The opposite off-
centering of the central ion corresponding to the two different polarization states are
shown. (b) The switching of the polarization of a ferroelectric capacitor upon the
application of a voltage larger than the coercive voltage.

2.5 Landau Theory of Ferroelectrics and Negative Capacitance


The Landau theory is a symmetry based phenomenology that serves as a conceptual
bridge between the microscopic models and the observed macroscopic phenomena. It
assumes a spatial averaging of local fluctuations. As a result, it is particularly well suited
to systems with long range interactions such as ferroelectrics and superconductors. In his
classic 1937 papers, Landau noted that a system cannot change smoothly between two
phases of different symmetries. Because the thermodynamic states of two phases that are
symmetry-wise distinct must be the same at their shared transition line, the symmetry of
one phase must be higher than that of the other. Landau then characterized the transition in
terms of an order parameter, a physical entry that is zero in the high symmetry (disordered)
phase and changes continuously to a finite value when the symmetry is lowered. For the

16
case of a ferroelectric-paraelectric transition, this order parameters is the polarization and
the high and low symmetry phases correspond to the paraelectric and the ferroelectric states
respectively. The free energy of U is then expanded as a power series of the order parameter
P where only symmetry compatible terms are retained. The state of the system is then found
by minimizing the free energy U (P) with respect to P to obtain the spontaneous
polarization 𝑃° . The coefficients of the series expansion U (P) can be determined from
experiments or from first principle calculations.

Figure 2.7: Polarization-voltage hysteresis characteristics of a ferroelectric capacitor.


The energy landscapes at different points on the hysteresis curve are also shown.

For a ferroelectric, the free energy U (P) can be represented as an even order polynomial
of the polarization P, which is as follows.
U = αP2 + βP4 + γP6 - EP (2.4)
Here, E = 𝑉⁄𝑑 is the applied electric field; V and d are the voltage applied across the

ferroelectric and the ferroelectric thickness respectively. α, β and γ are anisotropy

17
constants. β and γ are temperature independent. γ is a positive quantity; β is positive and
negative respectively for second order and first order phase transition.
Furthermore, at equilibrium, 𝑑𝑈⁄𝑑𝑃 = 0, which, combined with equation 2.4, results in the
following relation
E = 2αP + 4βP3 + 6γP5 (2.5)

Figure 2.8: Charge (or polarization)-voltage characteristics of a ferroelectric material


according to the Landau theory. The capacitance is negative in a certain region of
charge and voltage which is indicated by the dotted line.

Figure 2.8 shows the polarization-voltage characteristics of a ferroelectric capacitor


obtained using equation 2.5. We note in figure 2.8 that, in accordance with the Landau
theory of ferroelectrics, a ferroelectric capacitor has a non-linear charge-voltage
characteristics in which a negative capacitance can be obtained in a certain range of charge
and voltage indicated by the red dashed curve.

2.6 Why has ferroelectric negative capacitance never been observed until now?
Ferroelectricity is an established discipline in physics and materials science with its
origin back in the 1930s. The Landau theory of ferroelectricity has also been researched
actively since 1930s. And ferroelectricity is a very active field of research with a
publication rate of the order of ten thousand per year. Hence it begs the question “why has
the negative capacitance phenomenon never been explicitly observed in ferroelectric
materials until now?” One of the reasons is the unstable nature of the negative capacitance

18
in a ferroelectric capacitor. If the polarization in placed in the unstable region of the energy
landscape as shown in figure 2.9,

Figure 2.9: Negative capacitance state is unstable and the polarization spontaneously
rolls downhill from a negative capacitance state to one of the minima making a direct
measurement of the phenomenon experimentally difficult.

The ferroelectric capacitor spontaneously self-charges and the polarization rolls


downhill to one of the minima. This is also why, in the conventional experimental
measurement of polarization-voltage characteristics where voltage is the control variable
(figure 2.8), the negative capacitance region is masked by a hysteresis region and sharp
transitions between the two polarization states occur. As a result, a negative capacitance
cannot be directly measured by connecting a ferroelectric capacitor to an LCR meter as
shown in figure 2.10.

Figure 2.10: An LCR meter cannot directly measure a ferroelectric negative


capacitance.

19
Direct observation of negative capacitance in a ferroelectric material requires high
structural quality of the film. And finally, only now there is a significant technological
interest in negative capacitance for reducing power dissipation in electronics and
information paradigm, which makes it the right time to investigate this phenomenon with
rigor. That being said, it is quite interesting that the negative capacitance effects were
observed indirectly as early as 1956 [27, 28], although this fact was not explicitly
mentioned in those early papers.

20
Chapter 3
Device Structure and Tools

3.1 Device Structure


Ferroelectric NC transistors with the metal–ferroelectric––insulators– semiconductor
(MFIS) structure cannot be simulated even with the state-of-the-art device simulators. The
device can be considered as a series combination of a FE capacitor and a conventional
MOSFET. In this report, the device performance of an MFIS structure is numerically
calculated by combining the Silvaco Atlas commercial simulator with the Landau–
Khalatnikov (L-K) theory of ferroelectrics [29]. The 2-D simulation for the STANDARD
MOSFET has been carried out by mean of a Silvaco TCAD commercial simulator [30]
considering the nonlocal path band-to-band model, standard Shockley–Reed–Hall
recombination, drift-diffusion model, and quantum mechanical model. This 2-D hybrid
electrostatics for the STANDARD MOSFET and 1-D Landau model are solved self
consistently to simulate the NCFET. PZT is used as the gate ferroelectric due to its
numerous advantages like reliability, having a sufficient polarization value even in thin
films, high dielectric constant, and most importantly its nanosecond polarization reversal.
Dielectric constant, remnant polarization, standard polarization of PZT material are 1495,
27 µC/cm2, 30 µc/cm2 respectively at low coercive field (37 kV/cm). To reduce the
optimized ferroelectric thickness and improve the NC amplification effect at the same time,
we propose the DG-NCFET. To develop this device, Silvaco TCAD commercial simulator

21
3.2 Silvaco ATLAS
Silicon Valley Company (Silvaco) is a leading vendor in technology computer aided design
(TCAD). Established in 1984 and located in Santa Clara, California, Silvaco has developed
a number of exceptional CAD simulation tools to aid in semiconductor process and device
simulation. The ATLAS device simulator is specifically designed for 2D and 3D modeling
to include electrical, optical and thermal properties within a semiconductor device. ATLAS
provides an integrated physics-based platform to analyze DC, AC and time-domain
responses for all semiconductor-based technologies. The powerful input syntax allows the
user to design any semiconductor device using both standard and user-defined material of
any size and dimension. ATLAS also offers a number of useful device examples to assist
one’s unique design. DeckBuild is the run time environment used to input a command file
or deck and is given the extension ".in". To run ATLAS in the DeckBuild environment, the
user must first call the ATLAS simulator with the command:
Go Atlas
There is other simulation software available that can be used in conjunction with
DeckBuild, such as ATHENA and DevEdit, but in this work we have used only ATLAS.

DevEdit Runtime Output

Structure Files

ATHENA ATLAS Log Files

TonyPlot
Command File
Files
DeckBuild
Solution Files

Figure 3.1: ATLAS Inputs and Outputs

22
Table 3.1: ATLAS Command Groups with primary statements in each group
GROUP STATEMENTS

Structure Specification MESH, REGION, ELECTRODE, DOPING

Material Model Specification MATERIAL, MODEL, CONTACT

Numerical Method Selection METHOD

Solution Specification LOG, SOLVE, LOAD, SAVE

Results Analysis EXTRACT, TONYPLOT

3.3 Model Development in ATLAS


3.3.1 Meshing
The mesh statement is used to define the structure in an inverted 2D or 3D
Cartesian grid. The x-axis is positive from left to right, the y-axis is negative from bottom
to top. The reason for the inverted y-axis is that the manufacturing coordinates are usually
described as depth below the surface. All coordinates are entered in microns and the
spacing is used to refine the sharpness and accuracy at an assigned location. ATLAS
produces a series of triangles to form the mesh based on the user input parameters. Figure
(3.2) shows the mesh of our standard along with the parameters entered in atlas.

23
Figure 3.2: Meshing of SOI standard FET
3.3.2 Regions
The region statement is used to separate the initial mesh statement into distinct
blocks and sets the initial material parameters that can be referred to later by region number.
All meshed areas of a structure must be assigned a region and the regions must be ordered
from lowest to highest region. For instance, region 3 cannot be defined before region 2.

24
Figure 3.3: Different regions of SOI standard MOSFET

3.3.3 Device Electrode


Once the regions are set, the electrodes must be assigned to the desired region so
that it can be electrically analyzed. The electrodes can be assigned to any region or portion
of a region. ATLAS has some fixed names for electrodes e.g. Anode, Cathode, Gate,
Source, and Drain. The following statements were used to define these parameters:
ELECTRODE <position_parameters> NAME=<electrode_name>
The position parameters are specified in microns using the X.MIN, X.MAX, Y.MIN, and
Y.MAX parameters. Multiple electrode statements may have the same electrode name.
Nodes that are associated with the same electrode name are treated as being electrically
connected.

25
3.3.4 Doping
The last required input of the structure specification is the doping statement. The
doping statement is used to assign the doping level within the previously assigned regions.
Various properties can be appended to the doping statement to specify how the
semiconductor was doped and of whether the region is n or p type. The following
statements were used to define doping parameters:
DOPING <distribution_type> <dopant_type> <position_parameters>

Figure 3.4: Cross section of SOI standard MOSFET showing doping in different
regions and electrodes

26
3.3.5 Material
The material statement relates physical parameters with the materials assigned to
the mesh. The important material parameters for most standard semiconductors are already
defined by ATLAS and therefore do not require any changes. For ferroelectric material
defining, we use ferro model for considering ferroelectric effect in gate oxide region.in
addition, the permittivity characteristics, i.e. remnant polarization, spontaneous
polarization, critical electric field and zero field relative permittivity, should be defined for
ferroelectric layer. For Example:
Model region= 3 ferro
Material region=3 ferro.ec=1.1e6 ferro.pr=9.0e-6
ferro.ps=9.5e-6 ferro.epsf=32

3.3.6 Models
The models statement is essential to the accurate modeling of a particular
phenomenon because it sets flags for ATLAS to indicate the inclusion of different
mathematical models, physical mechanisms and other global parameters such as substrate
temperature. The model statements used in this project are listed below:
Model srh dd bbt.nonlocal bbt.nlderivs quantum print

27
Table 3.2: Description of different models used in this project
Model Syntax Comments

Non-Local Path Band-to-Band Model BBT.NONLOCAL Considers the spatial


separation of the
electrons generated
in the conduction
band from the holes
generated in the
valence band.
Drift-Diffusion Model DD Considers Current
densities in the
continuity equations
in Boltzmann
transport theory.
Standard Shockley-Reed-Hall SRH Uses fixed minority
carrier lifetime.
Should be used in
most simulations
Quantum Mechanical Model QUANTUM Considers various
effects of quantum
mechanical
confinement.

As with all ATLAS statements, a complete list of modeling parameters and their definitions
can be found in the ATLAS User’s Manual.

28
3.3.7 Numerical Method Selection
The NEWTON method is useful when the system of equations is strongly coupled
and has quadratic convergence. The NEWTON method may however spend extra time
solving for quantities which are essentially constant or weakly coupled. NEWTON also
requires a more accurate initial guess to the problem to obtain convergence. Method
statement used in this project is as follows:
Method newton
3.4 Simulation Parameters:
Here we used the 2D simulator. It will save our time also as 2D simulation is much
faster than the other one. Followings are the simulation parameters used in this work.
 Channel Length=20nm
 Channel Thickness =6nm
 Material Used: silicon (Si)
 Oxide Thickness=0.7nm
 Channel Doping Level (p+) = 1×1015 cm-3(to resolve convergence issue)
 Source Doping Level (n+) = 8×1020 cm3
 Drain Doping Level (n+) = 5×1020 cm3
 Gate Contact Work Function=4.9
 Oxide Used: SiO2
 Source and Drain Work Function=4.1
 Ferroelectric Material Thickness=2nm
 Supply Voltage =0.5 V
 Models Used=1. Drift-Diffusion model
2. Standard Shockley-Reed-Hall recombination model
3. Non-Local path band-to-band model
4. Quantum model
 Method Used=Newton

29
Chapter 4
Simulation Results and Discussion
4.1 Results:
Since Negative Capacitance cannot be simulated on Silvaco TCAD, so we did the
simulation of standard MOSFET in Silvaco TCAD and then combined with the results of
1-D Landau Model using the formula of amplification factor(β) of NC effect-
𝐶𝐹𝐸
β=
𝐶𝐹𝐸 +𝐶𝑀𝑂𝑆

Since CMOS is a constant and varies with gate voltage; therefore, β is a voltage dependent
parameter. On the other side, to have a nonhysteretic operation, the total capacitance of
gate (C-1Gate = C-1FE + C-1MOS) needs to be positive in the whole range of the gate. After
simulations, we get following graphs:

Figure 4.1: Drain current (ID) v/s Gate Voltage (VG) characteristics of simulated
standard MOSFET for bias voltage VDS =0.5V

30
Figure 4.2: Logarithmic Drain current [log (ID)] v/s Gate Voltage (VG) characteristics
of simulated standard MOSFET for bias voltage VDS=0.5V

31
Figure 4.3: Structure of Negative Capacitance MOSFET with PZT gate stack on oxide
layer.

32
Table No.4.3 Drain Current versus Gate Voltage for MOSFET and NCFET
MOSFET NCFET
Gate Voltage(VG) Drain Current(ID) Log(ID) Drain Current(ID) Log(ID)
0.00E+00 1.79E-13 -12.7474 1.79E-13 -12.7474

5.00E-02 1.01E-12 -11.9957 1.43E-07 -6.84343

1.00E-01 5.56E-12 -11.2552 4.42E-03 -2.35485

1.50E-01 3.05E-11 -10.5159 4.76E-02 -1.32251

2.00E-01 1.67E-10 -9.77696 1.12E-01 -0.9493

2.50E-01 9.13E-10 -9.03945 1.81E-01 -0.74232

3.00E-01 4.97E-09 -8.30398 2.43E-01 -0.61423

3.50E-01 2.68E-08 -7.57154 3.05E-01 -0.51546

4.00E-01 1.43E-07 -6.84343 3.64E-01 -0.43929

4.50E-01 7.56E-07 -6.12173 4.20E-01 -0.37701

5.00E-01 3.89E-06 -5.41018 4.72E-01 -0.32589

5.50E-01 1.92E-05 -4.71661 5.20E-01 -0.2838

6.00E-01 8.73E-05 -4.05905 5.73E-01 -0.24158

6.50E-01 3.37E-04 -3.47274 6.46E-01 -0.18979

7.00E-01 1.01E-03 -2.99539 7.33E-01 -0.13495

7.50E-01 2.34E-03 -2.6312 8.28E-01 -0.08173

8.00E-01 4.42E-03 -2.35485 8.85E-01 -0.05298

8.50E-01 7.26E-03 -2.1393 9.97E-01 -0.00147

9.00E-01 1.08E-02 -1.96558 1.05E+00 0.022237

33
MOSFET NCFET
Gate Voltage(VG) Drain Current(ID) Log(ID) Drain Current(ID) Log(ID)
9.50E-01 1.51E-02 -1.82158 1.07E+00 0.029768

1.00E+00 2.00E-02 -1.69955 1.13E+00 0.052888

1.05E+00 2.54E-02 -1.59435 1.17E+00 0.067918

1.10E+00 3.14E-02 -1.50247 1.26E+00 0.100389

1.15E+00 3.79E-02 -1.42138 1.27E+00 0.10339

1.20E+00 4.47E-02 -1.34921 1.33E+00 0.124125

Using above readings, we plotted it using MS-EXCEL tool.

Figure 4.4: Transfer characterstics of NC-MOSFET versus STANDARD MOSFET

34
Chapter 5
Conclusion and Future Scope
5.1 Conclusion
In summary, a new design space for nonhysteretic Negative Capacitance MOSFET has
been demonstrated on DG NCFETs. PZT is used as the gate ferroelectric, and amplification
factor is calculated using formula for NC effect [eq 3.3].We have shown that the NC effect
leads to enhancement of average subthreshold. It is demonstrated that the high-
performance NEGATIVE CAPACITANCE MOSFET can operate at 0.1 V gate voltage
using 2nm of PZT as the gate ferroelectric. The device average subthreshold swing is
reduced down to 40.3 mV/decade while the reference device’s average SS is 68.1
mV/decade. It has also been presented that using the DG structure reduces ferroelectric’s
optimized thickness by pinning the MOS capacitor in a relatively large value. This
indicates that the DG-NCFET has a transfer characteristic closer to the ideal switch.

5.2 Limitation
 It remains to be seen if ferroelectric negative capacitance does indeed lower the
switching energy of practical transistors.

 Negative capacitance has been observed in different systems such as electrolyte


electrode interfaces, semiconductor Schottky barriers and metal–insulator– metal
structures, but in all these cases energy had to be ‘pumped’ into the system from another
source.
5.3 Future Scope of Work
 Sub-threshold can be bring up-to 0.5 mV/decade by considering negative capacitance
in Four-terminal ferroelectric tunnel FET.
 The proposed model can be extended for heterojunction NCFETs.
 Compact models of NCFETs could be developed following the procedure presented in
this chapter. Such models would be useful to project the performance enhancement in
circuits using NCFETs.
 Dynamic control of antiferroelectric hysteresis loops by drain voltage could enable
novel memory devices.

35
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