Avelino, Anne Loraine L., Galang, Vincent N., Nañoz, Allona Jane M., Punzalan, Justine Roy A.
College of Engineering
School of Technology
First Asia Institute of Technology and Humanities
Abstract— This paper aims to create a simulation and an actual ADC is the fastest kind of analog-to-digital converter. The actual
design of a 3-bit flash analog-to-digital converter (ADC) using op implementation of the ADC uses 8 op amps to produce the desire
amps and priority encoder. 3-bit digital outputs.
I. INTRODUCTION
Flash analog-to-digital converter (ADC) was generated in this The circuit in Figure 2.1 shows the basic configuration of the
experiment. In this paper, it features three segments: Flash ADC Flash ADC. This circuit is also the basis in the simulation. The
section, the inverter and encoder section and the seven-segment reference voltage is set to 8V. However, in biasing the resistors,
display section. the circuit in Figure 2.2 was followed. The resistor is set to 1kilo-
ohms and thus, the first and last resistors were 1.5 kilo-ohms and
Flash ADC, also called the parallel A/D converter, is the 500 ohms respectively.
simplest to understand. It is formed of a series of comparators,
each one comparing the input signal to a unique reference voltage.
The comparator outputs connect to the inputs of a priority encoder
circuit, which then produces a binary output.
1
Figure 2.4: Seven-Segment Display
2
The inversion of the outputs of the comparators is to
comply with the logic input of the encoder. The encoder needs a
logic 0 input in the MSB to give a binary output of 111. However,
the first output of the encoder for decimal “7” is logic 000. But
the decoder needs logic 111 for the “7”, and thus the binary output
is to be inverted.
The design of a Flash converter was used to demonstrate the Figure 3.1
Analog-to-Digital Converter in actual. This design is considered
to be the fastest ADC, which is the side-effect of the unequal Complement to the computation of the ideal voltage, the
values of resistors. actual input voltage of each comparator is measured. The
counterpart of the 1V is 1V, as shown in Figure 3.2.
Setting a constant of 16V as the reference voltage, and a
maximum voltage swing of ±5V in each comparator, the results
of the ADC are then determined.
500Ω
𝟎𝟎𝟏 = (16 𝑉) = 𝟏𝑽
7.5𝑘Ω + 500Ω
1500Ω
𝟎𝟏𝟎 = (16 𝑉) = 𝟑𝑽
6.5𝑘Ω + 1500Ω
2500Ω
𝟎𝟏𝟏 = (16 𝑉) = 𝟓𝑽
5.5𝑘Ω + 2500Ω Figure 3.2 Figure 3.3
3500Ω
𝟏𝟎𝟎 = (16 𝑉) = 𝟕𝑽 Figure 3.3 shows the counterpart of 3V which is of the
4.5𝑘Ω + 3500Ω
same value. Meanwhile, Figure 3.4 is the counterpart of 5V which
4500Ω is equal to 5.01V and Figure 3.5 shows the equivalent of 7V
𝟏𝟎𝟏 = (16 𝑉) = 𝟗𝑽
3.5𝑘Ω + 4500Ω which is 7.01V.
5500Ω
𝟏𝟏𝟎 = (16 𝑉) = 𝟏𝟏𝑽
2.5𝑘Ω + 5500Ω
6500Ω
𝟏𝟏𝟏 = (16 𝑉) = 𝟏𝟑𝑽
1.5𝑘Ω + 6500Ω
Figure 3.11
Figure 3.12
Figure 3.9
Figure 3.13
4
Following the computation for the ideal input voltage, a
3V is set as the input voltage as shown in Figure 3.14. A digital
output of 2 can be seen in the seven segment display and the
second LED indicator is turned on, which represents 010 in
binary.
Figure 3.14
Figure 3.18
Figure 3.15
Figure 3.19
Figure 3.16
Figure 3.19 shows the results in the actual circuit. The
Similar to the previous case, in able to achieve the same input voltage which is supposed to exceed the 7.01V to produce
result as the simulation, their input voltages vary. Once the actual the desired result, is not complied for the circuit already produces
circuit is supplied with a greater value than the comparing voltage the desired output with only a 4V input. Comparing this case to
of the third comparator, 5.02V, the seven segment will display 3 the previous ones, it can be observed that the voltage difference
and the two LED indicators are turned on. However, with only a increases as the desired output increases.
3V input, shown in Figure 3.17, it has already the desired output.
This leads to an observation that the comparing voltage in each
comparator is not satisfied.
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Figure 3.20
Figure 3.23
Figure 3.24
Figure 3.21
Adjusting the input voltage to 13.1V, an output of 7 is
produced as displayed in the seven segment shown in Figure 3.24.
The testing of actual circuit is shown in Figure 3.21 with
The three LED indicators are all turned on representing a binary
the same output as the simulation. Instead of setting the input
equivalent of 111.
voltage that exceeds 9.02V to achieve an output of 5, only 5V is
needed to produce that output. Regarding the voltage difference
between the simulation and the actual testing, it can be observed
that the difference increments a value of 1 as the voltage
increases.
Figure 3.22
𝑽𝒓𝒆𝒇 𝟏𝟔
𝟏 𝑳𝑺𝑩 = = 𝟑 =𝟐
𝟐𝒏 𝟐
𝟎𝟎𝟎 = 𝟎
𝟏− 𝟏
𝟎𝟎𝟎 𝒕𝒐 𝟎𝟎𝟏 = = 𝟎
𝟐
(𝟑 − 𝟏) − (𝟑 − 𝟏)
𝟎𝟎𝟏 𝒕𝒐 𝟎𝟏𝟎 = = 𝟎
𝟐
(𝟓. 𝟎𝟐 − 𝟑) − (𝟓 − 𝟑) Figure
𝟎𝟏𝟎 𝒕𝒐 𝟎𝟏𝟏 = = 𝟎. 𝟎𝟏
𝟐 3.27
(𝟕. 𝟎𝟏 − 𝟓. 𝟎𝟐) − (𝟕 − 𝟓)
𝟎𝟏𝟏 𝒕𝒐 𝟏𝟎𝟎 = = −𝟎. 𝟎𝟎𝟓 DNL error observed from three to five were
𝟐
symmetrical. However, from digital value of five to six, DNL
(𝟗. 𝟎𝟐 − 𝟕. 𝟎𝟏) − (𝟗 − 𝟕) crossed center line (zero). As it approaches seven (final value)
𝟏𝟎𝟎 𝒕𝒐 𝟏𝟎𝟏 = = 𝟎. 𝟎𝟎𝟓
𝟐 DNL error is back to its positive value (0.005). Thus, the
(𝟏𝟏. 𝟎𝟐 − 𝟗. 𝟎𝟐) − (𝟏𝟏 − 𝟗) characteristic of DNL observed applies with the graph for INL
𝟏𝟎𝟏 𝒕𝒐 𝟏𝟏𝟎 = = 𝟎 error.
𝟐
(𝟏𝟑. 𝟎𝟑 − 𝟏𝟏. 𝟎𝟐) − (𝟏𝟑 − 𝟏𝟏)
𝟏𝟏𝟎 𝒕𝒐 𝟏𝟏𝟏 = = 𝟎. 𝟎𝟎𝟓
𝟐 IV. CONCLUSION
The DNL error results above are plotted and is shown Upon simulation, Flash ADC worked smoothly on
in Figure 3.26. Multisim12 using LM741 as comparators. Its output is then fed
to the input of LM7148 (priority encoder) and works just fine. In
contrast to its actual simulation, the group encountered series of
problems along the way. Output voltage of operational amplifiers
was not stable. The group tried first to hook the voltage swing of
the op amp to ground (-) and +5V (+). Although outputs vary,
still, more than 1 V is equivalent to low output. This output cannot
be read as voltage low input for a priority encoder. This is
equivalent to high output which is acceptable since all indicators
were high with the given parameters above. Thus, grounding the
negative swing is inappropriate. The group found solution to the
Figure 3.26 problem by connecting negative voltage to the negative swing.
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By doing so, outputs of op amps have now readable
outputs for the encoder. Moreover, an inverter is needed to negate
the outputs of the comparators before being fed to priority
encoder. This includes inverting the outputs of priority encoder
and leaving the enable input to ground. Also, the group found out
that as the voltage reference increases, accuracy of the output
becomes more evident. However, there is a limit in increasing
voltage reference because it can degrade the operation of
comparators.
Vincent N. Galang
REFERENCES
[1] ADC. [Online]. Available at:
http://ume.gatech.edu/mechatronics_course/ADC_F08.pdf
[2] ADC. [Online]. Available at:
http://www.analog.com/en/products/analog-to-digital-converters.html
[2] Flash ADC. [Online]. Available at:
http://www.allaboutcircuits.com/textbook/digital/chpt-13/flash-adc/