A NEW HIGH-FREQUENCY

VERY LOW OUTPUT-IMPEDANCE

CMOS BUFFER
Kostas Manetakis and Chris Toumazou
Department of Electrical and Electronic Engineering,
Imperial College of Science, Technology and Medicine,
Exhibition Road, London, SW7 2BT, UK
k.manetakis@ic.ac.uk

ABSTRACT 1
Zout = -
gm
A technique to increase the transconductance of the MOS
transistor by employing current feedback is presented and where gm is the small signal transconductance of M1.
applied to the design of a voltage follower. Simulation results
show that the output impedance of the buffer is kept very low
over a wide range of frequencies while the input impedance
remains very high. At the same time this buffer configuration
shows wide bandwidth of operation, ability to drive large
capacitive loads without oscillation and with very good
linearity. Finally an example of a CFOA using this buffer is
presented.

1.INTRODUCTION From above it is obvious that the higher the transconductance

Over the last decade MOS technology has made possible a
tremendous increase in chip size and complexity and thus made
feasible the integration of complete subsystems containing both
analogue and digital parts on the same chip. Currently, in
communication electronics there is a considerable interest in
utilizing CMOS not only for the baseband processing but also
for the mixer and IF functions. High-integration
implementations of transceivers in CMOS require new circuit
design ideas and alternative architectures to overcome the poor
characteristics of the MOS transistor at RF [l].
One of the disadvantages of the MOS transistor over the BJT is
its reduced transconductance gm for the same current. The
transconductance is one of the most important parameters of a
transistor, because it is a measure of the transfer efficiency of
the transistor from input to output. The higher the
transconductance the higher the gain of the transistor. A better
criterion however is the transconductance to current ratio
gm/Ids which measures the efficiency with which the current is
used to create transconductance [2]. For the MOS transistor this
ratio obtains its maximum value in the weak inversion region.
In strong inversion it is inversely proportional to the square root
of the current.
2. INCREASING THE TRANSCONDUCTANCE OF THE
MOS TRANSISTOR
of the transistor the lower the output impedance. A circuit that
increases the transconductance of the MOS transistor is shown
in figure 2.
T T
Figure 2. A Configuration that reduces the Impedance at the
Source terminal.
It comprises two source followers, one implemented with a
NMOS transistor M1 and the other implemented with a PMOS
transistor M2. The current that biases M1 is fed back by the
current mirror with a transfer ratio a.This circuit can be viewed
as a compound transistor. The compound-gate is the gate of M1
and the compound-source is the source of M2. The compound-
drain terminal can be obtained by duplicating the current that
flows out of the drain of M2 using a second output from the
current mirror. A first order analysis of the circuit of Figure 2
assuming a simple model for each transistor and ignoring
output conductance gives

Figure 1 shows a typical common-drain configuration which So it is clear that the gm of the compound transistor, to a first
has an output impedance given by
order approximation, is very high if the current transfer ratio CL
of the current mirror equals

0-7803-3073-0/96/$5.OO O1996 IEEE 485

 T T

a=8,1
8m2

A simpler technique to Figure 2 has been used before [3] for

reducing the impedance at the X node of current conveyors
implemented with bipolar transistors. There is the disadvantage t out

however that if bipolar transistors are employed, current

feedback reduces not only the output impedance but the input
impedance too. Since MOS is used here the input impedance
will remain high, which is a major advantage over the bipolar
case.
Figure 3. The proposed Voltage Follower
3. APPLICATION TO THE DESIGN OF A VOLTAGE
FOLLOWER

Linear high-speed voltage followers find many applications in

the design of communication circuits. Cable drivers for video
circuits is a very important application area. Almost all
operational amplifiers employ output voltage buffers to isolate
the load from the high impedance node. Especially high speed
op amps need output voltage buffers with the ability to drive
large output currents. Additionally voltage buffers are an
important subcircuit of current conveyors and current-feedback
opamps. In all the above applications the voltage followers used
should have very high input impedance, very low input
capacitance, very low output impedance, gain near unity, high
linearity, wide frequency response and in some cases the ability
to drive large capacitive loads without oscillation.
The voltage follower we have implemented using the technique
of Figure 2, is shown in Figure 3. It comprises two compound
transistors, one p-type and one n-type connected in a push-pull
arrangement. In conventional buffer design a trade-off exists
between DC-accuracy and speed. In the voltage follower shown
here, we have used current mirrors implemented with both a p-
type and a n-type MOS transistor (M4-M3 and M7-M8). This
kind of current mirror arrangement acts as NMOS-PMOS gate-
source voltage matching circuit [4]. In this way we compensate
the difference of the gate-source voltages of the Ml-M2 and
M6-M5 n-type p-type transistor pairs, which would normally
appear at the output as an output offset voltage.
A first order DC analysis assuming the simple square law
model for the MOS transistors shows that the voltage at the
output of the buffer is forced to be equal to the input voltage. In
this way the quiescent point of the circuit is well defined (self-
biasing). Essentially the gate-source voltages of M4 and M3 are
forced to be equal. Since MI has the same drain current as M3
and M2 has the same drain current as M4 the gate-source
voltages of MI and M2 are forced to be nearly equal assuming
Q
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I
Figure 4. The conventional Voltage Follower
To evaluate the performance of the circuit it was simulated
using HSPICE and the model parameters of the Northem
Telecom IOV, 0.811BiCMOS process. For the n-type transistors
we have used an aspect ratio 1 5 0 u d l u m while for the p-type
transistors we have used an aspect ratio 390dlu. The power
consumption is 440mW. The offset is -0.3mV. Figure 4 shows
the conventional class AB architecture. The output impedances
of the two circuits are shown in figure 5. The same aspect ratios
and power consumption have been assumed. For the new buffer
of Figure 3 the output impedance is below 20Q up to a
frequency of more than 200MHz. A maximum of 4 5 0 is
achieved at a frequency more than 1GHz. After this frequency
the output impedance decreases as the parasitic capacitances
start to dominate. For comparison a graph of the output
impedance of a conventional buffer architecture (Figure 4) is
also shown. It is seen that the output impedance of the proposed
architecture is much lower except around the peak of the
resonance at about 2GHz.
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all PMOS transistors have the same dimensions and all NMOS IO -
transistors have the same dimensions. Because of inequalities of 0 t . ...
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achieved. Best cancellation is achieved when using a twin-well Figure 5. Output Impedance of the New and the Conventional
technology. However a twin-well process is not strictly Architectures
necessary for high performance. We have assumed a single-well
process in the performance evaluation that follows.

486
This inductive behavior is a characteristic of every circuit that In Figure 9 the current-drive capabilities of the new and the
uses feedback methods to reduce output impedance and can conventional buffers are compared for a 50Cl load. For a lVpp
cause problems when driving capacitive loads since an RLC input voltage the new buffer can drive 20mA into the load,
resonator is fdrmed. To estimate the implications of the whereas the conventional buffer working at the same biasing
inductive behavior described above to the frequency response currents can drive 16mA. This improved current-drive
when driving capacitive loads, the small-signal frequency capability of the new architecture is a very important
response of the new circuit for a 50R //100pF load together with characteristic for applications such as cable drivers in video
the transient response to a 2V step is given in Figure 6 and circuits. For a lVpp sinewave at IOOKHz driving a 50Qload
Figure 7 respectively and compared to the performance of the the THD of the new buffer is 3% compared to 1% for the
conventional architecture. The new architecture offers a conventional buffer.
bandwidth of 144MHz and a 1% settling time of 7.7nSec
compared to 68MHz and ll.2nSec for the conventional
architecture. In Figure 8 the frequency responses are compared
for InF load capacitance. In this case the new buffer gives again
a twofold improvement. It is important to note that the
inductive output impedance of the buffer creates no problems
even when driving large capacitive loads.
0 -

In Figure 10 the small signal voltage transfer for various load

resistances is given as a function of frequency. It can be seen
I 6 ~ that with 5 0 0 load the -3dB frequency is more than 700MHz.

Figure 6. Frequency Response Comparison with 50R NlOOpF

load

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Figure 10. Small Signal Frequency Response for various

Resistive loads

4. APPLICATION TO THE DESIGN OF A CMOS CFOA

Figure 7. Transient Response Comparison with 50Q //100pF As mentioned above voltage buffers are very important
load subcircuits of the current feedback opamp (CFOA). The main
advantages of the CFOA over the more conventional voltage
opamp are the avoidance of the Gain-Bandwidth tradeoff and
the absence of Slew-Rate limiting [3].
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Figure 8. Frequency Response Comparison with 1nF load

In(+)
Capacitance

Figure 1 1. Current Feedback

487
In Figure 11 a CFOA using a version of the proposed buffer is 141 M. C. H. Cheng and C. Toumazou : "3V MOS Current
presented. The specific buffer used is optimized for f2.5V Conveyor Cell for vLsI Technology'', Electronic Letters, 4th
supply. Regulated cascodes are used to enhance the impedance 1993, 29y No.
at the gain node. In Figure 12 is plotted the frequency response
of a typical non-inverting amplifier using the CFOA of figure
11 for various gain values. The total power dissipation is
108mW. The slew-rate is 385VhSec.
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Figure 12. Frequency Response of the CFOA

CONCLUSIONS

A composite MOS transistor based on a technique that uses

current feedback to increase its transconductance has been
presented. A voltage follower has been designed using a p-type
and a n-type composite transistor. The simulation results show
high performance characteristics, namely wide bandwidth, good
linearity, low output impedance even at very high frequencies,
improved current drive capability over the conventional class
AB buffer and ability to drive difficult loads. Finally the
proposed buffer is applied to the design of very high gain-
bandwidth, high slew-rate CMOS CFOA

ACKNOWLEDGMENTS

The work is supported by the UK Engineering and Physical

Sciences Research Council, grant no. GlUJ14547. The authors
wish to acknowledge BNR (Northern Telecom) for technical
support.

REFERENCES

[l] Future Directions in Silicon ICs for RF Personal

Communications, P. R. Gray, R. G. Meyer, CICC May 1995.

[2] Design of Analog Integrated Circuits and Systems, K. R.

Laker, W. M. C. Sansen, McGraw -Hill Inc. 1994

[ 3 ] Emerging Techniques For High Frequency BJT Amplifier

Design: A Current-Mode Perspective, C. Toumazou, J. Lidgey
2% A. Payne, Sponsored by 1994 First International Conference
on Electronic Circuits and Systems, Cairo, Egypt.

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