EE6301- DIGITAL LOGIC CIRCUITS

Anna University Question Bank

UNIT 1: NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES

PART A:
1. Why are digital circuits more frequently constructed with NAND or NOR gates rather
than with AND and OR gates?
2. Perform (11011 - 100101) using 2's complement method.
3. Show that Excess-3 code is self-complementing.
4. Add the hexadecimal numbers: 93 and DE.
5. State the important characteristics of TTL family.
6. In which type of TTL gate wired AND logic is possible.
7. Define fan-in and fan-out characteristics of digital logic families.
8. Why should we take care while using CMOS devices?
9. What are the advantages of CMOS?
10. What is meant by weighted and non-weighted codes?
11. Give examples of weighted codes.
12. List the factors used for measuring the performance of digital logic families.
13. What is the advantage of Gray code over the binary number sequence?
14. Show that the excess-3 code is self-complementing.
15. Encode the ten decimal digits in the 2-out of-5 code.
16. Write the application of Gray code.
17. Define fan-in and fan-out.
18. Differentiate source and sink current.
19. Define power dissipation and propagation delay.
20. Why does propagation delay occur in logic circuits?
21. Define noise margin.
22. List the factors used for measuring the performance of digital logic families.
23. What is meant by tristate capability?
24. State the important characteristics of TTL family.
25. Distinguish between 7400 series and 5400 series.
26. What is the major difference between ECL and TTL?
27. Compare the totem-pole and open-collector outputs.
28. Give any two applications of open collector logic.
29. List the advantages of ECL as compared to TTL logic family.
30. Which is faster TTL or ECL? Which requires more power to operate?

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 31. What is the effect of increasing the supply voltage on the propagation delay of the
CMOS gates?
32. Why should we take care while using CMOS devices?
33. What are the advantages of CMOS?

PART – B
1. Explain the Gray code to binary conversion with necessary diagram.
2. Explain the concept, operation and characteristics of TTL family.
3. Explain the concept, operation and characteristics of ECL family.
4. Draw the TTL inverter circuit.
5. Explain the working of 2-input TTL totem-pole NAND gate.
6. Explain the working of 3-input TTL totem-pole NAND gate.
7. Draw the circuit diagram and explain the working of TTL inverter with tristate output.
8. Discuss about TTL parameters.
9. Name and explain the characteristics of TTL family.
10. Draw and explain the NOR gate using TTL logic.
11. Design a TTL logic circuit for a 3-input NAND gate.
12. Explain the concept, operation and characteristics of CMOS technology.
13. Write a short note on CMOS family.
14. Sketch the typical transfer characteristics of a CMOS inverter.
15. Draw the circuit of a CMOS two-input NAND gate and explain its operation.
16. Draw and explain the circuit diagram of a CMOS NOR gate.
17. Explain the concept, operation, characteristics of CMOS family.
18. Explain the characteristics of CMOS family.
19. Draw the MOS logic circuit for NOT gate and explain its operation.
20. Compare the characteristics of TTL, ECL and CMOS logic families.
21. Compare all the IC logic families based on
a. Power consumption
b. Fan-out
c. Power dissipation
d. Propagation delay
e. Switching speed
f. Noise margin
22. Compare the various digital logic families.
23. Write detailed notes on the working and characteristics of ECL and CMOS logic families.
24. Explain the working of (a)TTL NAND gate with open collector output configuration
(b) TTL inverter with tristate output configuration
25. Draw and explain ECL AND gate.
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 UNIT 2: COMBINATIONAL CIRCUITS
PART A:
1. Distinguish between completely specified function and incompletely specified function.
2. What is the maximum number of outputs for a decoder with a 6-bit data word?
3. Mention the differences between DEMUX and MUX.
4. What is a priority encoder?
5. Draw a 4 x 16 decoder using two 3 x 8 decoders.
6. Show that
7. Draw the truth table and logic circuit of half adder.
8. State Demorgan's theorem.
9. Why is MUX called as data selector?
10. How does don't care condition in K-map help for circuit simplification?
11. What is the difference between decoder and demultiplexer?
12. Express the following switching circuit in binary logic notations.

13. Sketch a half adder using logic gates.

14. Construct OR gate using only NAND
15. Define multiplexer.
16. What are universal gates?
17. Differentiate combinational and sequential circuits.
18. Apply Demorgan's theorem to simplify
19. Simplify the following Boolean expression to a minimim number of literals:
20. Simplify the Boolean expression: , (X+Y) (X+Y')
21. State the associative law of Boolean algebra.
22. State two absorption properties of Boolean algebra.
23. Name the two canonical forms of Boolean algebra.
24. What is variable mapping?
25. What are prime implicants?
26. How can NAND gate be used as an inverter?
27. What is the difference between half adder and full adder?
28. Define canonical form. Express in canonical SOP form.
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 29. Implement Ex-OR gate using only NAND gates.
30. Using K-map simplify the following function and implement the function using logic gates
f(A, B, C)= π(0, 4, 6)
31. Design a logic circuit to simulate the function f(A, B, C) = A (B+C) using only NAND
gates.
32. Realize OR and Ex-OR gates using only NAND gates
33. What is the drawback in binary parallel adder? How can it be rectified?
34. Draw a 4 x 16 decoder constructed with two 3 x 8 decoder.
35. Mention the uses of decoders.
36. What is the maximum number of outputs for a decoder with 6-bit input?
37. Mention the differences between DEMUX and MUX.
38. Give the applications of multiplexer and demultiplexers.
39. Distinguish between demultiplexer and decoder.
PART- B
1. State and prove Demorgan's theorem.
2. Show that the function expressed as a sum of its minterms is equivalent to a function
expressed as a product of its maxterms.
3. Plot the following Boolean function on a Karnaugh map and simplify it.
f(w, x, y, z) = ∑(0, 1,2, 4, 5, 6, 8, 9,12, 13, 14)
4. Solve g(w, x, y, z) = ∑m(1, 3, 4, 6, 11) + ∑d (0, 8, 10, 12, 13)
5. Express the following function as minimum SOP using K-map.
f(a, b, c, d) = S(0, 2,4,5,6,8,10,15) + ∑Φ (7,13,14)
6. Simplify the following switching function using Karnaugh map
F(A,B,C,D)= ∑(0,5,7,8,9,10,11,14,15) + Φ(1,4,13)
7. Simplify using K-map. f(w, x, y, z) = ∑(1,3,7,11,15) and don't care conditions
d(w,x,y,z) = ∑(0,2,5)
8. Simplify using Karnaugh map to obtain a minimum POS expression.
(A'+B'+C+D)(A+B'+C+D)(A+B+C+D')(A+B+C'+D')(A'+B+C+D')(A+B+C'+D)
9. Simplify the following switching function.
f(x1,x2,x3,x4,x5) = ∑m (1,3,6,10,11,12,14,15,17,19,20,22,24,29,30)
10. Simplify using K-map. f(E,D,C,B,A) = ∑m (3,5,6,8,9,12,13,14,19,22,24,25,30)
11. Find the minimum SOP form for the following switching function.
f(x1,x2,x3,x4,x5,x6) = ∑m (2,3,6,7,10,14,18,19,22,23,27,37,42,43,45,46,58,59). Implement
the reduced function using NAND gates only.
12. Construct the Ex-OR gate using 4-NAND gates only. Boolean expression for Ex-OR gate
is

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 13. Implement the following Boolean function using NAND-NAND logic.
Y = AC+ABC+A'BC+AB+D
14. Simplify and implement the following SOP function using NOR gates.
f(A,B,C,D) = ∑m (0,1,4,5,10,11,14,15)
15. Using K-map, simplify the following expression.
Y(A,B,C,D) = m1+m3+m5+m7+m8+m9+m0+m2+m10+m12+m13. Indicate the prime
implicants, essential and non-essential prime implicants. Draw the logic circuit using
AND-OR-INVERT gates and also using NAND gates.
16. Give the simplified expression for the following logic equation where d represents don't
care condition. f(A,B,C,D) = ∑m(0,8,11,12,15) + d (1,2,4,7,10,14). Represent the
simplified expression using logic gates.

17. Prove that is exclusive OR operation and it equals

18. A majority gate is a digital circuit whose output is equal to 1 if the majority of inputs are
1's. The output is 0 otherwise. Using a truth table, find the Boolean function implemented
by a 3-input majority gate. Simplify the function and implement with gates.
19. The inputs to a circuit are the 4 bits of a binary number D 3 D2 D1 D0. The circuit produces
a '1' if and only if all the following conditions hold.
(i) MSB is '1' or any of the other bits are '0'.
(ii) D2 is a '1' or any of the other bits are '0'
(iii) Any of the 4 bits are '0'
Obtain a minimal expression for the output.
20. Define full adder. Draw the logic circuit and truth table of full adder.
21. Design a full subtractor and implement it using logic gates.
22. Design a 4-bit binary ripple adder with full adders and discuss its operation.
23. Design a BCD to Excess-3 code converter using binary parallel adder.
24. Implement the given functions using multiplexer. (i) F(x,y,z) = ∑ (0,2,6,7);
(ii) F(x,y,z) = ∑ (0,3,5)
25. Implement a full adder circuit using 8:1 multiplexer.
26. Explain the concept and working of quadruple 2-to-1 multiplexer.
27. Write a brief note on multiplexer.
28. Implement a full subtractor using demultiplexer.
29. Implement the following multiple output combinational logic circuit using a 4-line to 16-
line decoder. f 1 = ∑ m (1,2,4,7,8,11,12,13), f 2 = ∑ m (2,3,9,11), f 3 = ∑ m (10,12,13,14),
f4 = ∑ m (2,4,8)
30. Design and implement a full adder circuit using a 3x8 decoder.
31. Design a logic circuit to convert the 8421 BCD to Excess-3 code.

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 32. Design and implement an 8421 code to Gray code. Realize the converter using only
NAND gates.
33. Write a brief note on binary to Gray code converter.
34. Obtain minimum SOP using K-map method.
f(A,B,C,D) = ∑m(0,2,4,8,9,10,11,12,13)
35. Determine the prime implicants of the following.
f(A,B,C,D) = ∑m(3,4,5,7,9,13,14,15)
36. Using 8-to 1 multiplexer realize the Boolean function.
f(A,B,C,D) = ∑m(0,1,2,4,5,7,8,9,12,13)
37. Obtain the minimum SOP. F= m0+m2+m4+m8+m9+m10+m11+m12+m13.
i. F= m2+ m3+m4+m6+ m7 m9+m11+m12
38. Implement a full adder using half adders
39. Minimize and implement the following multiple output functions in SOP form.
F1=∑ m(0,2,6,10,11,12,13)+ ∑d(3,4,5,14,15)
F2= ∑m(1,2,6,7,8,13,14,15)+ ∑d(3,5,12)
40. Simplify using K-map.
F(w,x,y,z)= ∑ m(0,1,2,4,5,6,8,9,12,13,14)
41. Solve g(w,x,y,z)= ∑m(1,3,4,6,11)+d(0,8,10,12,13)
42. Design a decimal adder to add two decimal digits.
43. Obtain minimum SOP using K-map method.
f(A,B,C,D) = ∑m(0,1,2,3,4,6,8,10,12,14)
44. Reduce the expression using Boolean algebra.
(i) x'y'z'+x'y'z'+x'yz+xy'z+xyz
(ii) abc'+ab'c+a'bc+abc
(iii) p'q'r+p'qr'+p'qr+pqr'+pq'r'
45. For the given logic diagram, find the Boolean expression.

46. Reduce the following expression using K-map.

f=x'y'z+w'xyz'+wxz+w'xyz
47. Implement a full adder circuit with (a) decoder (b) multiplexer

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 48. Write brief notes on the following. (a) demorgan's theorem (b) Comparators (c) Binary to
Gray code converters (d) Multiplexer
49. Implement the following Boolean function with NAND-NAND logic.
Y= AC+ABC+A'BC+AB+B
50. Simplify and implement the following SOP function using NOR gates. F(A,B,C,D) =
∑m(0,1,4,5,10,11,14,15)
51. Simplify : ((AB'+ABC)'+A(B+AB'))'
52. Express the function F=A+B'C in (a) Canonical SOP (b) Canonical POS form.
53. Design a full subtractor using half subtractors.
54. Solve using K-map: F(A,B,C,D) = ∑m(1,3,5,7,8,16,20,25,31)
55. Design a 3-bit magnitude comparator.
56. Design 2421 to excess-3 code converter.

(NOTE: Solve PART-B: problem No. 34, 35, 37, 43, 54 using Tabular method or Quine
McCluskey method)

UNIT 3: SYNCHRONOUS SEQUENTIAL CIRCUITS

PART A:
1. Define sequential logic circuit. Give an example.
2. What are synchronous sequential circuits?
3. Differentiate between combinational and sequential logic circuits.
4. Differentiate between a latch and flip-flop.
5. What is meant by edge-triggering in a flip-flop.
6. Draw the circuit of SR flip-flop.
7. Realize SR flip-flop using NOR gates.
8. Give the truth table/ state table for D flip-flop.
9. Draw the logic circuit of a clocked JK flip-flop.
10. Sketch the truth table/ state table of JK flip-flop.
11. What is racing condition in a JK flip-flop?
12. Realize a JK flip-flop using only NOR gates.
13. JK flip-flop is a universal flip-flop. Justify.
14. What is the drawback of SR flip-flop?
15. Give the characteristic equation and state diagram of JK flip-flop.
16. Draw the state diagram of SR flip-flop.
17. Draw the state diagram of JK flip-flop.
18. Give the excitation table for SR flip-flop.
19. Give the excitation table for JK flip-flop.

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 20. Give the excitation table for D flip-flop.
21. Convert JK flip-flop to T flip-flop.
22. Convert JK flip-flop to D flip-flop.
23. What is the difference between serial and parallel transfer? What type of register is used
in each case?
24. Show how the JK flip-flop can be modified into a D flip-flop or a T flip-flop.
25. Mention the major application of master slave flip-flop.
26. What is a state?
27. Why is state reduction necessary?
28. Determine the maximum number of binary states and the largest number that can be
counted by 5FF and 6FF configuration.
29. What are synchronous sequential circuits?
30. What is a self-starting counter?
31. How does the state transition diagram of a Moore model differ from Mealy model?
32. What is meant by lockout? How is it avoided?
33. What are state tables and state diagrams in sequential logic circuits?
34. How many flip-flops are required to design a mod 25 counter?
35. What is meant by state assignment?
36. What is meant by transition table?
37. What are the types of shift registers?
38. What do you mean by present state and next state?
39. What is a binary counter?
40. What is a Mealy machine? Give an example.
41. Compare Moore and Mealy circuits.
42. Differentiate between analysis and design of sequential logic circuits.
43. Draw the state diagram of MOD-10 counter.
44. What is the minimum number of flip-flops needed to design a counter of modulus- 60.
45. What is the minimum number of flip-flops needed to design a counter of modulo-21
synchronous counter.
46. How many flip-flops are required to design mod-25 counter?
47. Define registers.
48. Define shift registers.
49. Classify the registers with respect to serial and parallel input and output.
50. What is the difference between serial and parallel transfer? What type of registers is
used in each case?
51. If a serial-in serial-out shift register has N stages and if the clock frequency is f, what will
be time delay between input and output?
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 52. Draw the timing diagram of a 4-bit ring counter.
53. Draw a 2-bit ripple counter and convert it to a 2-bit ring counter.
54. Define universal shift register.
55. Mention the applications of shift registers.
56. What are the advantages of shift registers?
57. What is a ring counter?
PART B:
1. Explain the various types of triggering with suitable diagrams. compare their merits and
demerits.
2. Realize SR flip-flop using NOR gates and explain its operation.
3. Derive the characteristic equation of a SR flip-flop.
4. Draw the circuit of SR flip-flop and explain its operation.
5. Explain the working of JK flip-flop.
6. What is race around condition and how can it be eliminated? Explain these concepts
with relevant timing diagrams.
7. Explain the operation of JK master-slave flip-flop with suitable diagrams.
8. Show that the characteristic equation of Q'(t+1) of JK flip-flop is Q'(t+1) = J'Q' + KQ.
9. Convert SR flip-flop into JK flip-flop.
10. Convert SR flip-flop into D flip-flop.
11. A sequential circuit with 2 D FFs A and B, input X and output Y is specified by the
following next state and output equations.

(i) Draw the logic diagram of the circuit

(ii) Derive the state table
(iii) Draw the state diagram
12. A sequential circuit with 4 FFs A, B, C, D and an input X is described by the following
state equations.

(i) Obtain the sequence of states when X=1, starting from the state ABCD = 0001.
(ii) Obtain the sequence of states when X=0, starting from the state ABCD = 0000.

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 13. A sequential circuit has one flip-flop Q, two inputs x and y, and one output S. It consists
of a full adder circuit connected to a D flip-flop, as shown below. Derive the state table
and state diagram of the sequential circuit shown in Fig. 3.1.

14. Explain the various steps in the analysis of synchronous sequential circuits with a
suitable example.
15. Minimize the state table shown below:
Next state, 'Z' (output)
Present state X (input)
X=0 X=1
A B,0 C,0
B B,0 D,0
C B,0 C,0
D E,1 C,0
E B,0 D,0

16. Minimize the state table shown below:

Next state, 'Z' (output)

Present state X (input)

X=0 X=1

A A,0 B,0
B C,0 D,0
C A,0 D,0
D E,0 F,1
E A,0 F,1
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 F G,0 F,1
G A,0 F,1

17. Construct reduced state diagram for the following state diagram shown in Fig. 3. 2.

18. (i) Reduce the number of states in the following state table and tabulate the reduced
state table.
Next state output
Present state
X=0 X=1 X=0 X=1
A F B 0 0
B D C 0 0
C F E 0 0
D G A 1 0
E D C 0 0
F F B 1 1
G G H 0 1
H G A 1 0

(ii) Starting from state a, and input sequence 01110010011, determine the output
sequence for the given and reduced state table.
19. For a four bit even parity bit generator, input come serially. The four bits of the input
sequence are to be examined by the circuit and circuit produces a parity bit which is to
be added in the original sequence. The circuit should get ready for receiving another four
bits after producing a parity bit for the last sequence. Draw the state diagram and write
down the state transition table.
20. Design a sequential circuit with 4 FF ABCD. The next states of B, C, D are equal to the
present states of A, B, C respectively. The next state of A is equal to the Ex-OR of the
present states of C and D.
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 21. Design a synchronous sequential circuit using JK flip-flop for the given state diagram in
Fig. 3.3.

22. Design a BCD ripple counter using JK flip-flop.

23. Design a synchronous decade counter using D flip-flop.
24. Design a counter with the sequence 0, 1, 3, 7, 6, 4, 0.
25. Design a BCD up/down counter using SR flip-flop.
26. Design a synchronous counter using JK flip-flop to count the following sequence 7, 4, 3,
1, 5, 0, 7.
27. Design and implement a synchronous decade counter using T flip-flop. Draw the timing
diagram.
28. What is meant by universal shift register? Explain the principle of operation of 4-bit
universal shift register.
29. Design Johnson counter and state its advantages and disadvantages.
30. Construct the state diagram of a Mealy pattern detector that can detect a serial string of
4 inputs, where each input is a four bit code. If a string of four 4-bit codes is correctly
received, then an output is generated. An incorrect input code pattern is to generate a
second output. The second output is to be asserted only after receiving the sequence of
four 4-bit codes.
31. Design a BCD counter using T flip-flop.
32. The following sequence is to be realized by a counter consisting of 3 JK flip-flop.
A1 0000110
A2 0110010
A3 0101100
Design the counter.

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 35. Draw the state diagram. Derive the state equation and draw the clocked sequential
circuit for the following state table.
Next state Output
Present state
X=0 X=1 X=0 X=1
AB AB AB Y Y
00 00 01 0 0
01 11 01 0 0
10 10 00 0 0
11 10 11 0 0

36. Draw the state transition diagram of a sequence detector circuit that detects '1010' from
input data stream using Moore model, Mealy model.
37. Design a counter using JK flip-flop for realizing the following sequence.
Q2 Q1 Q0
0 0 0
0 0 1
0 1 1
1 1 1
1 1 0
1 0 0
0 0 0

38. (i) Design a 4-bit synchronous decade counter.

(ii) Sketch the state diagram and state table for 'D' and 'JK' flip-flops.
39. Differentiate between analysis and design of sequential logic circuits.
40. Design a sequential logic circuit for a 3-bit binary counter.
41. Design a counter with the following repeated binary sequence 0, 1, 3, 5, 7. Use T flip-
flop.
42. Design mod-7 counter using D flip-flops.
43. A sequential circuit has two JK flip-flops A and B, two inputs X and Y, and one output Z.
The equations are

Draw the logic diagram and state table.

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 UNIT 4: ASYNCHRONOUS SEQUENTIAL CIRCUITS
PART A:
1. How does the operation of an asynchronous input differ from that of a synchronous
input?
2. What is an asynchronous sequential circuit?
3. What is a fundamental mode asynchronous sequential circuit?
4. Illustrate pulse mode asynchronous circuit.
5. Sketch the block diagram of an asynchronous sequential circuit.
6. How does the operation of an asynchronous input differ from that of a synchronous
input?
7. Define flow table in asynchronous sequential circuit.
8. What is the difference between flow table and transition table?
9. What is race condition in an asynchronous sequential circuit?
10. What are the drawbacks in designing asynchronous sequential circuits?
11. What are hazards?
12. What are static-0 and static-1 hazards?
13. Explain dynamic hazard.
14. What is the cause of essential hazard?
15. What is a PLA?
16. How does the architecture of a PLA differ from a PROM?
17. Whether PAL is same as PLA? Explain.
18. Distinguish between a PAL and PLA.
19. Draw the block diagram of PLA.
20. What is the advantage of PLA over ROM?
21. What are ASM?
22. Define Merger graph.
23. State the hazards in asynchronous sequential circuits.
24. What is the difference between synchronous and asynchronous sequential circuits?
25. Name the types of ROM?
26. What is FPGA?
27. List the configurable elements in the FPGA architecture.
28. Compare ROM, PROM and EPROM memory devices.
29. What are the advantages of PLAs?
30. What are the different classifications of memory?
31. What is Turing machine?
32. What are the terms that determine the size of a PAL?
33. Write a short note on one hot state assignment.
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 34. Define secondary variables.
35. Define closed covering.
36. Define compatibility.
37. List the different techniques for state assignment.
38. What is stable state and unstable state?

PART B:
1. Design a pulse-mode circuit having two input lines x 1 and x2, and one output line z. The
circuit should produce an output pulse to coincide with the last input in the sequence x1-
x2-x2. No other input sequence should produce an output pulse.
2. Design a pulse-mode circuit having two input lines x1, x2 and x3, and one output line z.
The output should change from 0 to 1, only for input sequence x 1-x2-x3 occurs while z=0.
Also the output z should remain in 1 until x 2 occurs. Use SR flip-flop for the design.
3. Derive the flow table for the circuit shown in Fig. 4.1.

4. Consider the following asynchronous sequential circuit as shown in Fig. 4.2 and draw
maps, transition table and state table.

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 5. List and explain the steps used for analyzing an asynchronous sequential circuit.
6. State the condition of stability in asynchronous sequential logic.
7. When does oscillation occur in an asynchronous sequential logic circuit?
8. Develop the state diagram and primitive flow table for a logic system that has two inputs
S and R and single output Q. The device is to be an edge triggered SR flip-flop but with
a clock. The device changes state on the rising edge of the two inputs. Static input
values are not to have any effect in changing the Q output.
9. Design an asynchronous sequential circuit with two inputs X and Y and one output Z.
Whenever Y is 1, input X is transferred to Z. When Y is 0, the output does not change for
any change in X.
10. Design an asynchronous sequential circuit that has two inputs X 2 and X1 and output Z.
When X1=0, the output Z is 0. The first change in X 2 that occurs while X1 is 1 will cause Z
to be 1. The output Z will remain 1 until X 1 returns to 0.
11. Design a two-input (x1, x2), two-output (z1, z2) fundamental-mode circuit that has the
following specifications. When x1x2=00, z1z2=00. The output 10 will be produced
following the occurrence of the input sequence 00-01-11. The output will remain at 10
until the input returns to 00 at which time it becomes 00. An output of 01 will be
produced following the receipt of the input sequence 00-10-11. And once again, the
output will remain at 01 until a 00 input occurs, which returns the output to 00.
12. Design a circuit with inputs A and B to give an output Z=1 when AB=11but only of A
becomes 1 before B by drawing the total state diagram, primitive flow table and output
map in which the transient states are included.
13. Draw and explain the state transition diagram of modulo-6 counter in asynchronous
sequential logic.

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 14. Design an asynchronous sequential logic circuit for the state transition diagram shown in
Fig. 4.3.

15. Describe the steps involved in design of asynchronous sequential circuit in detail with an
example.
16. Define asynchronous sequential circuit, cycles, races, critical races and non-critical
races.
17. When do you get the critical and non-critical races? How will you obtain race free
condition?
18. Describe with reasons, the effect of races in asynchronous sequential circuit design.
Explain its types with illustrations. Show the method of race-free state assignments with
examples.
19. List and explain the steps used for analyzing an asynchronous sequential circuit.
20. Find a way to remove the hazard in product of sum expression given by,

21. What ate hazards in sequential circuits? How can they be eliminated?
22. Explain the various types of hazards in sequential circuit design and the methods to
eliminate them. Give suitable examples.
23. Design a combinational circuit using ROM. The circuit accepts 3-bit number and
generates an output binary number equal to square of input number.
24. Design a ROM for the following functions. ;
25. Draw a PLA circuit to implement the logic functions. and
26. Design a combinational circuit using PLA. The circuit accepts 3-bit number and
generates an output binary number equal to square of input number.
27. Implement the following Boolean functions using PLA. ;

28. Implement the following Boolean functions using PLA. ;

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 29. Design and implement a 4-bit binary to Gray code converter using a PLA.
30. Design an AND-OR-PLA that implements the following functions:
;
31. Generate the following Boolean expressions with PAL with 4 inputs and 4 outputs.
; ;
;
32. A combinational logic circuit is defined by the following function. Implement the circuit
using PAL having three inputs, three product terms and two outputs.
;
33. Design an asynchronous sequential machine that will permit passage of a complete
single clock pulse from a continuous stream of input clock pulses, when an external
input signal is high, the machine is to ignore the case when both the input clock and the
control signal to high at the same time.
34. Describe the following digital circuits. (a) FPGA (b) EPROM
35. Describe the different types of memories.
36. Describe the procedure to get state table from excitation table in an asynchronous
sequential circuit. How does it differ from synchronous sequential circuit?
37. (i)How do you get output specifications from a flow table in asynchronous sequential
circuit operating in fundamental mode?
(ii)When do you get the critical and non-critical races? How will you obtain race free
conditions?
38. What do you understand by FPGA? Explain the operation and applications.
39. Design an asynchronous BCD counter.
40. Describe the characteristics of all types of memories.
41. Implement the following Boolean functions using PROM.; ,

42. Design an asynchronous Modulo-8 down counter using JK flip-flop.

43. Draw and explain the state transition diagram of modulo-6 counter in asynchronous
sequential logic.
44. Write briefly about PLA and EPROM.
45. Discuss about the programmable logic devices.
46. Design an asynchronous sequential circuit whose output respond for every even
numbered clock pulse.
47. Sketch the transition table and state table for an asynchronous sequential circuit
described by the following Boolean expressions. ;
48. Design an asynchronous sequential circuit that will output only the first pulse received.
Any further pulses will be ignored.
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 49. An asynchronous sequential circuit is described by and Z=Y. Draw
the logic diagram, transition table and output map.
50. Find a static hazard free circuit for the given Boolean function.

UNIT 5: VHDL
PART A:
1. What is the need for VHDL?
2. What are the operators present in VHDL?
3. Write VHDL code that illustrates the read and write operations of memory.
4. When can RTL be used to represent digital systems?
5. What are the modeling techniques in HDL?
6. Write HDL code for half-adder.
7. What are the advantages of hardware languages?
8. Write VHDL code for half-adder in data flow model.
9. Write VHDL code for 2 x 1 MUX.
10. What are the advantages of package declaration over component declaration?
11. Write the VHDL code for AND gate.
12. What is the meaning of the following statements in RTL? T 1: ACC <- ACC and MDR.
13. Write the behavioral model of D flip-flop.
14. Define RTL.
15. What is meant by package?
16. What are miscellaneous operators?
17. Define entity in a VHDL module.
18. Define architecture in a VHDL module.
19. What is data flow model?
20. What is structural model?
21. What is behavioral model?
22. What is test bench?

PART B:
1. Discuss briefly the use of 'packages' in VHDL.
2. Explain the concept of behavioral and structural modeling in VHDL. Take an example of
full-adder and write codes for both type of modeling.
3. List and briefly explain the different data types supported in VHDL.

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 4. Construct a VHDL module listing for a 16 x 1MUX that is based on the assignment
statement. Use a 4-bit select word S3, S2, S1, S0 to map the selected input Pi (i=0,...15) to
the output.
5. Write the HDL description for the Boolean expression. X=A+BC+B'D; Y=B'C+BC'D'.
6. Write HDL code for 8 x 1 MUX.
7. Construct VHDL module for a JK fli p-flop.
8. Write the VHDL code for mod-6 counter.
9. Write the VHDL code for 4-bit universal shift register.
10. How is memory modeled in VHDL? Write a VHDL code that illustrates the read and write
operations of memory.
11. Explain the design procedure of RTL using VHDL with an example.
12. Express how arithmetic and logic operations are performed using RTL.
13. Write a note on test benches.
14. Write HDL program for full-adder and 4-bit comparator.
15. Write a HDL behavioral description of JK flip-flop using if-else statement based on the
value of present state.
16. Draw the logic diagram of the following module.
module request (A, B, C, Q, CLK);
input A, B, C, CLK;
output Q;
request Q, E;
always @(posedge CLK)
begin
E<= A & B;
Q<= E/C;
end
end module
Answer:

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 17. Express how arithmetic and logic operations are expressed using RTL.
18. Briefly discuss the different datatypes supported in VHDL.
19. Write the VHDL code for decade counter.
20. Write HDL for 4-bit binary counter with parallel load and explain.
21. Write HDL code for 4-bit adder.
22. Write the VHDL code for 2-to-4 decoder in structural model.
23. Write a VHDL program for an 8-bit comparator and explain the design procedure.
24. Write VHDL code for a master-slave JK flip-flop and using JK flip-flop as structural
element, write the code for 4-bit asynchronous counter.

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