PART – B
1. Explain the Gray code to binary conversion with necessary diagram.
2. Explain the concept, operation and characteristics of TTL family.
3. Explain the concept, operation and characteristics of ECL family.
4. Draw the TTL inverter circuit.
5. Explain the working of 2-input TTL totem-pole NAND gate.
6. Explain the working of 3-input TTL totem-pole NAND gate.
7. Draw the circuit diagram and explain the working of TTL inverter with tristate output.
8. Discuss about TTL parameters.
9. Name and explain the characteristics of TTL family.
10. Draw and explain the NOR gate using TTL logic.
11. Design a TTL logic circuit for a 3-input NAND gate.
12. Explain the concept, operation and characteristics of CMOS technology.
13. Write a short note on CMOS family.
14. Sketch the typical transfer characteristics of a CMOS inverter.
15. Draw the circuit of a CMOS two-input NAND gate and explain its operation.
16. Draw and explain the circuit diagram of a CMOS NOR gate.
17. Explain the concept, operation, characteristics of CMOS family.
18. Explain the characteristics of CMOS family.
19. Draw the MOS logic circuit for NOT gate and explain its operation.
20. Compare the characteristics of TTL, ECL and CMOS logic families.
21. Compare all the IC logic families based on
a. Power consumption
b. Fan-out
c. Power dissipation
d. Propagation delay
e. Switching speed
f. Noise margin
22. Compare the various digital logic families.
23. Write detailed notes on the working and characteristics of ECL and CMOS logic families.
24. Explain the working of (a)TTL NAND gate with open collector output configuration
(b) TTL inverter with tristate output configuration
25. Draw and explain ECL AND gate.
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UNIT 2: COMBINATIONAL CIRCUITS
PART A:
1. Distinguish between completely specified function and incompletely specified function.
2. What is the maximum number of outputs for a decoder with a 6-bit data word?
3. Mention the differences between DEMUX and MUX.
4. What is a priority encoder?
5. Draw a 4 x 16 decoder using two 3 x 8 decoders.
6. Show that
7. Draw the truth table and logic circuit of half adder.
8. State Demorgan's theorem.
9. Why is MUX called as data selector?
10. How does don't care condition in K-map help for circuit simplification?
11. What is the difference between decoder and demultiplexer?
12. Express the following switching circuit in binary logic notations.
(NOTE: Solve PART-B: problem No. 34, 35, 37, 43, 54 using Tabular method or Quine
McCluskey method)
(i) Obtain the sequence of states when X=1, starting from the state ABCD = 0001.
(ii) Obtain the sequence of states when X=0, starting from the state ABCD = 0000.
14. Explain the various steps in the analysis of synchronous sequential circuits with a
suitable example.
15. Minimize the state table shown below:
Next state, 'Z' (output)
Present state X (input)
X=0 X=1
A B,0 C,0
B B,0 D,0
C B,0 C,0
D E,1 C,0
E B,0 D,0
X=0 X=1
A A,0 B,0
B C,0 D,0
C A,0 D,0
D E,0 F,1
E A,0 F,1
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F G,0 F,1
G A,0 F,1
17. Construct reduced state diagram for the following state diagram shown in Fig. 3. 2.
18. (i) Reduce the number of states in the following state table and tabulate the reduced
state table.
Next state output
Present state
X=0 X=1 X=0 X=1
A F B 0 0
B D C 0 0
C F E 0 0
D G A 1 0
E D C 0 0
F F B 1 1
G G H 0 1
H G A 1 0
(ii) Starting from state a, and input sequence 01110010011, determine the output
sequence for the given and reduced state table.
19. For a four bit even parity bit generator, input come serially. The four bits of the input
sequence are to be examined by the circuit and circuit produces a parity bit which is to
be added in the original sequence. The circuit should get ready for receiving another four
bits after producing a parity bit for the last sequence. Draw the state diagram and write
down the state transition table.
20. Design a sequential circuit with 4 FF ABCD. The next states of B, C, D are equal to the
present states of A, B, C respectively. The next state of A is equal to the Ex-OR of the
present states of C and D.
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21. Design a synchronous sequential circuit using JK flip-flop for the given state diagram in
Fig. 3.3.
36. Draw the state transition diagram of a sequence detector circuit that detects '1010' from
input data stream using Moore model, Mealy model.
37. Design a counter using JK flip-flop for realizing the following sequence.
Q2 Q1 Q0
0 0 0
0 0 1
0 1 1
1 1 1
1 1 0
1 0 0
0 0 0
PART B:
1. Design a pulse-mode circuit having two input lines x 1 and x2, and one output line z. The
circuit should produce an output pulse to coincide with the last input in the sequence x1-
x2-x2. No other input sequence should produce an output pulse.
2. Design a pulse-mode circuit having two input lines x1, x2 and x3, and one output line z.
The output should change from 0 to 1, only for input sequence x 1-x2-x3 occurs while z=0.
Also the output z should remain in 1 until x 2 occurs. Use SR flip-flop for the design.
3. Derive the flow table for the circuit shown in Fig. 4.1.
4. Consider the following asynchronous sequential circuit as shown in Fig. 4.2 and draw
maps, transition table and state table.
15. Describe the steps involved in design of asynchronous sequential circuit in detail with an
example.
16. Define asynchronous sequential circuit, cycles, races, critical races and non-critical
races.
17. When do you get the critical and non-critical races? How will you obtain race free
condition?
18. Describe with reasons, the effect of races in asynchronous sequential circuit design.
Explain its types with illustrations. Show the method of race-free state assignments with
examples.
19. List and explain the steps used for analyzing an asynchronous sequential circuit.
20. Find a way to remove the hazard in product of sum expression given by,
21. What ate hazards in sequential circuits? How can they be eliminated?
22. Explain the various types of hazards in sequential circuit design and the methods to
eliminate them. Give suitable examples.
23. Design a combinational circuit using ROM. The circuit accepts 3-bit number and
generates an output binary number equal to square of input number.
24. Design a ROM for the following functions. ;
25. Draw a PLA circuit to implement the logic functions. and
26. Design a combinational circuit using PLA. The circuit accepts 3-bit number and
generates an output binary number equal to square of input number.
27. Implement the following Boolean functions using PLA. ;
UNIT 5: VHDL
PART A:
1. What is the need for VHDL?
2. What are the operators present in VHDL?
3. Write VHDL code that illustrates the read and write operations of memory.
4. When can RTL be used to represent digital systems?
5. What are the modeling techniques in HDL?
6. Write HDL code for half-adder.
7. What are the advantages of hardware languages?
8. Write VHDL code for half-adder in data flow model.
9. Write VHDL code for 2 x 1 MUX.
10. What are the advantages of package declaration over component declaration?
11. Write the VHDL code for AND gate.
12. What is the meaning of the following statements in RTL? T 1: ACC <- ACC and MDR.
13. Write the behavioral model of D flip-flop.
14. Define RTL.
15. What is meant by package?
16. What are miscellaneous operators?
17. Define entity in a VHDL module.
18. Define architecture in a VHDL module.
19. What is data flow model?
20. What is structural model?
21. What is behavioral model?
22. What is test bench?
PART B:
1. Discuss briefly the use of 'packages' in VHDL.
2. Explain the concept of behavioral and structural modeling in VHDL. Take an example of
full-adder and write codes for both type of modeling.
3. List and briefly explain the different data types supported in VHDL.