2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems
Compact Implementations of FPGA-Based PUFs
with Enhanced Performance
N. Nalla Anandakumar Mohammad S. Hashmi
Hardware Security Research Group Department of ECE
SETS, Chennai, India IIIT Delhi, New Delhi, India
Email: nallaa@iiitd.ac.in Email: mshashmi@iiitd.ac.in
Abstract—The Physically Unclonable Functions (PUFs) are
used in numerous security applications such as device authen-
tication, secret key generation, FPGA intellectual property (IP)
protection, and trusted computing. In this paper, compact im-
plementations of Ring oscillator-based PUF (RO-PUF), Arbiter-
based PUF (A-PUF) and RS Latch-based PUF (RS-LPUF) on an
FPGA (Field Programmable Gate Array) platform are presented.
The proposed schemes provide very competitive area trade-offs
and effectively enable smallest FPGA implementations, reported
so far, of RS-LPUF, RO-PUF, and A-PUF respectively. The
designs have been validated by developing prototypes on Xilinx
Spartan-6 FPGAs at core voltage of 1.2V and normal operating
temperature. Finally, a detailed comparison of statistical analysis
on their performance using measured PUF data have been
carried out. It has been demonstrated that the proposed designs
exhibit significantly improved performance in terms of statistical
properties when compared to the existing works.
Keywords-PUF; PDL; FPGA; RO PUF, Arbiter PUF, RS Latch
PUF;
I. I NTRODUCTION
The security challenges are becoming inherent with the in-
creasing number of ubiquitous computing and communication
devices. An on-chip PUF, concept introduced in [1]- [2], has
the capability to extract unique keys from the intrinsic process
variability of silicon devices, using a challenge and response
mechanism which is extremely hard or impossible to unclone,
and therefore can potentially address such security concerns
in an efficient way.
Silicon PUFs implemented on FPGA platforms are ex-
tremely flexible, secure, cost effective, and offer quick turn-
around. Applications of FPGA based PUFs are diverse and
could be found in IP protection [3], RFIDs [4], secure key
generation [5], and remote activation [6]. There have been
numerous reports of such an implementations, in the past
decade, such as A-PUF [7], RO-PUF [5], SRAM-PUF [3],
Butterfly-PUF [8] and RS-LPUF [9].
In principle, A-PUF is composed of two identically con-
figured delay paths which are stimulated by an activating
signal and subsequently the output is generated using the
arbiter according to the propagation delay of the signal in the
two delay paths. In the RO-PUF, the difference in oscillator
frequencies of selected pairs of ring-oscillators generate the
PUF response. The SRAM-PUF utilize the unstable power-
up values of SRAMs while the Butterfly-PUF works as the
2380-6923/16 $31.00 © 2016 IEEE
DOI 10.1109/VLSID.2017.7
Somitra Kumar Sanadhya
Department of CSE
IIIT Delhi, New Delhi, India
Email: somitra@iiitd.ac.in
SRAM-PUF having two cross-coupled latches. The most re-
cent RS-LPUF is based on the location information of the
random latches and the practical advantage of it over SRAM-
PUF is that its behavior does not rely on a power-up condition.
Furthermore, programmable delay line (PDL) based FPGA
PUF [10] also possess the potential for on-chip applications.
In this paper, effective approach for three distinct FPGA
based PUFs design are being reported where they make use
of programmable delay lines in conjunction with A-PUF, RO-
PUF, and RS-LPUF respectively to generate higher probability
of random variations. In summary, the key contributions of this
paper are as follows:
• Compact design of A-PUF, RO-PUF, and RS-LPUF on
a Xilinx Spartan-6 FPGAs (XC6SLX45-3CSG324) are
proposed. The programmable delays of FPGA LUTs have
been used to achieve more random process variations.
• The Obtained results from these designs have been com-
pared with existing FPGA based PUFs in terms of area.
It has been demonstrated that the proposed RS-LPUF
requires only 54 slices, RO-PUF requires 82 slices, and
A-PUF requires 234 slices to generate 256 bit response
on Xilinx Spartan-6 device. These results represent the
most compact A-PUF, RO-PUF, and RS-LPUF imple-
mentations on FPGAs and are potential candidates for
light-weight secure applications.
• The obtained performance have been evaluated by consid-
ering the PUF parameters based on statistical properties
of PUF responses.
In the subsequent sections, Xilinx Spartan-6 FPGAs, PDLs,
and important PUF quality metrics are briefly discussed and is
followed by implementation details of A-PUF, RO-PUF, and
RS-LPUF. This is succeeded by discussion on implementa-
tion results along with area comparisons with the existing
techniques, and discussion on experimental results and the
associated validation. Finally, the paper concludes with some
remarks on the future possibilities.
II. P RELIMINARIES
A. Xilinx Spartan-6 FPGAs
Spartan-6 FPGAs from Xilinx, composed of array of config-
urable logic Blocks (CLBs), have been used to build RO-PUF,
RS-LPUF, and A-PUF. This FPGA has three different types of
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CLB slices, namely SliceM, SliceL, and SliceX. In this, each
CLBs consist of two slice types where one slice is either a
SliceM or SliceL and the other is always a SliceX. Moreover,
a slice contains four 6-input lookup-tables (LUTs) and eight
flip-flops (FFs). In this paper, the LUT primitives have been
instantiated in HDL for Spartan-6 which are described in the
Spartan-6 Libraries Guide for HDL Designs [11].
B. Programmable delay lines (PDLs)
The internal variations of FPGA Look-Up Tables (LUTs)
can be generated from the changes in LUTs propagation delays
under different inputs [10], [12]. For example, the LUT in
Fig. 1 [12] is programmed to implement an inverter whose
LUT output (O) is always an inversion of its first input (A1 ).
The other inputs A2 and A3 of LUT act as “don’t-care” bits
but their values affect the signal proposition path from A1 to
the output (O). In this context, it has been shown, Fig. 1 [12],
that the signal propagation path from A1 to the output (O) is
shortest for A2 A3 = 00 and longest for A2 A3 = 11 for 3-
input LUTs. However, this paper makes use of Xilinx Spartan
6 devices having 6-input LUTs that can allow implementation
of fine PDLs. For clarity, it is pertinent to be aware about the
possibility of realization of fine PDL and coarse PDL, shown
in Fig. 2, on the Spartan-6 FPGAs. For the implementation of
the fine PDL, the LUT inputs A3 to A6 are fixed to 0 and the
only input that controls the delay is A2. For the coarse PDL,
all of the LUT inputs are tied and controlled together [12].
Fig. 1: PDL using a 3-input LUT [12].
Fig. 2: Fine and coarse PDLs implemented by a single 6-input
LUT [12].
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C. PUF Properties
In general, uniqueness, reliability, and uniformity are
the three major quality matrics (statistical properties) for
PUFs [13].
1) Uniqueness measures the variation of responses obtained
from different PUF instances for the same set of challenges.
If Xi and Xj are the n-bit responses of ith and jth PUF
instances respectively then the uniqueness is expressed as:
k−1 k
2   HD(Xi , Xj )
U niqueness = × 100%
k(k − 1) i=1 j=i+1 n
where k is number of PUF instances (tested devices).
2) Reliability determines how efficiently a PUF can generate
the same response at different operating condition (ambient
temperatures or supply voltages) over a period of time for
a given challenge. The reliability is calculated using the
following equation:
 s

1  HD(Xi , Xi,t )
Reliabilityi = 1− × 100%
s t=1 n
where HD(Xi , Xi,t ) is the Hamming distance of n-bit
reference response Xi of chip i with Xi,t . Where the terms
Xi,t is the response generated at time t, and s is the number
of response of same set of challenges.
3) Uniformity determines how uniform the proportion of 0’s
and 1’s are in the PUF response and is calculated by:
n
1
U nif ormityi = ri,j × 100%
n j=1
where ri,j is jth bit of n-bit response of PUF instance i.
III. D ESIGN AND I MPLEMENTATIONS
This section includes optimized design and implementa-
tions of A-PUF, RO-PUF, and RS-LPUF along with their
performance assessments on Xilinx Spartan-6 FPGAs. This
FPGA is developed in 45 nm technology and is specifically
appropriate for embedded applications. These designs have
been developed by using Xilinx ISE design suite 14.5 and
coded in VerilogHDL.
A. RO-PUF
In [14] and [15], RO-PUFs were implemented on Xilinx
Spartan-3E devices with each RO placed in four slices in one
CLB. In the proposed design here, RO-PUF incorporating fine
PDL and implemented on Xilinx Spartan-6 devices, where 2
ROs are implemented inside a single CLB but each RO placed
in a single slice, is presented.
Here, each Ring oscillator (RO) is realized using 3 inverters
and 1 AND gate as can be seen in Fig. 3 (black dash lines).
For the design of inverters and AND gate, three LUTs and one
LUT has been utilized respectively. The AND gate is being

Fig. 3: The proposed design of RO-PUF.
Fig. 5: PUF array con-
Fig. 4: Implementation of figuration of 32 ROs on
2 ROs per CLB. Spartan-6 device
used for enabling the RO. Two ROs are implemented inside
a single CLB, where each RO is implemented inside a single
slice of CLB as shown in Fig. 4, each with a different color
scheme. In this design, 32 ROs are configured at the center
of a chip in a 4 × 4 matrix of CLBs as shown in red in
Fig. 5. The hard macro technique to place them at selected
locations in order to make all the ROs identical has been used.
In order to generate programmable delays inside the 6-input
LUT, one LUT-input is the ring connection while one other
input is essentially the challenge bit. All other remaining LUT-
inputs are fixed to zero. In addition, it is important to note that
one of the input to the LUT of AND gate is used for enabling
the RO (see Fig. 3).
The architecture of the proposed RO-PUF, given in Fig. 3,
implemented on Xilinx Spartarn-6 FPGA device starts with
initiation of 8-bit master challenge from a user PC (Matlab)
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through a UART interface to the 8-bit Galois LFSR and
that generates the 256 subsequent challenges. Then from
each of these subchallenges two different ROs are chosen
for comparison. The subchallenges consist of two parts: the
4 least significant bits (LSB) select one of the 16 ROs in
group 1 through the multiplexer 1 while the 4 most significant
bits (MSB) of the subchallenge select one of the 16 ROs
in group 2 through the multiplexer 2. The frequency of the
selected ROs in group 1 and group 2 are then obtained and fed
into the 32-bit respective counters. A crystal 100 MHz clock
signal generated by an on-board oscillator drives the 8-bit
reference counter. The counter 1, counter 2, and the reference
counter start counting at the same time and are forced to
stop when reference counter hits its maximum value. Then,
the comparison of counter 1 and counter 2 values generates
a response bit 0 or 1 for this RO pair depending on which
counter had the higher value. Subsequently, the generated
response is stored in a 256-bit shift register. In this case,
therefore, 256 response bits are generated for each 8-bit master
challenge. Finally, the generated response bits are sent to the
PC using a UART 8-bit interface for the PUF performance
analysis. The controller circuitry is responsible for starting and
stopping the ROs using the enable input, the ROs selection,
counting the oscillations, and returning the responses based on
their comparisons.
B. RS-LPUF
[9] and [16] provide the implementations of SR-latch based
PUF on Xilinx Spartan-6 FPGA device. In [9], PUF response
determines the final state of the output patterns (all zeros, all
ones, or a combination of zeros and ones) of each latch by
applying consecutive rising edges. If the final output (1000
repetitions of the experiment) patterns are all zeros then the
corresponding response bits are 00. Similarly, if the final
output patterns are all ones then the corresponding response
bits are 11 and if the final output patterns combine ones and
zeros then the corresponding response bits are 10. In [16], PUF
response is determined using the exact number of oscillations
at the output of each latch during the metastable state by
applying a rising-edge at a control signal. In the current work,
the PUF response is derived from the difference in counting the
numbers of 1’s of the selected pairs of RS-LPUFs by applying
a consecutive rising edges and the concept is similar to the
proposed RO-PUF.
The implementation reported in [9] has two NAND gates
and one FF (for each SR-latch) implemented in same kinds
of slices on different CLBs. On the other hand, the design
in [16] has two NAND gates and two FFs (for each SR-
latch) implemented on different kinds of slices on the same
CLB. In the current work, two NAND gates and one FF (for
each SR-latch) are implemented in a single slice on one CLB
shown in Fig. 6. Moreover, In this work only 32 RS latches
for generating the 256 response bits are used whereas the
designs in [9] and [16] require 128 RS latches and 512 latches
respectively. Additionally, the proposed approach employs the
concept of PDL in the design of PUF for improving the
random response.
Fig. 6: Implementation of 4 RS latches per CLB
Fig. 7: RS-LPUF design.
In the proposed work, an SR-latch is created from two LUTs
and one flip-flop (FF) as shown in Fig. 6. Two LUTs are
used to create NAND gates while the FF in front of the two
NAND gates is used to reduce the clock skew. Furthermore,
four latches are implemented inside a single CLB whereas two
RS Latches are implemented inside similar type of CLB slice
using hard macro, shown in Fig. 6, each with a different color
scheme.
These slices are placed manually at predefined location
with predefined connections to minimize the skew of internal
signals. In order to generate programmable delays inside the
6-input LUT, 3 inputs of each LUT are used for connection
purposes such as FF output, another LUT output, and one
challenge bit while the remaining LUT-inputs are fixed to zero.
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The proposed RS-LPUF architecture is shown in Fig. 7. In
this design, 32 RS latches are configured at the center of a chip
in a 4 × 2 matrix of CLBs. A 100-MHz clock signal generated
by an on-board oscillator is applied to each FF, which divides it
into a 50-MHz clock signal that is applied to corresponding RS
latches. The D-type FF acts as frequency divider by feeding
back the output from Q to the input terminal D, the output
pulses at Q have a frequency that are exactly one half that
of the input clock frequency (see Fig. 7). The RS Latches are
enabled and stopped using the enable signal of the architecture
and before applying the enable signal the flip-flop (FF) is reset.
It is done to ensure that the latches always start with the same
initial state. In this design, similar to the RO-PUF approach,
the generation of 256 subsequent challenges and selection of
2 SR-latches are done in 2 groups based on the subsequent
challenge inputs.
As per the architecture, RS latch output is 1 when input
is 0 in a stable state. When input of the RS latch changes
from 0 to 1 (i.e., the rising edge), the RS latch temporarily
enters a metastable state. It then enters a stable state with either
output 0 or 1. In every clock cycle, the outputs of selected RS
latches in group 1 and group 2 are fed into the 8-bit counters
1 and 2 respectively. Then both counter value is incremented
every time selected RS latches output 1’s. The counter 1,
counter 2, and 8-bit reference counter start counting at the
same time and are forced to stop when reference counter hits
its maximum value. The comparison of counter 1 and counter
2 values generate a response bit 0 or 1 for this RS latch pair,
depending on which counter had the higher value. Finally, the
generated response is stored in a 256-bit shift register. In this
case, 256 response bits are generated for each 8-bit master
challenge which are then sent to the PC using a UART 8-bit
interface for the PUF performance analysis.
C. A-PUF
In [10], PDL based A-PUF is presented on Xilinx Virtex 5
FPGA device. The design of the switching elements in PDL
based A-PUF uses non-swapping path based switches instead
of path-swapping switches to cancel out the delay skews
caused by asymmetries in routing on FPGAs. In their design,
the PDL (top and bottom part of switch) is implemented by 2
LUTs each acting as an inverter. The 2 LUTs are implemented
in same kinds of slices on different CLB. They placed 16
PUF instances in parallel on the FPGA to produce 16 bits of
responses per challenge, where each PUF instance consists of
64 stages of PDLs. Finally, the PUF responses are determined
to apply 1000 random challenges to the PUF instances. If
more than half of the responses are 1’s, the PUF response
is considered 1, and 0 otherwise. On the other hand, the
current work proposed in this paper utilizes the proposed RO-
PUF design approach where PUF response is derived from
the difference in counted 1’s between the selected pairs of
PUF instances from 32 PUF instances by applying rising clock
edges. It is imperative to note that each PUF instance here
consists of 8 stages of PDLs. The PDL is implemented by 2
LUTs each acting as buffer and the 2 LUTs are implemented
in different slice on the same CLB (see Fig. 8).
Fig. 8: Implementation of one PUFI on the 3 CLBs.
Fig. 9: A-PUF design.
The 32 PUF instances (PUFI) are implemented in 32 × 3
matrix of FPGA CLBs with each PUFI consisting of 8 stages
of buffer and one arbiter which connects the last stage of the
two paths. So, each PUFI uses 16 LUTs (i.e., 2 CLBs) for
buffers and one FF (i.e., 1 CLB) for arbiter shown in gray
in Fig. 8. The top (in blue box) and bottom (in green box)
paths are identical but are independent. Once again, these
slices are placed using hard macro with a predefined location
and connections. In order to generate programmable delays
inside the 6-input LUT, one LUT-input is the path while one
other input is essentially the challenge bit. All other remaining
LUT-inputs are fixed to zero.
The proposed A-PUF architecture is shown in Fig. 9. In
this design, similar to the RO-PUF approach, the generation
of 256 subsequent challenges and selection of 2 PUFIs are
done in 2 groups based on the subsequent challenge inputs.
Each of the generated subsequent challenge is then applied to
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configured delay paths of the PUFIs (see Fig. 9). A 100-MHz
clock signal generated by an on-board oscillator is also applied
to the PUFIs. In every clock cycle, the outputs of a selected
PUFI in group 1 and group 2 are fed into the 8-bit counters 1
and 2 respectively. Then both counter value is incremented
every time the selected PUFIs outputs 1’s. The counter 1,
counter 2, and the 8-bit reference counter start counting at
the same time and are forced to stop when reference counter
hits its maximum value. Next, the comparison of counter 1 and
counter 2 values generates a response bit 0 or 1 for this PUFIs
pair, depending on which counter had the higher value. Finally,
the generated response is stored in a 256-bit shift register. As
a result, 256 generated response bits for each 8-bit master
challenge are sent to the PC for PUF response analysis.
IV. A NALYSIS AND D ISCUSSION
At first, the proposed architectures developed on Spartan-6
boards were compared with the existing state-of-the-art and
the obtained results are presented in Table I. It is apparent
from the results that the number of CLBs required for rings
in the proposed RO-PUF is substantially lower than the other
recently reported RO-PUFs [14], [15]. One can also see that
the proposed RO-PUF implementation outperforms [17] on the
same FPGA device in term of area.
It is also evident from the results in Table I that the number
of CLBs required for the RS Latches configuration in the
proposed RS-LPUF is much lower than other RS-LPUFs [9],
[16]. One can, therefore, easily identify that the proposed RS-
LPUF implementation outperform other reported works [9],
[16] in term of area.
Furthermore, it can also be seen in the Table I that the
number of CLBs required for the PUFIs configuration in
the proposed A-PUF are much lower than other reported A-
PUF [10]. Once gain, the proposed A-PUF implementation
outperforms other A-PUF [18] in terms of area.
For the performance evaluation in terms of uniqueness,
uniformity, and reliability, the proposed design schemes have
been implemented on five Spartan-6 (XC6SLX45) FPGAs at
normal operating conditions. The results of the evaluation of
the proposed designs along with the data for existing state-of-
the-art are reported in Table II. Following observations can be
deduced from the obtained results:
1. It can be inferred that the proposed RO-PUF outperforms
all the previous RO-PUFs [13]–[15] in terms of reliability. The
results are much improved in terms of uniqueness and unifor-
mity values and are closer to ideal values when compared to
other RO-PUFs [13], [14].
2. For RS-LPUF, the Table II conveys that the proposed
RS-LPUF exhibits much better performance when compared
to previous RS-LPUFs [9], [16] in terms of reliability. The
uniqueness values obtained for the proposed design is closer
to the ideal value as well.
3. Finally, for the A-PUF, it can be seen in the Table II that
the proposed design shows much better performance compared
to the other A-PUFs [13] in term of uniqueness while the
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